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^Ir TeIXAS 

Instruments 


TMS370 Family 


• Data Manual 

i 



1988 



8-Bit Microcontroller Family 



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icrocontroller 

Technical Bulletin Board 

Hotline Service 

71 3 274-2370 71 3 274-3700 



Introduction 



TMS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module ■£ 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information ■[£ 



Appendixes 



TMS370 Family 
Data Manual 



^ 



Texas 
Instruments 



IMPORTANT NOTICE 

Texas Instruments (Tl) reserves the right to make changes to or to discontinue 
any semiconductor product or service identified in this publication without 
notice. Tl advises its customers to obtain the latest version of the relevant in- 
formation to verify, before placing orders, that the information being relied 
upon is current. 

Tl warrants performance of its semiconductor products to current specifica- 
tions in accordance with Tl's standard warranty. Testing and other quality 
control techniques are utilized to the extent Tl deems necessary to support this 
warranty. Unless mandated by government requirements, specific testing of 
all parameters of each device is not necessarily performed. 

Tl assumes no liability for Tl applications assistance, customer product design, 
software performance, or infringement of patents or services described herein. 
Nor does Tl warrant or represent that license, either express or implied, is 
granted under any patent right, copyright, mask work right, or other intellec- 
tual property right of Tl covering or relating to any combination, machine, or 
process in which such semiconductor products or services might be or are 
used. 



Copyright © 1988, Texas Instruments Incorporated 



Contents 



Section Page 

1 Introduction 1-1 

1.1 TMS370 Overview 1-2 

1 .2 TMS370 Architecture Overview 1-4 

1.3 Manual Organization 1-7 

1.4 Symbols and Conventions 1-8 

1.5 Applicable Documents 1-8 

2 TMS370 Family Devices 2-1 

2.1 Summary and Device Comparison 2-2 

2.2 TMS370Cx10 Features 2-3 

2.3 TMS370Cx50 Features 2-4 

2.4 TMS370 Family Pinouts/Pin Descriptions 2-6 

2.4.1 TMS370Cx10 Pinouts 2-6 

2.4.2 TMS370Cx10 Pin Descriptions 2-7 

2.4.3 TMS370Cx50 Pinouts 2-8 

2.4.4 TMS370Cx50 Pin Descriptions 2-9 

3 CPU and Memory Organization 3-1 

3.1 CPU/Register File Interaction 3-2 

3.2 CPU Registers 3-3 

3.2.1 Stack Pointer (SP) 3-3 

3.2.2 Status Register (ST) 3-4 

3.2.3 Program Counter 3-5 

3.3 Memory Map 3-6 

3.3.1 Register File .. 3-7 

3.3.2 Peripheral File 3-9 

3.3.3 Data EEPROM Module 3-11 

3.3.4 Program Memory 3-11 

3.4 Memory Operating Modes 3-13 

3.4.1 Microcomputer Single-Chip Mode (all TMS370 devices) 3-14 

3.4.2 Microcomputer Mode w/External Expansion (TMS370Cx50) 3-16 

3.4.3 Microprocessor Mode without Internal Memory 3-19 

3.4.4 Microprocessor Mode with Internal Program Memory 3-20 

3.4.5 Memory Mode Summary 3-22 

4 System and Digital I/O Configuration 4-1 

4.1 System Configuration 4-2 

4.1.1 Privilege Mode 4-2 

4.1.2 Oscillator Fault 4-3 

4.1.3 Automatic Wait States 4-3 

4.1.4 Powerdown and Idle Modes 4-4 

4.1.5 System Control Registers 4-7 

4.2 Digital I/O Configuration 4-11 

4.2.1 Microcomputer Mode 4-16 

4.2.2 Microprocessor Mode 4-16 



III 



5 Interrupts and System Reset 5-1 

5.1 Interrupts 5-2 

5.1.1 Interrupt Operation 5-2 

5.1.2 External interrupts 5-5 

5.1.3 Interrupt Control Registers 5-8 

5.1.4 Multiple Interrupt Servicing 5-11 

5.2 Resets 5-12 

6 EEPROM Modules 6-1 

6.1 Data EEPROM Module 6-2 

6.1.1 Control Registers 6-2 

6.1.2 Programming the Data EEPROM . 6-5 

6.1.3 Write Protection Register Operation 6-8 

6.2 Program EEPROM Module 6-9 

6.2.1 Program EEPROM Control Register (PEECTL) 6-10 

6.2.2 Programming the Program EEPROM 6-11 

6.2.3 Write Protection of Program EEPROM 6-12 

7 Timer 1 Module 7-1 

7.1 Timer 1 Overview 7-2 

7.1.1 Introduction 7-2 

7.1.2 Major Components 7-3 

7.1.3 Operating Modes Overview 7-6 

7.2 Timer 1 -16-Bit, General Purpose Timer 7-7 

7.2.1 General-Purpose-Timer Operating Modes 7-7 

7.2.2 Clock Prescaler/External Clock Source 7-11 

7.2.3 Edge Detection 7-13 

7.2.4 General Purpose Counter 7-14 

7.2.5 Compare Register 7-14 

7.2.6 Capture/Compare Register 7-15 

7.2.7 Interrupts 7-16 

7.3 Watchdog Timer 7-17 

7.3.1 Watchdog Counter 7-17 

7.3.2 Power-up RESET 7-19 

7.3.3 Reset Frequency 7-20 

7.3.4 Overflow Flag 7-20 

7.4 Low- Power Modes 7-21 

7.4.1 Halt 7-21 

7.4.2 Standby 7-21 

7.5 Control Registers 7-22 

7.5.1 Timer 1 Counter Control Register 1 7-24 

7.5.2 Timer 1 Counter Control Register 2 7-25 

7.5.3 Timer 1 Counter Control Register 3 7-27 

7.5.4 Timer 1 Counter Control Register 4 7-29 

7.5.5 Timer 1 Port Control Registers 7-31 

7.5.6 Timer 1 interrupt Priority Control Register 7-33 



IV 



8 Timer 2 Module 8-1 

8.1 Timer 2 Overview 8-2 

8.2 Timer 2 Operation 8-5 

8.2.1 Operation iVIodes 8-5 

8.2.2 Clock Sources 8-8 

8.2.3 Timer 2 Edge Detection Circuitry 8-9 

8.2.4 1 6- Bit Resettable Up Counter 8-10 

8.2.5 Compare Register 8-10 

8.2.6 Capture Register (Dual Capture iVIode only) 8-11 

8.2.7 Capture/Compare Register 8-11 

8.2.8 Timer-2 I/O Pin Functions 8-12 

8.2.9 Timer 2 Interrupts 8-12 

8.2.10 Power-Down Modes 8-13 

8.3 Timer 2 Control Registers 8-14 

8.3.1 Timer 2 Control Register 1 8-16 

8.3.2 Timer 2 Control Register 2 8-17 

8.3.3 Timer 2 Control Register 3 8-19 

8.3.4 Timer 2 Port Control Registers 8-21 

8.3.5 Timer 2 Interrupt Priority Control Register 8-23 

9 Serial Communications Interface (SCI) Port 9-1 

9.1 SCI Overview 9-2 

9.1 .1 Physical Description 9-2 

9.1.2 SCI Features 9-4 

9.1.3 SCI Formats and Operation Modes 9-5 

9.1 .4 SCI Control Registers 9-6 

9.2 SCI Operation 9-7 

9.2.1 SCI Programmable Data Format 9-7 

9.2.2 SCI Port Interrupts 9-7 

9.2.3 SCI Clock Sources 9-8 

9.2.4 SCI Communications Modes 9-9 

9.2.5 SCI Multiprocessor Communications 9-13 

9.2.6 SCI Initialization Examples 9-16 

9.3 SCI Control Registers 9-19 

9.3.1 Communication Control Register (SCICCR) 9-20 

9.3.2 Control Register (SCICTL) 9-22 

9.3.3 Baud Select Registers (BAUD MSB and BAUD LSB) 9-24 

9.3.4 Transmitter Interrupt Control and Status Register (TXCTL) 9-25 

9.3.5 Receiver Interrupt Control and Status Register (RXCTL) 9-26 

9.3.6 Receiver Data Buffer Register (RXBUF) 9-28 

9.3.7 Transmit Data Buffer Register (TXBUF) 9-28 

9.3.8 Port Control Register 1 (SCIPC1) 9-29 

9.3.9 Port Control Register 2 (SCIPC2) 9-30 

9.3.10 Priority Control Register (SCIPRI) 9-31 



10 Serial Peripheral Interface (SPI) Module 10-1 

10.1 Serial Peripheral Interface (SPI) Module Overview 10-2 

10.1.1 Physical Description 10-2 

10.1.2 SPI Control Registers 10-4 

10.2 SPI Operation 10-5 

10.2.1 SPI Data Format 10-6 

10.2.2 SPI Interrupts 10-6 

10.2.3 SPI Clock Sources 10-7 

10.2.4 SPI Operation Modes 10-7 

10.2.5 Initialization 10-8 

10.2.6 SPI Example 10-9 

10.3 SPI Control Registers 10-10 

10.3.1 SPI Configuration Control Register 10-11 

10.3.2 SPI Operation Control Register 10-13 

10.3.3 Serial Input Buffer (SPIBUF) 10-14 

10.3.4 Serial Data Register (SPIDAT) 10-14 

10.3.5 Port Control Registers 10-15 

10.3.6 SPI Interrupt Priority Control Register (SPIPRI) 10-17 

11 Analog-To-Digital Converter Module 11-1 

11.1 Analog-To- Digital Converter (A/D) Overview 11-2 

11.1.1 A/D Physical Description 11-2 

11.1.2 A/D Control Registers 11-4 

11.2 A/D Operation 11-5 

11.2.1 A/D Input/Output Pins 11-5 

11.2.2 A/D Sampling Time 11-5 

11.2.3 A/D Conversion 11-5 

11.2.4 A/D Interrupts 11-6 

11.2.5 A/D Programming Considerations 11-7 

11.3 A/D Example Program 11-8 

11.4 A/D Control Registers 11-10 

11.4.1 Analog Control Register (ADCTL) 11-11 

11.4.2 Analog Status and Interrupt Register, (ADSTAT) 11-13 

11.4.3 Analog Conversion Data Register (ADDATA) 11-13 

11.4.4 Analog Port E Data Input Register (ADIN) 11-14 

11.4.5 Analog Port E Input Enable Register (ADENA) 11-14 

11.4.6 Analog Interrupt Priority Register (ADPRI) 11-15 

12 Assembly Language instruction Set 12-1 

12.1 Instruction Operation 12-2 

12.2 Addressing Modes 12-3 

12.2.1 General Addressing Modes 12-4 

12.2.2 Extended Addressing Modes 12-10 

12.2.3 Additional Addressing Modes 12-17 

12.3 Instruction Set Overview 12-18 

12.4 Instruction Set Descriptions 12-29 



VI 



13 Design Aids 13-1 

13.1 Microprocessor Interface Example 13-2 

13.1.1 Read Cycle Timing 13-7 

13.1.2 Write Cycle Timing 13-10 

13.1.3 Design Options 13-12 

13.1.4 Software Examples For Bank Switching 13-13 

13.2 Programming with the TMS370 Family 13-15 

13.3 Serial Communications 13-18 

13.3.1 SPI Port Interfacing 13-18 

13.3.2 SCI Port Interfacing 13-19 

13.4 Analog/Digital Converter 13-21 

13.5 Sample Routines 13-22 

13.5.1 T1PWM Pin Setup 13-22 

13.5.2 Clear RAM 13-23 

13.5.3 RAM Self Test 13-23 

13.5.4 ROM Checksum 13-24 

13.5.5 Binary-to-BCD Conversion 13-25 

13.5.6 BCD-To-Binary Conversion 13-25 

13.5.7 BCD String Addition 13-26 

13.5.8 Fast Parity 13-27 

13.5.9 Bubble Sort 13-27 

13.5.10 Table Search 13-28 

13.5.11 16-by-16 (32- Bit) Multiplication 13-29 

13.5.12 Keyboard Scan 13-29 

13.5.13 Divide 1 13-31 

13.5.14 Divide Instruction 2 13-31 

14 Development Support 14-1 

14.1 The Assembly Language Tools 14-2 

14.1.1 The Assembler 14-3 

14.1.2 The Linker 14-3 

14.1.3 TheArchiver 14-5 

14.1.4 Code Conversion Utility 14-5 

14.2 TheXDS System 14-6 

14.2.1 XDS System Configuration Requirements 14-7 

14.2.2 The Debugger Function 14-8 

14.2.3 Breakpoint/Trace/Timing Functions 14-11 

14.2.4 XDS System Operating Considerations 14-16 

14.3 TheTI EEPROM Programmer 14-17 

14.4 Prototyping/Preproduction Devices 14-19 

15 Electrical Specifications 15-1 

15.1 TMS370Cx10 Specifications 15-2 

15.2 TMS370Cx50 Specifications 15-10 



VII 



16 Customer Information 16-1 

16.1 Mask ROM Prototype and Production Flow 16-2 

16.2 Mechanical Package Information 16-5 

16.3 TMS370 Family Numbering and Symbol Conventions 16-9 

16.3.1 Device Prefix Designators 16-9 

16.3.2 Device Numbering Convention 16-10 

16.3.3 Device Symbols 16-10 

16.4 Development Support Tools Ordering Information 16-13 

16.4.1 TMS370 Macro Assembler, Linker, and Utilities 16-13 

16.4.2 TMS370 EEPROM Programmer 16-13 

16.4.3 TMS370 XDS System 16-13 

16.4.4 Complete TMS370 Development System 16-13 

A Peripheral File Map A-1 

B Character Sets B-1 

C Opcode/Instruction Cross Reference C-1 

D Instruction/Opcode Cross Reference D-1 

E Glossary E-1 



VIM 



Illustrations 



Figure Page 

1-1 TMS370 Block Diagram 1-4 

2-1 PinoutsforTMS370C010, andTMS370C810 2-6 

2-2 PinoutsforTMS370C050andTMS370C850 2-8 

3-1 Register File 3-2 

3-2 Stack Example 3-3 

3-3 Program Counter After Reset 3-5 

3-4 TMS370 Memory Map 3-6 

3-5 Register File Addresses 3-7 

3-6 Microcomputer, Single Chip Mode 3-1 5 

3-7 Microcomputer Mode with Function A Expansion 3-17 

3-8 Microcomputer Mode with Function B Expansion 3-18 

3-9 Microprocessor Mode without Internal Memory 3-19 

3-10 Microprocessor Mode with Internal Program Memory 3-21 

3-1 1 Memory Operating Modes 3-23 

4-1 System Configuration and Control Registers 4-2 

4-2 Digital Port Control Registers 4-11 

4-3 Port Control Register Operation 4-12 

4-4 Port Configuration Registers Set- Up 4-13 

4-5 System Interface Example 4-17 

5-1 Interrupt Control 5-3 

5-2 Peripheral File Frame 1 - External Interrupt Control Registers 5-5 

5-3 Interrupt 1 Block Diagram 5-6 

5-4 Interrupts 2 and 3 Block Diagram 5-7 

5-5 Typical Reset Circuit 5-14 

6-1 Write Protection Bits 6-3 

6-2 EEPROM Programming Example 6-6 

7-1 Timer 1 Block Diagram 7-4 

7-2 Dual Compare Mode 7-9 

7-3 Capture/Compare Mode 7-10 

7-4 Timer 1 System Clock Prescaler 7-11 

7-5 Pulse Accumulation 7-13 

7-6 Watchdog Timer 7-17 

7-7 Peripheral File Frame 4 - Timer 1 Control Registers 7-23 

8-1 1 6-Bit Programmable General Purpose Timer 2 8-3 

8-2 Timer 2 Memory Map 8-4 

8-3 Dual Compare Mode 8-6 

8-4 Dual Capture Mode 8-7 

8-5 Timer 2 Clock Sources 8-8 

9-1 SCI Block Diagram 9-3 

9-2 SCI Data Frame Formats 9-7 

9-3 Asynchronous Communication Format 9-9 

9-4 Isosynchronous Communication Format 9-10 

9-5 SCI RX Signals in Communication Modes 9-1 1 

9-6 SCI TX Signals in Communications Modes 9-12 

9-7 Idle Line Multiprocessor Communication Format 9-14 

9-8 Double- Buffered WUT and TXSHF 9-15 

9-9 Address Bit Multiprocessor Communication Format 9-16 

1 0-1 SPI Block Diagram 10-3 

10-2 SPI Master/Slave Connection 10-5 



IX 



1 0-3 SPI Control Registers 10-10 

1 1 -1 Analog-to- Digital Converter Block Diagram 11-3 

1 1 -2 Ratiometric Conversion Example 11-6 

1 1 -3 Peripheral File Frame 7: A-to-D Converter Control Registers 11-10 

12-1 Implied Operand Addressing Mode 1 2-4 

1 2-2 Register Addressing Mode 1 2-5 

1 2-3 Peripheral Addressing Mode 1 2-6 

1 2-4 Immediate Addressing Mode 1 2-7 

1 2-5 Program Counter Relative Addressing Mode 1 2-8 

1 2-6 Stack Pointer Relative Addressing Mode 12-9 

1 2-7 Absolute Direct Addressing Mode 12-11 

1 2-8 Relative Direct Addressing Mode 12-11 

1 2-9 Absolute Indexed Addressing Mode 12-12 

12-10 Relative Indexed Addressing Mode 12-13 

1 2-1 1 Absolute Indirect Addressing Mode 12-14 

12-12 Relative Indirect Addressing Mode 12-14 

1 2-1 3 Absolute Offset Indirect Addressing Mode 12-15 

12-14 Relative Offset Indirect Addressing Mode 12-16 

13-1 Microprocessor Interface Example 1 3-3 

1 3-2 Valid Address-To- Data Read Timing 13-7 

1 3-3 Chip Select Low To Data Read Timing 13-8 

1 3-4 Chip Select High To Next Data Bus Drive Timing 1 3-9 

1 3-5 Read Data Hold After Chip Select High Timing 13-10 

1 3-6 Write Data Setup Timing 13-11 

1 3-7 Write Data Hold After Chip Select High 13-12 

1 3-8 Master/Slave CPU Interface Example 13-19 

1 3-9 SCI/RS-232 Interface Example 13-19 

13-10 Auto Baudrate Waveform 1 3-20 

1 3-1 1 A/D Converter Sample Applications 1 3-22 

13-12 Keyboard Scan Values . 1 3-29 

1 4-1 Software Developement Flow 1 4-2 

1 4-2 Linker Output Generation 1 4-4 

1 4-3 Typical XDS System Configuration 1 4-7 

1 4-4 XDS Debugger Top Level Screen 1 4-9 

1 4-5 BTT Operation 14-13 

1 4-6 BTT Screen 14-14 

1 4-7 Trace Sample Screen 1 4-1 5 

14-8 Typical EEPROM/UVEPROM Programmer Configuration 14-17 

1 5-1 Recommended Crystal/Clock Connections 1 5-4 

1 5-2 Output Loading Circuit for Test 1 5-4 

1 5-3 XTAL2/CLKIN Measurement Points 15-5 

1 5-4 General Measurement Points 1 5-5 

1 5-5 External Clock Timing 1 5-6 

1 5-6 Switching Time Measurement Points 1 5-6 

1 5-7 SPI Master External Timing 15-8 

1 5-8 SPI Slave External Timing 15-9 

1 5-9 Recommended Crystal/Clock Connections 1 5-1 2 

15-10 Output Loading Circuit for Test 15-12 

1 5-1 1 XTAL2/CLKIN Measurement Points 15-13 

15-12 General Measurement Points 15-13 

15-13 External Clock Timing 15-14 

15-14 Switching Time Measurement Points 15-14 

15-15 External Read Timing 15-16 

15-16 External Write Timing 15-17 

1 5-1 7 SPI Master External Timing 15-18 

1 5-1 8 SPI Slave External Timing 15-19 



15-19 SCI Isosynchronous Mode Timing For Internal Clock 15-20 

1 5-20 SCI Isosynchronous Mode Timing For External Clock 1 5-21 

1 5-21 Analog Timing 1 5-23 

16-1 Prototype and Production Flow 1 6-2 

16-2 28-pin Plastic Dual-Inline Package, 100-MIL Pin Spacing (Type N Package 

Suffix) 16-6 

16-3 28-Pin Plastic- Leaded Chip Carrier Package (Type FN Package Suffix) ... 16-7 

16-4 68-Pin Plastic Leaded Chip Carrier Package (Type FN Package Suffix) 16-8 

1 6-5 Development Flowchart 1 6-9 

1 6-6 TMS370 Family Nomenclature 16-10 

16-7 Tl Standard Symbolization for Mask ROM Device in 28-Pin N-Type Package 16-10 

16-8 Tl Standard Symbolization for Mask ROM Device in 28- Pin FN Type Package 16-11 

1 6-9 Tl Standard Symbolization for Mask ROM Device in 68-Pin FN Type Package 1 6-1 1 

16-10 Tl Standard Symbolization for Program EEPROM Device in N-Type Package 16-11 

16-11 Tl Standard Symbolization for EEPROM Device in FN-Type Package 16-12 

A-1 Interrupt 1 Block Diagram A-6 

A-2 Interrupts 2 and 3 Block Diagram A-6 

A-3 Timer 1 : Dual Compare Mode A-7 

A-4 Timer 1 System Clock Prescaler A-8 

A-5 Timer 1 : Capture/Compare Mode A-9 

A-6 Watchdog Timer A-9 

A-7 Timer 2: Dual Compare Mode A-1 

A-8 Timer 2: Dual Capture Mode A-1 1 

A-9 SCI Block Diagram A-1 2 

A-1 SPI Block Diagram A-1 3 

A-11 Analog-to- Digital Converter Block Diagram A-1 4 

Tables 



Table Page 

1 -1 TMS370 Family Features 1-3 

2-1 TMS370 Family Feature Summary 2-2 

2-2 TMS370Cx50 Feature Summary 2-4 

2-3 TMS370Cx1 Pin Descriptions 2-7 

2-4 TMS370Cx50 Pin Descriptions 2-9 

3-1 Peripheral File Address Map 3-9 

3-2 Vector Address Map 3-11 

3-3 Operating Mode Summary 3-22 

4-1 Privilege-Mode Configuration Bits 4-3 

4-2 Wait State Control Bits 4-4 

4-3 Powerdown/ldle Control Bits 4-5 

5-1 Hardware System Interrupts 5-4 

5-2 Reset Sources 5-1 2 

5-3 Control- Bit States Following Reset 5-13 

7-1 Timer 1 I/O Pin Definitions 7-4 

7-2 Timer 1 and Watchdog Counter Memory Map 7-5 

7-3 Counter Overflow Rates 7-12 

8-1 Timer 2 I/O Pin Definitions 8-12 

8-2 Peripheral File Frame 6: Timer 2 Control Registers 8-15 

9-1 SCI Memory Map 9-6 

9-2 SCI Control Registers 9-19 

9-3 Transmitter Character Bit Length 9-20 



XI 



1 0-1 SPI Memory Map 10-4 

1 0-2 SPI Character Bit Length 10-11 

1 0-3 SPI Clock Frequency 10-12 

1 1 -1 A/D Memory Map 11-4 

1 2-1 Addressing Modes 12-3 

1 2-2 TMS370 Symbol Definitions 12-18 

1 2-3 TMS370 Family Instruction Overview 12-19 

12-4 TMS370 Family Opcode/Instruction Map 12-27 

1 2-5 Compare Instruction Examples - Status Bit Values 1 2-41 

1 3-1 Wait State Control Bits 13-5 

1 3-2 Memory Interface Timing 1 3-6 

15-1 Absolute Maximum Ratings over Operating Free-Air Temperature Range 

(unless otherwise noted) 1 5-2 

1 5-2 Recommended Operating Conditions 1 5-2 

15-3 Electrical Characteristics over Full Range of Operating Conditions 15-3 

1 5-4 External Clocking Requirements 1 5-6 

15-5 General Purpose Output Switching Time Requirements 15-6 

15-6 Recommended EEPROM Timing Requirements For Programming 15-7 

15-7 SPI Master External Timing Characteristics 15-8 

15-8 SPI Master Externa! Timing Requirements 15-8 

1 5-9 SPI Slave External Timing Characteristics 1 5-9 

15-10 SPI Slave External Timing Requirements 15-9 

15-11 Absolute Maximum Ratings over Operating Free-Air Temperature Range 

(unless otherwise noted) 1 5-1 

1 5-1 2 Recommended Operating Conditions 1 5-1 

15-13 Electrical Characteristics over Full Range of Operating Conditions 15-11 

1 5-1 4 External Clocking Requirements 15-14 

15-15 Peripheral Module and General Purpose Output Switching Times 15-14 

15-16 Recommended EEPROM Timing Requirements For Programming 15-15 

15-17 Switching Characteristics and Timing Requirements 15-15 

15-18 SPI Master External Timing Characteristics 15-18 

15-19 SPI Master External Timing Requirements 15-18 

1 5-20 SPI Slave External Timing Characteristics 15-19 

1 5-21 SPI Slave External Timing Requirements 15-19 

15-22 SCI Isosynchronous Mode Timing Charateristics For Internal Clock 15-20 

15-23 SCI Isosynchronous Mode Timing Requirements For Internal Clock 15-20 

15-24 SCI Isosynchronous Mode Timing Charateristics For External Clock 15-21 

15-25 SCI Isosynchronous Mode Timing Requirements For External Clock 15-21 

15-26 A/D Converter Recommended Operating Conditions 15-22 

15-27 A/D Converter Operating Characteristics Over Full Range Of Operating Con- 
ditions 1 5-22 

1 5-28 Analog Timing Requirements 1 5-22 

1 6-1 Package Types 1 6-5 

B-1 ASCII Character Set B-1 

B-2 Control Characters B-2 

C-1 TMS370 Family Opcode/Instruction Map C-2 

D-1 TMS370 Family Instruction/Opcode Set D-2 



XII 



Introduction 



TIVIS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications interface (SCI) Port 



Serial Peripheral Interface (SPI) Module Ml* 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



1. Introduction 



This manual describes the TMS370 family of microcontroller products. The 
objective of the manual is to provide the information needed to implement a 
microcontroller design using a TMS370 device. 

This section gives a broad overview of the TMS370 family covering the 
following topics: 

Section Page 

1 .1 TMS370 Overview 1 -2 

1.2 TMS370 Architecture Overview 1 -4 

1.3 Manual Organization 1-7 

1 .4 Symbols and Conventions 1 -8 

1.5 Applicable Documents 1-8 



1-1 



Introduction 



1.1 TMS370 Overview 



The TMS370 family consists of VLSI, 8-bit, CMOS microcontrollers with 
on-chip EEPROM storage and peripheral support functions. This family of 
microcontrollers provides superior performance in complex real-time control 
applications in demanding environments. With devices available in mask- 
programmable read-only memory (ROM) and electrically-erasable program- 
mable read-only memory (EEPROM), the designer has a significant range of 
options to chose from in deciding the most economical, efficient manner of 
getting a product to market. 

The prototyping and production devices of the TMS370 family are totally 
interchangeable. This reduces development costs and cycle time, and facili- 
tates rapid product modification and upgrade. The alterable non-volatile 
memory (EEPROM) allows a designer to customize his equipment for a spe- 
cific application with quick turnaround. 

The TMS370 family is fully supported by a host of Tl development tools which 
provide simplified software development for quicker market introduction of 
new products. These development support tools include an Assembler, a 
Linker, an In-Circuit emulator (XDS - extended Development Support), and 
an EEPROM/UVEPROM programmer. All of these tools work together using 
an MS™-DOS-based Personal Computer (PC) as the host and central control 
element.1 This allows selection of the host computer and the text management 
and editing tools based on user preference. 



TMS370 FEATURES AND BENEFITS 



FEATURES 
Sub 2-Micron Technology 

Series of compatible devices 
EEPROM Technology 



- Versatile memory 
configurations 

- Programmable Interrupt 
Handling 

- 14 Addressing Modes 



BENEFITS 

- Low power consumption over wide 
temperature range 

- Supports software migration 

- Alterable, non-volatile memory on-chip 
to support in-socket programming and 
form factor emulation 

- Many memory options to meet 
applications requirements 

- Provides design flexibility 



Increases programmer's flexibility 
during software development phase 



i MS is a trademark of Microsoft Corporation. 



1-2 



Introduction 



Table 1-1. TMS370 Family Features 



FEATURE 


370C010 


370C810 


370C050 


370C850 


COMMENTS/BENEFITS 


Program Memory 


4 Kbytes 
ROM 


4 Kbytes 
EEPROM 


4 Kbytes 
ROM 


4 Kbytes 
EEPROM 


EEPROM supports In-socket 
programming 


Static RAM 


128 
bytes 


128 
bytes 


256 
bytes 


256 
bytes 


Data retention in low- power 
modes 


Data EEPROM 


256 
bytes 


256 
bytes 


256 
bytes 


256 
bytes 


Data retention in power-off 
mode 


Watchdog Timer 


Y 


Y 


Y 


Y 


Helps ensure system integrity 


Timer 1 


Y 


Y 


Y 


Y 


16 bits with 200 ns resolution 


Timer 2 






Y 


Y 


16 bits with 200 ns resolution 


A/D Converter 






Y 


Y 


8 channel, 8-blt accuracy with 
selectable references; provides 
conversion of external analog 
inputs in 164 cycles 


Serial 

Communications 

Interface 






Y 


Y 


Async. transmission up to 
1 56 kbits/s; Sync transmission 
up to 2.5 Mbits/s; software 
selectable baud rate 
and data format 


Serial Peripheral 
Interface 


Y 


Y 


Y 


Y 


Data transmission up to 
2.5 Mbits/s. 


External Interrupt 
Inputs (3) 


Y 


Y 


Y 


Y 


Selectable edge detection 


External Memory 
Bus Expansion 






Y 


Y 


Non-multiplexed address bus and 
data bus. Eliminates requirements 
for glue chips and saves board 
space 


Max. Digital I/O 


22 


22 


55 


55 


Provides the designer with multi- 
purpose ports for increased 
flexibility 


Pin Count 


28 


28 


68 


68 


Provides alternatives to meet the 
requirements of the application 


Packaging 


DIP/ 
PLCC 


DIP/ 
PLCC 


PLCC 


PLCC 


Supports high density surface 
mount 



TMS370 APPLICATIONS 



INDUSTRIAL 

- Motor Control 

- Temperature controllers 

- Process control 

- Meter control 

- Medical Instrumentation 

- Security systems 



TELECOMMUNICATIONS 

- Modems 

- Intelligent phones 

- Intelligent line card control 

- Telecopiers 

- Debit cards 



AUTOMOTIVE 

Climate control systems 
Cruise control 
Entertainment systems 
Instrumentation 
Navigational systems 
Engine control 
Sub-systems diagnostics 

COMPUTER 

Keyboards 

Peripheral interface control 

Disk controllers 

Terminals 



1-3 



Introduction 



1.2 TMS370 Architecture Overview 

Figure 1-1 is a block diagram of the TMS370 architecture showing the major 
functions. The unshaded blocl<s and paths in the figure are features common 
to TMS370Cx10 and TMS370Cx50 devices. Shaded blocks and paths are 
present only on TMS370C050 and TMS370C850 devices. 

The TMS370 family is based on a register-to-register architecture which 
allows access to a 256-byte Register File in a single bus cycle. On-chip 
memory includes a 4-kilobyte Program Memory (EEPROM or mask ROM), a 
128/256-byte Static RAM, and a 256-byte Data EEPROM. 

The versatile on-chip peripheral functions include (depending on the specific 
member of the series) an Analog-to- Digital converter (A/D), a Serial Com- 
munications Interface function (SCI), a Serial Peripheral Interface (SPI), up 
to three timers, and up to 55 digital Input/Output pins. 



XTAL2/ 
INT1 1NT2 INT3 XTAL1 CLKIN MC RESET 




VSS2 VCC2 



[■[■•yy-yJi TMS370Cx50 only 

^Bus expansion for TMS370Cx50 only 



Figure 1-1. TMS370 Block Diagram 



1-4 



Introduction 



CPU 

The TMS370 CPU is an 8-bit processor with Status register. Program Counter 
register, and Stack Pointer internal to the CPU module. The CPU uses the 
Register File as working registers, accessed on the internal bus in one bus 
cycle. The 8-bit internal bus also allows access to memory, and the peripheral 
interfaces. TMS370C050 and TMS370C850 devices allow externa! bus 
expansion through Ports A, B, C, and D. 



REGISTER FILE 

The Register File is located at the beginning of the TMS370 memory map. 
Register-access instructions in the TMS370 instruction set allow access to any 
of these registers in one bus cycle. This segment of the memory map is used 
as general purpose RAM and the Stack. 



DATA EEPROM 

The Data EEPROM module contains 256 bytes of Electrically Erasable Pro- 
grammable Read Only Memory. This memory is useful for constants and 
infrequently changed variables required by the application program. The 
EEPROM can be programmed and erased using available Programmers or by 
the TMS370 itself under program control. 



PROGRAM MEMORY 

The Program Memory module contains four kilobytes of memory. In 
TMS370C810 and TMS370C850 devices the Program Memory is EEPROM 
and can be programmed, erased, and reprogrammed for prototype or small 
production runs. In TMS370C010 and TMS370C050 devices, the program 
memory is mask ROM, programmed at the factory. 



INPUT/OUTPUT PORTS 

TMS370C01 and TMS370C81 devices have two ports: Ports A and D. Both 
of these ports can be programmed, bit-by-bit, to function as either a digital 
input or a digital output. 

TMS370C050 and TMS370C850 devices have four ports: Ports A, B, C, and 
D. These ports can be configured by software as the data, control, and address 
lines for an external bus. Any bits not needed for an external bus can be pro- 
grammed to be either a digital input or a digital output. 



1-5 



Introduction 



WATCHDOG TIMER 

The Watchdog Timer can be programmed to generate an interrupt when it 
times out. This function provides a hardware monitor over the software to 
prevent a "lost" program. If not needed as a watchdog, this timer can be used 
as a general purpose timer. 



TIMER 1 and TIMER 2 

These timers can be programmed to one of many configurations to count 
events, compare the counter contents to a preset value, or time-out after a 
preset interval. The results of these operations can generate an interrupt to the 
CPU, set flag bits, reset the timer counter, toggle an I/O line, or generate 
pulse-width-modulated (PWM) outputs. 



SCI. SERIAL COMMUNICATIONS INTERFACE 

The SCI module is a built-in serial interface which can be programmed to be 
asynchronous or isosynchronous. All timing, data format, and protocol factors 
are programmable and controlled by the SCI module in operation. The CPU 
takes no part in the serial communications except to write data to be trans- 
mitted to registers in the SCI and read received data from registers in the SCI 
when interrupted. 



SPI, SERIAL PERIPHERAL INTERFACE 

The SPI module is a built-in serial interface which facilitates communication 
between networked master and slave CPUs. As in the SCI, the SPI is setup 
by software and from then on, the CPU takes no part in timing, data format, 
or protocol. Also, as In the SCI, the CPU reads and writes to memory mapped 
registers to receive and transmit data. An SPI Interrupt alerts the CPU when 
received data is ready. 



A-TO-D CONVERTER 

The A-to-D Converter module is an eight-channel, 8-bit, successive- 
approximation, analog-to-digital converter. The reference source and input 
channel are selectable. The conversion result can be programmed to be the 
ratio of the input voltage to the reference voltage or the ratio of one analog 
input to another. Input lines not required for A/D conversion can be pro- 
grammed to be digital input lines. 



1-6 



Introduction 



1.3 Manual Organization 



The following sections of this manual and their contents are summarized 
below. 

Section 2: Family Devices 

Presents the features of TMS370 family members including pinouts. 
Sections 3-11 

Describes the operation and programming of each major function in the 
TMS370 architecture. 

Section 12: Instruction Set 

Describes the TMS370 addressing modes and each of the 73 instruc- 
tions including samples and examples. 

Section 13: Design Aids 

Gives sample interface circuits and programing examples. 

Section 14: Development Support 

Describes the hardware and software design-development tools avail- 
able for the TMS370 series. 

Section 15: Electrical Specifications 

Gives timing diagrams and electrical specifications. 
Section 16: Customer Information 

Gives packaging, numbering, and ordering information. 
Appendix A: 

Gives reference tables and diagrams for TMS370 control bits. 

Appendix B - D: 

Give reference tables for the TMS370 character set, instruction set, and 
opcodes. 

Appendix E: Glossary 

Index 



1-7 



Introduction 



1.4 Symbols and Conventions 

The following symbols and conventions are used in this manual 



SYMBOL 


EXAMPLE 


DESCRIPTION 


(xxxxxx.n) 


SPICTL4 


Bit location convention used in text, where 'xxxxxx' is the name of 
the register containing the bit and 'n' is the bit number 
(7=msb, 0=lsb). 


(xx.n) 


4A.0 


Bit location convention used in figures, where 'xx' is the hexadecimal 
address of the peripheral register containing the bit and 'n' is the 
bit number (7 = msb, = Isb). 


h 


1000h 


Designates a number in the hexadecimal number system. 


TMS370C0x0 




Refers to TMS370C010 and TMS370C050 devices. 


TMS370C8xO 




Refers to TMS370C810 and TMS370C850 devices. 


TMS370CxlO 




Refers to Ti\/IS370C010 and Ti\/IS370C81 devices. 


TMS370Cx50 




Refers to TMS370C050 and TI\/IS370C850 devices. 


set 




When used in reference to bits, means to write a logic 1 to the bit. 


clear 




When used in reference to bits, means to write a logic to the bit. 


POn 


P012 


Hexadecimal Peripheral File (PF) address used in instructions 
accessing the PF. 


Pn 


PI 8 


Decimal Peripheral File (PF) address used in instructions accessing 
thePF. (i.e., P18 = P012). 


ROn 


R010 


Hexadecimal Register File (RF) address used in instructions accessing 
the RF. 


Rn 


R16 


Decimal Register File (RF) addreiss used in instructions accessing 
the RF. (i.e., R16 = R010) 



1.5 Applicable Documents 



1 ) TMS370 Family Assembly Language Tools User's Guide, SPNU01 0. 

2) TMS370IEEPROM Programmer's User's Guide, S P N U 01 1 . 

3) TMS370 Family PC Debugger Interface User's Guide, SPNU01 2 

4) TMS370 XDSI22 Quick Reference Card, SPNU009 

5) TMS370C050/TMS370C850 8-Bit Microcontrollers Data Sheet, 
SPNS010 

6) TI\/IS370C010/TMS370C810 8-Bit Microcontrollers Data Sheet, 
SPNS012 



Introduction 



TMS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications interface (SCI) Port 



Serial Peripheral Interface (SPI) Module WH 



Analog-To-Oigital Converter Module 



Assembly Language instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



2. TMS370 Family Devices 



This section discusses the features of the TMS370 family^ of microcomputers. 
All family members are software compatible, allowing easy migration within 
the TI\/IS370 family by maintaining a software base, development tools, and 
design expertise. 

The TMS370 family devices are divided into two categories: 

• TMS370Cx10 devices which include the TMS370C01 and 
TMS370C810 

• TI\/IS370Cx50 devices which include the TMS370C050 and 
TMS370C850 

Both categories are supported by development tools that include the XDS, 
Assembler, and Linker. 

This section begins with a summary and comparison of the TMS370 family 
devices, and then provides key features, pinouts, and pin descriptions for the 
Individual categories. 

Section Page 

2.1 Summary and Device Comparison 2-2 

2.2 TMS370Cx10 Features 2-3 

2.3 TMS370Cx50 Features 2-4 

2.4 TMS370 Family Pinouts/Pin Descriptions 2-6 

2.4.1 TMS370Cx10 Pinouts 2-6 

2.4.2 TMS370Cx10 Pin Descriptions 2-7 

2.4.3 TMS370Cx50 Pinouts 2-8 

2.4.4 TMS370Cx50 Pin Descriptions 2-9 



1 Throughout this manual, the term TMS370 or TMS370 family refers to all members of the 
group. 

2-1 



Summary and Device Comparison. 



2.1 Summary and Device Comparison. 

The TMS370 family CMOS devices can be sumnnarized as follows: 

- The TMS370C010 and TMS37OC810 are 8-bit, single-chip microcom- 
puters, containing a CPU, a 16-bit timer, flexible I/O, a serial peripheral inter- 
face, 128 bytes of on-chip static RAM, and 256 bytes of data EEPROM. The 
TMSSTOCOIO also has 4K bytes of mask ROM program memory, while the 
TMS370C810 has 4K bytes of EEPROM program memory. 

- The TMS370C050 and TMS370C850 devices have the same basic features 
as the TMS370Cx10 with the addition of another 16-bit timer (timer 2), a 
serial communications interface, 128 bytes of on-chip static RAM (for a total 
of 256), memory expansion ports, and an eight channel A/D converter. 

- Development tools include the TM 5370 XDS, Assembler, and Linker. 

Table 2-1. TMS370 Family Feature Summary 





TMS370C010 


TMS370C810 


TMS370C050 


TMS370C850 


Maximum Oscillator 
Freq. 


20 MHz 


20 MHz 


20 MHz 


20 MHz 


Voltage 


5V ±10% 


5V ±10% 


5V ±10% 


5V ±10% 


Operating 
temperature 


-40°C to 85°C 


-40X to 85X 


-40°C to 85°C 


-40°C to 85°C 


Program Memory 


4K ROM 


4K EEPROM 


4KR0M 


4K EEPROM 


Internal RAM 


1 28 bytes 


1 28 bytes 


256 bytes 


256 bytes 


Data EEPROM 


256 bytes 


256 bytes 


256 bytes 


256 bytes 


Modules 
SPI 

Timer 1 

Watchdog timer 
Timer 2 
SCI 
A/D Port 


Yes 
Yes 
Yes 
No 
No 
No 


Yes 
Yes 
Yes 
No 
No 
No 


Yes 
Yes 
Yes 
Yes 
Yes 
Yes 


Yes 
Yes 
Yes 
Yes 
Yes 
Yes 


I/O Lines: 
Bidirectional 
Input only 


22 
1 


22 

1 


46 
9 


46 
9 


Memory Expansion 


No 


No 


Yes 


Yes 


Interrupts/Reset 
External 
Vectors total 
Sources total 


4 
6 
13 


4 
6 
13 


4 
10 
23 


4 
10 
23 


Package Type 


28-pin DIP 
28-pin PLCC 


28-pin DIP 
28-pin PLCC 


64-pin PLCC 


64-pin PLCC 



2-2 



TMS370Cx10 Features 



2.2 TMS370Cx10 Features 

The key features of the TMS370Cx10 devices are as follows: 



- CMOS EEPROM Technology 

- EEPROM programming with single 5-volt supply 

- Flexible operating features 

- Power reduction STANDBY and HALT modes 

- -40C to 85C operating temperature 

- 2 MHz to 20 MHz input clock frequency 

- 5-volt supply (Vcc) 

- Wake-up power-down mode 

- Memory-mapped ports for easy addressing 

- 14 addressing modes using eight formats, including: 

- Register-to-register arithmetic 

- Indirect addressing 

- Indexed and indirect branches and calls 

- 1 6-bit general-purpose timer, software configurable as: 

- 16-bit event timer 

- 16-bit pulse accumulator 

- 16-bit input-capture function 

- Two compare registers 

- Self contained PWM output function 

- On-chip 24-bit watchdog timer 

- Serial peripheral interface (SPI) 

- Variable-length high-speed shift register 

- Synchronous master/slave operation 

- Error detection flags 

- Flexible interrupt handling 

- Two software programmable interrupt levels 

- Programmable rising or falling edge detect 

- System integrity features: 

- Oscillator fault detection 

- Privileged mode lockout 

- Watchdog timer (24-bit) 



2-3 



TMS370Cx50 Features. 



2.3 TMS370Cx50 Features. 



Table 2-2. TMS370Cx50 Feature Summary 



FEATURE 


Tjws^^ocmo 


TMS37»Cd1d 


TMS370C050 


TMS370C850 


Maximum Oscillator 
Freq. 


2&MHJt 


2QMtiz 


20 MHz 


20 MHz 


Voltage 


$V ±10% 


5 V ±10% 


5V ±10% 


5V ±10% 


Operating 
temperatures 


-40*C to 8$"C 


'4<rCtoB5*C 


-40X to 85X 
0°C to 70°C 


-40X to 85X 
0°C to VOX 


<i^Cto70*C 


OrCKfWC 


Program Memory 


4KR0M 


4K EEPROM 


4KR0M 


4K EEPROM 


Internal RAM 


MBimeA 


128:bYtci 


256 bytes 


256 bytes 


Data EEPROM 


25fihytB& 


2S6 bytes 


256 bytes 


256 bytes 


Modules 
SPI 

Timer 1 

Watchdog timer 
Timer 2 
SCI 
A/D Converter 


Ye& 


Xm 


Yes 
Yes 
Yes 
Yes 
Yes 
Yes 


Yes 
Yes 
Yes 
Yes 
Yes 
Yes 


Vest 
Yes 


Yes 


fito 


^fo 


Ho 


Na ] 


so 


No 


I/O Lines: 
Bidirectional 
Input only 


22 


^ 


46 
9 


46 
9 


1 ] 


t 


Memory Expansion 


m 


^ H0 


Yes 


Yes 


Interrupts/Reset 
External 
Vectors total 


- 




4 
10 
23 


4 

10 
23 


A 
6 
13 


A 

13 


Package Type 


Sa-pin DIP 


28-pffl DIP 


64-pin PLCC 


64-pin PLCC 


aS'pin I^LCC 


a^-pln PLCC 



The TMS370Cx50 devices contain all the features of the TMS370Cx10 
devices plus additional capabilities. The following features are common to all 
TMS370Cx50 and TMS370Cx10 devices: 



CMOS EEPROM Technology 

- EEPROM programming with single 5-volt supply 

Flexible operating features 

- Power reduction STANDBY and HALT modes 

- -40C to 85C operating temperature 

- 2 MHz to 20 MHz input clock frequency 

- 5-volt supply (Vcc) 

- Wake-up power-down mode 



- Memory-mapped ports for easy addressing 



2-4 



TMS370Cx50 Features. 



14 addressing modes using eight formats, including: 

- Register-to-register arithmetic 

- Indirect addressing 

- Indexed and indirect branches and calls 

16-bit general purpose timer - software configurable as: 

- 16-bit event timer 

- 16-bit pulse accumulator 

- 16-bit input-capture function 

- Two compare registers 

- Self contained PWM output function 

On-chip 24-bit watchdog timer 

Serial peripheral interface (SPI) 

- Variable-length high-speed shift register 

- Synchronous master/slave operation 

- Error detection flags 

Flexible interrupt handling 

- Two software programmable interrupt levels 

- Programmable rising or falling edge detect 

System integrity features: 

- Oscillator fault detection 

- Privileged mode lockout 

- Watchdog timer (24-bit) 



The following features are unique to the TMS370Cx50 devices: 

- Eight channel A/D converter 

- 2nd 16-bit general purpose timer 

- Serial communications interface (SCI) 

- Asynchronous and Isosynchronous modes 

- Full duplex, double buffered Rx and Tx 

- Additional 128 bytes of on-chip RAM (256 bytes total) 

- Flexible system memory configurations 

- Precoded external chip select outputs 

- Programmable external memory/peripheral WAIT states 

- Addressable memory expansion to over 1 1 2K bytes 

- No logic needed for external memory addressing 

- WAIT line to extend bus cycles 



2-5 



TMS370 Family Pinouts/Pin Descriptions 



2.4 TI\/IS370 Family Pinouts/Pin Descriptions 

2.4.1 TMS370Cx10 Pinouts 

The pinouts for the TMS370Cx1 devices are shown below. 



D6C;; 

D7C 
A7C 

vccC 

XTAL2/CLKIN [^ 
XTAL1 [2 

A4Q 
A3l^ 
A2[^ 

VssC 
AlC 
AOC 



1 U28 

2 27 



3 

4 

5 

6 

7 

8 

9 

10 

11 

12 



26 
25 
24 
23 
22 
21 
20 
19 
18 
17 



13 16 

14 15 



U D3 
3 RESET 
3 D4 

U SPISOMI 
U SPICLK 

uspisimo 

Dtiic/cr 

I]tipwm 

Utievt 

Hmc 

Hints 

I]lNT2 
I]lNT1 
I]D5 



O 

O r- r-> CO CO 

> < Q Q Q 



UJ 'T 

CC Q 



C 4 3 2 1 28 27 26 

XTAL2/CLKIN ] 5 O 25 [ SPISOMI 

XTALl ]6 24 [ SPICLK 

A6]7 23[SPISIMO 

A5]8 22[T1IC/CR 

A4]9 2l[T1PWM 

A3] 10 20[T1EVT 

A2 ]11 19[ MC 
12 1314 1516 17 18 



c/) T- o in T- CM n 
05 < < Q H 1- H 

> -z.-z.-z. 



A. 28-Pin DIP B. 28-Pin PLCC 

Figure 2-1 . Pinouts for TMS370C010, and TMS370C810 



2-6 



TMS370 Family Pinouts/Pin Descriptions 



2.4.2 TMS370Cx10 Pin Descriptions 



Table 2-3. TMS370Cx10 Pin Descriptions 



Pin 


I/O 


Description 


Name 


No. 


AO 
A1 
A2 
A3 
A4 
A5 
A6 
A7 


14 

13 

11 

10 

9 

8 

7 

3 


I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 


Port A is a general purpose bidirectional I/O port. 


D3 
D4 
D5 
D6 
D7 


28 

26 

15 

1 

2 


I/O 
I/O 
I/O 
I/O 
I/O 


Port D is a general purpose bidirectional I/O port. 


INT1 
INT2 
INT3 


16 
17 
18 


1 

I/O 
I/O 


External non-maskable or maskable interrupt/General purpose input pin. 
External maskable interrupt input/General purpose bidirectional pin. 
External maskable interrupt input/General purpose bidirectional pin. 


T1IC/CR 

T1PWM 
T1EVT 


22 

21 
20 


I/O 

I/O 
I/O 


Timer 1 Input Capture/Counter Reset input pin/General purpose 
bidirectional pin. 

Timer 1 PWM output pin/General purpose bidirectional pin. 
Timer 1 external Event input pin/General purpose bidirectional pin. 


SPISOMI 
SPISIMO 
SPICLK 


25 
23 
24 


I/O 
I/O 
I/O 


SPI Slave Output pin. Master Input pin/General purpose bidirectional pin. 
SPI Slave Input pin, Master Output pin/General purpose bidirectional pin. 
SPI bidirectional Serial Clock pin/General purpose bidirectional pin. 


RESET 


27 


I/O 


System reset bidirectional pin. As an input it initializes microcontroller, 
as an open-drain output it indicates an internal failure was detected by 
the Watchdog or Oscillator Fault circuit. 


MC 


19 


1 


Mode control input pin; enables EEPROM Write Protection Override 
(WPO) mode. Normal operation = OV, WPO = 12V. 


XTAL2/ 
CLKIN 
XTAL1 


5 
6 


1 




Internal oscillator crystal input/External clock source input. 
Internal oscillator output for crystal. 


Vcc 


4 




Positive supply voltage 


Vss 


12 




Ground reference 



NOTE: Each pin associated with Interrupt 2, Interrupt 3, Timer 1, and SPI functional blocks may be 
individually programmed as a genera! purpose bidirectional pin if it is not used for it's primary 
block function. 



2-7 



TMS370 Family Pinouts/Pin Descriptions 



2.4.3 TMS370Cx50 Pinouts 



C3 ] 
C4] 
C5 ] 
C6 U 
C7 

^CC2 
^SS2 . 
AO ] 

] 



A1 

A2p 
A3 ]20 
A4 ]21 
A5 ]22 
A6 ]23 
A7 ]24 
T2EVT ] 25 
T2IC2/PWM ] 26 






lUJ 
CO 

lo 

Oh-(OU5^CO<MT-00 



CNJ CM »- 

O CO o 



^UJ *" T ^- -^^ r^ Vk/ UJ -^r \.'J VM 1— K^ »-* IJ uj \. 

>oo5omtnmmmmmmQ>>> 



9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 



60 [ D1/CSH3 
59 [ D2/CSH2 
58 [ D3/CLK0UT 
57 [ D4 /R/W 
56 [ D5/CSPF 



55 [ 
54 [ 
53 C 
52 [ 
51 

50 [ 
49 
48 [ 
47 [ 
46 [ 
45 [ 
44 [ 



27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 

~ " — II— ii—ir— ir— 1[— ir— ir-ir-ir— i r-|[-ir— 1 



D6/CSH1/EDS 
D7/CSE1/WAiT 



RESET 

INT1 

INT2 

INT3 

SPISOMI 

SPISIMO 

SPICLK 

T1IC/CR 

T1PWM 

T1EVT 



K i>i a Q 

O -I X X 5 

> y s b 5 

o o o o o 

c^ en CO CO > 



r- m mO zz f^ n ■^ m to 

O O CD^ *»-<<<<<< 



Figure 2-2. Pinouts for TMS370C050 and TMS370C850 



2-8 



TMS370 Family Pinouts/Pin Descriptions 



2.4.4 TMS370Cx50 Pin Descriptions 



Table 2-4. TMS370Cx50 Pin Descriptions 



Pin 


I/O 


Description 


Name 


Alternate 
Function 


No. 


AO 
A1 
A2 
A3 
A4 
A5 
A6 
A7 


DATAO (LSB) 

DATA1 

DATA2 

DATA3 

DATA4 

DATA5 

DATA6 

DATA7 (MSB) 


17 
18 
19 
20 
21 
22 
23 
24 


I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 


Single-chip mode: Port A is a general 
purpose bidirectional port. 

Expansion mode: Port A may be individually 
programmed as the external bidirectional 
data bus ( DATAO- DATA7). 


80 
B1 
B2 
B3 
B4 
B5 
B6 
B7 


ADDO 
ADD1 
ADD2 
ADD3 
ADD4 
ADD5 
ADD6 
ADD7 


65 

66 

67 

68 

1 

2 

3 

4 


I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 


Single chip mode: Port B is a general purpose 
bidirectional I/O port. 

Expansion modes: Port B may be individually 
programmed as the low order address output 
bus (ADD0-ADD7). 


CO 
CI 
C2 
C3 
C4 
C5 
C6 
C7 


ADDS 

ADD9 

ADD10 

ADD11 

ADD12 

ADD13 

ADD14 

ADD15 


5 
7 
8 
10 
11 
12 
13 
14 


I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 
I/O 


Single chip mode: Port C is a general purpose 
bidirectional I/O port. 

Expansion mode: Port C may be individually 
programmed as the high order address output 
bus (ADD8-ADD15). 


INT1 
INT2 
INT3 


INTIN 

INTI01 

INTI02 


52 
51 
50 


1 

I/O 
I/O 


External interrupt (non-maskable or maskable)/ 
General purpose input pin. 

External maskable interrupt input/General 
purpose bidirectional pin. 

External maskable interrupt input/General 
purpose bidirectional pin. 



2-9 



TMS370 Family Pinouts/Pin Descriptions 



Table 2-4. TMS370Cx50 Pin Descriptions (Continued) 



Pin 


I/O 


Description 


Name 


Alternate 
Function 


No. 


DO 

D1 

D2 

D3 

D4 
D5 

D6 
D7 


Function 

A B 


64 

60 

59 

58 

57 
56 

55 
54 


I/O 

I/O 

I/O 

I/O 

I/O 
I/O 

I/O 
I/O 


Single chip mode: Port D is a general purpose 
bidirectional I/O port. 
Each of the Port D pins can be individually 
configured as either a general purpose I/O 
pin, primary memory control signal (Function A), 
or secondary memory control signal (Function B). 
All chip selects are independent and can be used 
for memory bank switching. 

I/O pin/A: Chip Select Eighth output 2 goes low 
during memory accesses to 2000h-3FFFh /B: Opcode 
fetch goes low during the opcode fetch memory 
cycle. 

I/O pin/A: Chip Select Half output 3 goes low 
during memory accesses to 8000h-FFFFh. 

I/O pin/A: Chip Select Half output 2 goes low 
during memory accesses to SOOOh-FFFFh. 

I/O pin/A, B: Internal clock signal is 1/4 
XTAL2/CLKIN frequency. 

1/0 pin/A, B: Read/Write output pin. 

I/O pin/A: Chip Select Peripheral output for 
peripheral file goes low during memory accesses 
to10C0h-10FFh. 

I/O pin/A: Chip Select Half output 1 goes low 
during memory accesses to SOOOh-FFFFh 
/B: External Data Strobe output goes low during 
memory accesses from external memory and has the 
same timings as the five chip selects. 

I/O pin/A: Chip Select Eighth output goes low 

during memory accesses to 2000h-3FFFh /B: Wait input 

pin extends bus signals. 


CSE2 


OCF 

CLK- 
OUT 

R/W 
EDS 


CSH3 


CSH2 

CLK- 
OUT 

R/W 

CSPF 


CSH1 


CSE1 


WAIT 


T1IC/CR 
T1PWM 
T1EVT 


Alter 
Func 


nate 
:tion 


46 
45 
44 


I/O 
I/O 
I/O 


Timer 1 Input Capture/Counter Reset input 
pin/General purpose bidirectional pin. 

Timer 1 PWM output pin/General purpose 
bidirectional pin. 

Timer 1 External Event input pin/General purpose 
bidirectional pin. 


T1I01 
T1I02 
T2I03 


T2IC1/ 
CR 

T2IC2/ 
PWM 

T2EVT 


T2I01 
T2I02 
T2i03 


27 
26 
25 


I/O 
I/O 
I/O 


Timer 2 Input Capture 1 /Counter Reset input 
pin/General purpose bidirectional pin. 

Timer 2 Input Capture 2/PWM output pin/ 
General purpose bidirectional pin. 

Timer 2 External Event input pin/General purpose 
bidirectional pin. 



2-10 



TMS370 Family Pinouts/Pin Descriptions 



Pin 


I/O 


Description 


Name 


Alternate 
Function 


No. 


SPISOMI 
SPISIMO 
SPICLK 


SPII01 
SPII02 
SPII03 


49 
48 
47 


I/O 
I/O 
I/O 


SPI Slave Output pin. Master Input pin/ 
General purpose bidirectional pin. 

SPI Slave Input pin. Master Output pin/ 
General purpose bidirectional pin. 

SPI bidirectional Serial Clock pin/ 
General purpose bidirectional pin. 


SCITXD 
SCIRXD 
SCICLK 


SCII01 
SCII02 
SCII03 


30 
29 
28 


I/O 
I/O 
I/O 


SCI Transmit Data output pin/General 
purpose bidirectional pin. 

SCI Receive Data Input pin/General 
purpose bidirectional pin. 

SCI bidirectional Serial Clock pin/ 
General purpose bidirectional pin. 


ANO 

AN1 
AN2 

AN3 
AN4 
AN5 
AN6 
AN7 


EO 

El 
E2 

E3 
E4 
E5 
E6 
E7 


36 

37 
38 

39 
40 
41 
42 
43 


1 


A/D analog input (AN0-AN7) or positive 
reference pins (AN1 -AN7). 

Port E may be individually programmed as general 
purpose input pins if not used as A/D converter 
analog input or positive reference input. 


Vcc3 
Vss3 




34 
35 




A/D converter positive supply voltage and optional 
positive reference input pin. 

A/D converter ground supply and low reference input 
pin. 


RESET 




53 


I/O 


System reset bidirectional pin. As an input it 
initializes microcontroller, as open-drain output it 
indicates an internal failure was detected by the 
Watchdog or Oscillator Fault circuit. 


MC 




6 


1 


Microprocessor/Microcomputer mode control pin, also 
enables EEPROM Write Protection Override (WPO) 
mode. 


XTAL2/ 
CLKIN 
XTAL1 




31 
32 


1 




Internal oscillator crystal input/External 

clock source input. 

Internal oscillator output for crystal. 


Vcci 




33,61 




Positive supply voltage for digital logic. 


Vcc2 




15,63 




Positive supply voltage for digital I/O pins. 


Vssi 




9 




Ground reference for digital logic. 


Vss2 




16,62 




Ground reference for digital I/O pins. 



NOTE. Each pin associated with the Interrupt, Timer 1, Timer 2, SPI, and SCI functional blocks may 
be individually programmed as a general purpose bidirectional pin if it is not used 
for its primary block function. 



2-11 



TMS370 Family Pinouts/Pin Descriptions 



2-12 



Ihtrbdiictibn 



TiyiS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module Ml* 



Analog-To-Dlgital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



3. CPU and Memory Organization 



This section describes the CPU registers and memory organization. In the 
TMS370 register-to- register architecture, the CPU and RAM act as a single 
unit along with the Program Counter, Stack Pointer, and Status Register. 

The following conventions are used in this section when discussing specific 
members of the TMS370 family: 

TMS370C0x0 refers to TMS370C010 and TMS370C050 devices. 
TMS370C8xO refers to TMS370C810 and TMS370C850 devices. 
TMS370Cx10 refers to TMS370C010 and TMS370C810 devices. 
TMS370Cx50 refers to TMS370C050 and TMS370C850 devices. 



Page 



his section covers the following topics: 

Section 

3.1 CPU/Register File Interaction 3-2 

3.2 CPU Registers 3-3 

3.2.1 Stack Pointer (SP) 3-3 

3.2.2 Status Register (ST) 3-4 

3.2.3 Program Counter 3-5 

3.3 Memory Map 3-6 

3.3.1 Register File 3-7 

3.3.2 Peripheral File 3-9 

3.3.3 Data EEPROM Module 3-11 

3.3.4 Program Memory 3-11 

3.4 Memory Operating Modes 3-13 

3.4.1 Microcomputer Single-Chip Mode (all TMS370 devices) 3-14 

3.4.2 Microcomputer Mode w/External Expansion (TMS370Cx50) ... 3-16 

3.4.3 Microprocessor Mode without Internal Memory 3-19 

3.4.4 Microprocessor Mode with Internal Program Memory 3-20 

3.4.5 Memory Mode Summary 3-22 



3-1 



CPU/Register File Interaction 



3.1 CPU/Register File Interaction 

The first 256 address locations in the memory space, OOOOh through OOFFh 
(0000h-007Fh for TMS370Cx10 devices), are called the Register File. Any 
location in this block can be accessed as: a general purpose register, data 
memory storage, program instructions, or part of the stack. 

Figure 3-1 illustrates the multiple use of the Register File. For example, mem- 
ory address 0004h can also be treated as register R4. Or, the stack pointer 
could be loaded with the address 0004h and the stack would start at the next 
location. 

Registers RO and R1 are also called A and B respectively. Some instructions 
imply Registers A or B. For example, the instruction LDSP assumes that the 
value to be loaded into the Stack Pointer is contained in Register B. 



RO (A) 


OOOOh 


R1 (B) 


0001 h 


R2 


0002h 


R3 


0003 h 


R4 


0004h 


R5 


0005h 


R6 


0006h 


R7 


0007h 


R8 


OOOBh 


R9 


0009h 


R10 


OOOAh 


R11 


OOOBh 


R12 


OOOCh 


R13 


OOODh 


R14 


OOOEh 


R15 


OOOFh 


' 


' 


; 


R255 


OOFFh 



• GENERAL PURPOSE 
REGISTERS 



• DATA MEMORY 
STORAGE 



PROGRAM EXECUTION 
STACK 



Figure 3-1. Register File 



This multiple use of the Register File gives designers the flexibility to use the 
Register File however they wish. The partitioning of the Register File is 
determined by the value loaded into the stack pointer and the use of the 
Register File by the program. 



3-2 



CPU Registers 



3.2 CPU Registers 



The CPU contains three registers to control the status and direction of the 
program. These are the: Stack Pointer, Status Register, and Program Counter. 
These registers and their use are described in the following paragraphs. 



3.2.1 Stack Pointer (SP) 



The stack operates as a last-in, first-out, read/write memory. The stack is typ- 
ically used to store the return address on subroutine calls and the status reg- 
ister contents during interrupts. 

The Stack Pointer (SP) is an 8-bit CPU register that points to the last entry 
or top of the stack. The SP is automatically incremented before data is pushed 
onto the stack and decremented after data is popped from the stack. 

The stack can be placed anywhere in the Register File. During reset, the SP 
is loaded with 01 h. To control the area occupied by the stack, the application 
program must set the Stack Pointer and include code to monitor the stack size. 

The SP is loaded from Register B (R1) using the assembly language instruc- 
tion LDSP. The LDSP instruction allows the stack to be located anywhere in 
the Register File space. The SP may be read into Register B using the STSP 
command. Figure 3-2 illustrates an example SP initialization and stack oper- 
ation. 



INIT MOV #60h,B 
LDSP 



Load Register B with the value 

60h. 

Load the stack pointer with the 

contents of Register B. 



OOOOh 
TOP OF STACK ON RESET - 0001 h 



INITIAL TOP OF STACK - 0060h 



UPPER STACK LIMIT - 007Fh 

OR 

OOFFh 




I INCRE 

4 PUSH THEN 

I ^ STOR 

. FETCl 

POP A THEN 



INCREMENT 

THEN 

STORE 

FETCH 

THEN 

DECREMENT 



Figure 3-2. Stack Example 



For TMS370Cx50 devices, if the stack is pushed beyond its limit of OOFFh, the 
SP register wraps around from OOFFh to OOOOh without an error indication. 
The stack for Ti\/IS370Cx10 devices is not implemented beyond 7Fh; data 
pushed beyond this limit is lost. The application program must guard against 
stack overflow. 



3-3 



CPU Registers 



3.2.2 Status Register (ST) 



Bit# 



The ST register includes four status bits and two interrupt enable bits. The four 
status bits indicate the outcome of the previous instruction. Conditional 
instructions (for example, the conditional jump instructions) use these status 
bits to determine program flow. The two interrupt bits control the two inter- 
rupt levels. The ST register, status bit notation, and status bit definitions are 
as follows: 

Status Register (ST) 
7 6 5 4 3 2 10 



c 


N 


Z 


V 


IE2 


IE1 


— 





RW-0 



RW-0 RW-0 



RW-0 



RW-0 RW-0 



R=Read, W=Write, -n= Value after RESET 

Bits 0-1 - Reserved. Read data is indeterminate. 

Bit 2 - IE1. Level 1 Interrupt Enable. 

This bit controls interrupt level 1 (highest priority). 

= disable interrupt requests from priority level 1. 

1 = enable interrupt requests from priority level 1. 

Bit 3 - IE2. Interrupt Enable, Chain 2. 

This bit controls interrupt level 2 (lowest priority). 

= disable interrupt requests from priority level 2. 

1 = enable interrupt requests from priority level 2. 

Bit 4 - V. Overflow. 

Set by the CPU if an arithmetic overflow condition was detected during the 
previous instruction. The value of this flag is significant at the completion of 
the following instructions: ADC, ADD, SUB, SBB, CMP, DIV. 



Instruction 


V 


ADC, ADD, INC, INCW 


(C XOR N) AND (Bit 7{s} XNOR Bit 7{d}) 


CMP, DEC, SUB, SBB 


(C XOR N) AND (Bit 7{s} XOR Bit 7{d» 


DIV 


1 if Rn :S A, which means quotient > 255 



Bit 5 - Z. Zero. 

Set by the CPU if the result of the previous operation was 0; cleared otherwise. 

Bit 6 - N. Negative. 

CPU sets this bit to the value of the most significant bit (sign bit) of the result 
of the previous operation. 

Bit 7 - C. Carry. 

This status bit is set by arithmetic instructions as a carry bit or as a no-borrow 
bit. It is also effected by the rotate instructions. See each instruction in 
Section Section 12 for a detailed description of how the Carry bit is used. 

When the CPU acknowledges an interrupt, the contents of the Status Register 
are automatically pushed onto the stack, then the Status Register is cleared 
(for more information on interrupt effects on the Status Register, see Section 
5.1 .1 ). The normal exit from an interrupt service routine is made with the RTI 
instruction. When the CPU executes the RTI instruction, it automatically re- 
stores the content of the Status Register with a stack-pop operation. 



3-4 



CPU Registers 



The four condition flags (C, N, Z, and V) are updated every time an instruction 
is executed which manipulates or moves data. Thus, conditional branches 
should be performed immediately after a data manipulation operation. The 
instructions that do not affect the contents of these flags are: 



TRAP through TRAP 15 


- IDLE, 


CALL 


- NOP 


CALLR 


- PUSH ST 


BR 


- RTS 


DJNZ 


- STSP 


JMP 


- JMPL 


Conditional Jump instructions 


- LDSP 



The LOST instruction allows a program to change all bits in the Status 
Register. The byte following this instruction is loaded directly into the Status 
Register. The assembly language instructions DINT, EINT, EINTH, and EINTL 
enable specific interrupts. These instructions are converted to a "LDST #iop8" 
opcode by the assembler so that "#iop8" is the appropriate value to set or clear 
the specific interrupt (see section Section 12 for more information on the 
LDST instruction). 

The carry (C) bit can be set with the SETC opcode and cleared with the CLRC 
opcode. 



3.2.3 Program Counter 



The contents of the Program Counter (PC) point to the memory location of 
the next instruction to be executed. The PC consists of two 8-bit registers in 
the CPU: the Program Counter High (PCH) and Program Counter Low (PCL). 
These registers contain the MSB and LSB of a 16-bit address. 

During RESET, the PCH (MSB of the PC) is loaded with the contents of 
memory location 7FFEh and the PCL (LSB of the PC) is loaded with the 
contents of memory location 7FFFh. Figure 3-3 illustrates this operation using 
an example value of 7000h as the contents of memory locations 7FFEh and 
7FFFh (Reset vector). 



MEMORY 



PROGRAM 
PCH 



COUNTER (PC) 
PCL 



OOOOh 


; ; 


1 70 


00 J 


- 


, 


I 


. 


1 


7FFEh 


70 










7FFFh 


00 















Figure 3-3. Program Counter After Reset 



3-5 



Memory Map 



3.3 Memory Map 



Figure 3-4 shows the memory maps of TMS370Cx50 and TMS370Cx10 
devices. The partitioning of memory and the physical location of memory 
(that is, on or off chip) depends on the device used and the memory mode of 
operation. The memory modes of operation are discussed in Section 3.4. 

Each TMS370Cx50 device can be programmed to use the 16 address bits to 
access up to 64 kilobytes of memory. In addition, memory expansion features 
allow up to 112 kilobytes of external memory. (The expansion features are 
described further in Section 3.4.2.) 



OOOOh 
OOFFh 


256 BYTE RAM 
(REGISIbJ^ FILE STACK) 


0100h 

OFFFh 
lOOOh 
10BFh 


RE8Siira:> 


PERIPHERAL FILE 


10C0h 
10FFh 


PERIPHERAL EXP 


1100h 
1EFFh 


l?ESffiVSD 


IFOOh 
1FFFh 


256 BYTE 
DATA bhHROM 


2000h 
3FFFh 


MEMORY EXPANSION 


4000h 
6FFFh 


MICROPROCESSOR MODE 
MEMORY EXPANSION 


7000h 
7FFFh 


4K BYTE ROM 


8000h 
FFFFh 


MEMORY EXPANSION 



Figure 3-4. TMS370 Memory Map 



The following paragraphs describe each block of the memory map. 



3-6 



Memory Map 



3.3.1 Register File 



The beginning addresses of the memory map (OOOOh-OOFFh forTMS370Cx50 
devices or 0000h-007Fh for TMS370Cx10 devices) are on-chip RAM called 
the Register File (RF). In TMS370Cx50 devices, the RF has 256 bytes of 
memory treated as registers RO through R255. In TMS370Cx10 devices, the 
RF has 128 bytes of memory treated as registers RO through R127. 

The first two registers, RO and R1, are also called Register A and Register B, 
respectively. The memory addresses of these registers are given in Figure 3-5. 



RO (A) 


OOOOh 


R1 (B) 


0001 h 


R2 


0002h 


R3 


0003h 


R4 


0004 h 


R5 


0005h 


R6 


0006h 


R7 


0007h 


RB 


oooah 


R9 


0009h 


R10 


OOOAh 


R11 


OOOBh 


R12 


OOOCh 


R13 


OOODh 


R14 


OOOEh 


R15 


OOOFh 


' 


' 


- 


R255 


OOFFh 



GENERAL PURPOSE 
REGISTERS 



DATA MEMORY 
STORAGE 



PROGRAM EXECUTION 
STACK 



Figure 3-5. Register File Addresses 



3-7 



Memory Map 



Locations within the RF address space may serve as either the CPU register 
file or general purpose read/write memory. Instructions can reside in and be 
executed from any location in the address space without restriction. The stack 
also occupies a portion of the Register File. 

Therefore, any location in the register file can be accessed by one of three 
ways. 

1 ) Normal memory access using a hexadecimal address. For example, 

MOV A,0006(B);Movethe contents of Register A to 

; memory location 0006h indexed by B. 

2) Register access using the register number. For example, 

MOV A,R6 ;Move the contents of Register A to 

; Register R6. 

3) Stack access using the stack pointer. For example, 

MOV #5 ,B ;Move the value 5 into Register B. 

LDSP ;Move the contents of Register B to 

; the Stack Pointer. 
PUSH A ;lncrement Stack Pointer to 6. 

; Move contents of Register A to 0006h. 

Access time to the Register File, when used as a general purpose register, is a 
single system clock cycle. Any other access to the Register File takes two clock 
cycles. 

A Reset operation has no effect on the contents of any memory location within 
the Register File except for locations OOOOh (Register A) and 0001 h (Register 
B). Registers A and B are cleared in the beginning of the reset process. 

The Halt, Idle, and Standby states have no effect on the contents of the 
Register File. 



3-8 



Memory Map 



3.3.2 Peripheral File 



The Peripheral File (PF) is a set of memory-mapped registers which provide 
access to all internal peripheral modules, system-wide control functions, and 
EEPROM programming control. 

The PF includes 256 addresses in the memory map from lOOOh-IOFFh. The 
PF is divided into 16 frames of 16 bytes each. Each peripheral module is allo- 
cated its own set of control registers. In addition, some frames are dedicated 
to specific functions. 

The instruction set includes some instructions which access the Peripheral File 
directly. These instructions designate the register by the number of the file 
register relative to lOOOh, preceded by 'PO' for a hexadecimal designator or 'P' 
for a decimal designator. For example, the System Configuration Control 
Register is located at address 101 Oh; its Peripheral File hexadecimal desig- 
nator is P010 and its decimal designator is PI 6. 

Table 3-1 gives the address map for the Peripheral File. 



Table 3-1. Peripheral File Address Map 



FRAME 
NO. 


ADDRESS 


DESCRIPTION 


TMS370Cx50 


TMS370Cx10 





1000h 


Reserved for factory test 


... 


... 


1 


101 Oh 


System and EEPROM control registers 


Yes 


Yes 


2 


1020h 


Digital I/O port control registers 


Yes 


Yes 


3 


1030h 


8 PI registers 


Yes 


Yes 


4 


1040h 


TIMER1 registers 


Yes 


Yes 


5 


1050h 


SCI registers 


Yes 


NA 


6 


1060h 


TiMER2 registers 


Yes 


NA 


7 


1070h 


A-to-D registers 


Yes 


NA 


8 


1080h 


Reserved 


NA 


NA 


9 


1090h 


Reserved 


NA 


NA 


10 


lOAOh 


Reserved 


NA 


NA 


11 


lOBOh 


Reserved 


NA 


NA 


12 


lOCOh 


External Peripheral control 


Yes 


NA 


13 


lODOh 


External Peripheral control 


Yes 


NA 


14 


lOEOh 


External Peripheral control 


Yes 


NA 


15 


lOFOh 


External Peripheral control 


Yes 


NA 



NA - Not Available 



3-9 



Memory Map 



Frame of the Peripheral File (memory addresses lOOOh-IOOFh) is reserved 
for factory testing. The results of access to this frame are unpredictable. 

Frame 1 (1010h-101 Fh) contains system configuration and control functions. 
It also contains registers for controlling EEPROM programming. EEPROM 
module control registers are described in Section 6. 

Frame 2 (1020h-102Fh) contains the Digital I/O Pin configuration/control 
registers. The individual functions controlled by these registers are described 
in Section 4.2, page 4-1 1 . 

Frames 3 through 7 are used by the internal peripherals. These peripherals and 
their control registers are described in the following sections. 

• SPI registers - Section 10 

• Timer 1 registers - Section 7 

• SCI registers - Section 9 

• Timer 2 registers - Section 8 

• A-to-D registers - Section 11 

Frames 8 through 1 1 are reserved. 

Frames 12 through 15 are available for external expansion of the Peripheral 
File on devices that have bus expansion capability. These frames are located 
in external memory and accessed by the external address and data buses. 



3-10 



Memory Map 



3.3.3 Data EEPROM Module 



The Data EEPROM module is a 256 byte array at memory locations 1 FOOh 
through 1 FFFh. This 256 byte array is configured into 8 blocks of 32 bytes. 
Each block can be individually write protected. This module can be pro- 
grammed on either a byte-wide or single-bit basis. Read-access time for the 
EEPROM module is two system clock cycles. 

Programming of the Data EEPROM array is controlled by the Data EEPROM 
Control Register (DEECTL) at memory address 101 Ah and a Write Protection 
Register (WPR) at memory address 1 FOOh. EEPROM programming com- 
mands are controlled through these registers. See Section 6.1 .1.1 and Section 
6.1 .1 .2 for more details on the WPR and DEECTL registers. 



3.3.4 Program Memory 



The Program Memory is arranged as individually-addressable bytes located at 
7000h through 7FFFh in the memory map. Data may be read or code may be 
executed directly from these locations. 

Memory addresses 7FECh through 7FFFh are reserved for interrupt and reset 
vectors. Trap vectors, used with TRAPO through TRAP1 5 instructions, are at 
addresses 7FC0h through 7FDFh. Table 3-2 gives the memory map for the 
reserved vector locations. 

The Program Memory may be either ROM or EEPROM depending the specific 
member of the TMS370 family. The differences are described in the para- 
graphs following Table 3-2. 

Table 3-2. Vector Address Map 



ADDRESS 


DESCRIPTION 


TMS370Cx50 


TMS370Cx10 


NO. OF 
BYTES 


7FC0h 


Trap 0-1 5 


Yes 


Yes 


32 


7FE0h 


Reserved 


NA 


NA 


12 


7FECh 


A-D Converter 


Yes 


NA 


2 


7FEEh 


Timer 2 


Yes 


NA 


2 


7FF0h 


Serial Communications Interface TX 


Yes 


NA 


2 


7FF2h 


Serial Communications Interface RX 


Yes 


NA 


2 


7FF4h 


Timer 1 


Yes 


Yes 


2 


7FF6h 


Serial Peripheral Interface 


Yes 


Yes 


2 


7FF8h 


Interrupt 3 


Yes 


Yes 


2 


7FFAh 


Interrupt 2 


Yes 


Yes 


2 


7FFCh 


Interrupt 1 


Yes 


Yes 


2 


7FFEh 


Reset 


Yes 


Yes 


2 



NA - Not Available 



3-11 



Memory Map 



3.3.4.1 Program ROM Module (TMS370C0x0 devices only) 

The Program ROM module consists of read-only memory which is pro- 
grammed at the time of device fabrication. All accesses to the ROM module 
requires two system clock cycles. 



Note: 

All TMS370 family devices contain mask ROM space reserved for Tl use 
only. This space includes locations 7FE0h through 7FEBh. This reserved 
area should not be used in the customer's software algorithm, nor should 
it be used during mask ROM/firmware development. 
The contents of the reserve locations are changed by Tl. 



3.3.4.2 Program EEPROM Module (TMS370C8xO devices only) 

The Program EEPROM module replaces the Program ROM for systems in 
prototype or small production runs. The module consists of 4 kilobytes of 
EEPROM (7000h-7FFFh) and the necessary programming control logic. 

The Program EEPROM Control Register (PEECTL) is located at memory 
location lOICh in the Peripheral File. 

Read access to the Program EEPROM is performed as normal memory read 
cycles. Write cycles require a special sequence of events. This sequence is the 
same as that for the Data EEPROM. See Section 6.2.2 for a detailed dis- 
cussion of programming the EEPROM Modules. 

The EEPROM can be written to only when the microcomputer is operating 
under Write Protect Override (WPO), which is set by applying 12 volts to the 
MC pin. 



3-12 



Memory Operating Modes 



3.4 Memory Operating Modes 

TMS370Cx50 devices have four memory operating modes. 

• Microcomputer modes 

- microcomputer single-chip mode 

- microcomputer with external expansion 

• Microprocessor modes 

- microprocessor without internal program memory 

- microprocessor with internal program memory 

TMS370Cx10 devices have no memory expansion capability and operate only 
in the microcomputer, single-chip mode. 

For TMS370Cx50 devices, the basic microcomputer and microprocessor 
operating modes are se lected by the voltage level applied to the dedicated 
MC pin when the RESET pin goes inactive (high). 



If the MC pin is low when the RESET signal goes high then the processor 
enters the microcomputer mode. If the MC pin is high when the RESET signal 
goes high, then it enters the microprocessor mode. Changing the MC pin 
alone will not change the memory mode. To change memory operating mode, 
change the MC pin and then reset the device. 

Applying 12 volts to the MC pin after Reset forces the device to enter the 
Write Protect Override (WPO) mode. 



Note: 

If 12 volts is applied to the MC pin when the RESET pin goes from low 
to high, the results are unpredictable. 



If the processor resets into a microcomputer mode, the software can change 
the internal system configuration registers to select the desired memory 
expansion configuration. Part of this configuration setup involves Digital I/O 
Port D. Each pin of Port D can be programmed to serve one of three purposes: 
Digital I/O, Function A signal, or Function B signal. Function A includes chip 
select signals which may be used in the Microcomputer Mode with External 
Memory Expansion. Function B includes signals used in either the Micro- 
computer or the Microprocessor modes to access external memory chips. 

Each of these modes are described in the following paragraphs. 



3-13 



Memory Operating Modes 



3.4.1 Microcomputer Single-Chip Mode (all TMS370 devices) 

In the Microcomputer Single Chip mode, a TMS370 device functions as a 
self-contained microcomputer with all memory and peripherals on the chip. 
There is no external address or data bus in this mode, which allows more pins 
(used for the external buses in other modes) to be programmed as 
input/output pins. This mode maximizes the general purpose I/O capability for 
real-time control applications. Figure 3-6 shows a memory map for the 
Microcomputer, 

During reset the MC pin must remain at a low level in order to successfully 
enter the microcomputer mode. While operating in the single-chip mode, 
external circuitry may place 12 volts on the MC pin to enter the Write Protect 
Override (WPO) mode to alter protected EEPROM. 

To put a TMS370 device into the Microcomputer Single Chip Mode: 

1 ) Place a lo w logi c level on the MC pin. 

2) Take the RESET pin active low, then return RESET to its inactive high 
state. 



Note: 

The preceding procedure must be followed for TMS370Cx1 devices even 
though they operate only in the Microcomputer, Single Chip Mode. 



3-14 



Memory Operating Modes 



REGISTER FILE/STACK 



PERIPHERAL FILE 



DATA EEPROM 



{ 



ADDRESS 
(HEX) 
0000 
OOFF 
0100 



PROGRAM ROM/EEPROM 



{ 



OFFF 
1000 
10BF 
10CO 



1EFF 
1F00 
1FFF 
2000 



6FFF 
7000 
7FFF 

aooo 



FFFF [ 



ON CHIP 



mMimmm 

AVAIUBLE 



NOT 
AVAiLASLE 



NOT 
AVAiU^LE 



NOT 



Figure 3-6. iVIicrocomputer, Single Chip iVlode 



3-15 



Memory Operating Modes 



3.4.2 Microcomputer Mode w/External Expansion (TMS370Cx50) 

The microcomputer mode also supports bus expansion to external memory or 
peripherals, while all on-chip memory (Register File, ROM, and EEPROM) 
remains active. Digital I/O ports, under the control of their associated port 
control registers, become the external buses as follows: 

• Port A: 8-bit data bus 

• Port B and C: 16-bit address bus 

• Port D: 8-bit control bus 

If it is not necessary to use the entire address, data, or control bus, then each 
unused pin can be individually programmed as a general purpose input/output 
pin. These bits are programmed by setting the Digital I/O control registers in 
the Peripheral File (see Section 4.2 for further information on programming 
I/O pins). 

The address bus and data bus are non-multiplexed, eliminating the require- 
ment for an external address/data latch, thereby lowering system cost. Exter- 
nal interface decode logic can be reduced further by using the precoded chip 
select outputs. The Port D outputs can be programmed, on a pin-by-pin basis, 
to provide direct memory/peripheral chip selection or chip enable functions. 

Each Port D pin can be individually set to Function A, Function B or general 
purpose I/O. When Port D is set up to drive the chip selection signals 
(Function A), a m emor y acc ess to any location between 2000h and 3 FFFh , 
acti vates pins CSEl and CSE2. Typically, an application that uses both CSEl 
and CSE2 sets one as the active chip-select function and sets the other as a 
general-purpose high-level output. 

Simil arly, a mem ory ac cess to any location between 8000h and FFFFh acti- 
vates cs m, CS H 2, an d CSH 3 if e nabled by the appropriate port control regis- 
ters. The CSHI, CSH2, and CSH3 signals can be used as memory bank select 
signals under software control. As a result, up to 96 kilobytes of external 
memory can be mapped into the 32-kilobyte logical address space of 
8000h-FFFFh as shown in Figure 3-7. 



The CSPF pin is activated, if enabled, during accesses to the upper 4 frames 
(memory addresses lOCOh-IOFFh) of the peripheral file. This signal can be 
used as a chip select for external expansion of the Peripheral File. 



Note: 

Applications that use more than one chip-select signal for the same 
address should set the unused chip-selects (i.e., chip-selects not currently 
used to select memory banks) to general-purpose high-level outputs. 



3-16 



Memory Operating Modes 



ADDRESS 

(HEX) ON CHIP 




OFF CHIP 






FUNCTION A 

CHIP SELECT 

SIGNALS 


REGISTER FILE/STACK <|^ qq"" 






0100 
r OFFF 


Wh 




PERIPHERAL FILE <^ 1000 
•^ 10BF 
PERIPHERAL EXPANSION / 

•-1100 

r 1EFF 
DATAEEPROM<^ 1F00 




1000 
10FF 










- 
•^ 








N/A 










^ 1FFF 


1 






MEMORY EXPANSION <^ 






2000 
3FFF 
















•" 




4000 

( 6FFF 

PROGRAM ROM/EEPROM <^ 7000 

^ 7FFF 


H/A 














1 






1 




•- 




MEMORY EXPANSION < 






8000 
FFFF 





























N/A - NOT AVAILABLE 

Figure 3-7. Microcomputer iVIode with Function A Expansion 



All p redecoded chip selects have the same timing as the Exte rnal Data Strobe 
(EDS) signal (see Section 15, Electrical Specifications). EDS is a Function B 
(microprocessor mode) signal which goes low whenever an access to external 
memory is made. Figure 3-8 shows a memory map for the Microcomputer 
Mode with Function B Expansion. 



3-17 



Memory Operating Modes 



REGISTER FILE/STACK 



PERIPHERAL FILE 
PERIPHERAL EXPANSION 



DATA EEPROM 



MEMORY EXPANSION 



PROGRAM ROM/EEPROM 



MEMORY EXPANSION 



{ 



ADDRESS 

(HEX) ON CHIP 

0000 

OOFF 

0100 



^<: 



OFFF 
000 
OBF 



100 



{J 



1EFF 

1F00 

FFF 



{ 



HfA 



nm 



OFF CHIP 



4000 
6FFF 


Hfk 


7000 
7FFF 





10C0 
10FF 






»_ 
•^ 


^ 




' 








2000 






3FFF 


*" 


' 








8000 






FFFF 







FUNCTION B 
CHIP SELECT 



EDS 



N/A - NOT AVAILABLE 

Figure 3-8. Microcomputer Mode with Function B Expansion 



See Section 4.2 for a description of the Digital I/O port control registers and 
how the chip select signals are enabled. 

To put a TMS370Cx50 device into the Microcomputer Mode with External 
Expansion: 

1 ) Place a lo w logi c level on the MC pin. 

2) Take the RESET pin active low, then return RESET to its inactive high 
state. 

3) Program the Digital I/O registers to select the chip select or control sig- 
nals needed (Function A or Function B). 



3-18 



Memory Operating Modes 



3.4.3 Microprocessor Mode without Internal Memory 

(TMS370Cx50 only) 

When a TMS370Cx50 device is activated in the microprocessor mode, the 
Register File and data EEPRO M re main active, but the on-chip Program ROM 
or EEPROM is disabled. The EDS signal goes low when a memory access is 
made to addresses 1 020-1 02F, lOCOh-IOFFh, and 2000h-FFFFh. The pro- 
gram area, the reset vector, interrupt vectors, and trap vectors must be located 
in off-chip memory locations. 

When a TMS370Cx50 device is RESET into the microprocessor mode, the 
Digital I/O, Port D registers are set to Function B expansion memory control 
signals. The chip-select signals are not available in Function B. Ports B and 
C are set up as the external address bus and Port A is set up to be the external 
data bus. Software cannot change the Digital I/O configuration. 

Figure 3-9 shows a memory map for the Microprocessor Mode. 



REGISTER FILE/STACK / 

PERIPHERAL FILe/ !J 
PERIPHERAL EXPANSION / 

PERIPHERAL FILE / ]°30 
PERIPHERAL EXPANSION / 



ADDRESS 

(HEX) ON CHIP 
0000 



OFF CHIP 



OOFF 
0100 

OFFF 

1000 

OIF 



Wh 



1100 



DATA EEPROM 



{ 1 



1EFF 
FOO 
FFF 



N/A 



MEMORY EXPANSION < 



1020 
102F 



10C0 

10FF 



2000 



FFFF 



• II 

• 



FUNCTION B 

CHIP SELECT 

SIGNALS 

EDS 



N/A-NOT AVAILABLE 

Figure 3-9. Microprocessor Mode without Internal Memory 



3-19 



Memory Operating Modes 



To put a TI\/IS370Cx50 device into tiie Microprocessor Mode without Internal 
Memory: 

1 ) Place a hi gh log ic level on the MC pin. 

2) Take the RESET pin active low, then return RESET to its inactive high 
state. 

3.4.4 Microprocessor Mode \A^ith Internal Program Memory. 

In the microprocessor modes. Ports A, B, C, and D become the address, data, 
and control buses for interface to external memory and peripherals. The on- 
chip Register File, data EEPROM, and internal Program ROM or EEPROM 
remain active. Any memory access to ad dress es 1020h-102F, lOCOh-IOFFh, 
2000h-3FFFh, and 8000h-FFFFh causes EDS to go low. 

When a TMS370Cx50 device is RESET into the microprocessor mode, the 
Digital I/O, Port D registers are set to Function B expansion memory control 
signals. The chip-select signals are not available in Function B. Ports B and 
C are set up as the external address bus and Port A is set up to be the external 
data bus. Software cannot change the Digital I/O configuration. 

After RESET, the TMS370Cx50 device enters the microprocessor mode with 
no internal memory. External memory must contain the reset vector. Software 
must clear the MEMORY DISABLE bit (SCCR1.2) to enable the internal 
memory. 

Figure 3-1 shows a memory map for the Microprocessor Mode, with Internal 
Program Memory. 



3-20 



Memory Operating Modes 



REGISTER RLE/STACK 

PERIPHERAL FILE 
PERIPHERAL EXPANSION 

DATA EEPROM 
MEMORY EXPANSION 

PROGRAM ROM/EPROM 



{ 



ADDRESS 

(HEX) ON CHIP 



0000 
OOFF 




0100 
OFFF 


H/A 


1000 
101F 





1030 

10BF 



1100 



'( 



1EFF 
FOO 
FFF 



{ 



4000 

6FFF 
7000 
7FFF 



MEMORY EXPANSION < 



N/A 



f^A 



1020 
102F 



10C0 
10FF 



2000 
3FFF 



SCCR1.2- 



8000 



FFFF 



OFF CHIP 



FUNCTION B 

CHIP SELECT 

SIGNALS 

EDS 



N/A-NOT AVAILABLE 

t-AFTER RESET UNTIL SCCR1.2 IS CLEARED BY THE PROGRAM. 



Figure 3-10. Microprocessor Mode with Internal Program Memory 



To put a TMS370Cx50 device into the Microprocessor Mode with internal 
Program Memory: 

1 ) Place a hi gh log ic level on the MC pin. 

2) Take the RESET pin active low, then return RESET to its inactive high 
state. 

3) The CPU reads the RESET vectors from external memory 
(7FFEh/7FFFh). The program pointed to by the vectors must include 
code to clear the MEMORY DISABLE bit (SCCR1.2) to enable the 
internal memory. The internal program memory (7000h-7FFFh) is now 
available. 



Note: 

Once the MEMORY DISABLE bit is cleared, the external memory at 
4000h-7FFFh is no longer available to the processor. 



3-21 



Memory Operating Modes 



3.4.5 Memory Mode Summary 



Table 3-3 summarizes the features of each Memory Mode and the procedure 
to activate the TMS370 device into each mode. Figure 3-1 1 gives the memory 
maps of the four modes. 



Table 3-3. Operating Mode Summary 



FEATURE 


pCOMPUTER 
SINGLE CHIP 


mCOMPUTER 

w/EXPANDED 

MEMORY 


mprocessor 

w/INTERNAL 
MEMORY 


pPROCESSOR 


Device 


TMS370C050/850 
TMS370C01 0/810 


TMS370C050/850 


TMS370C050/850 


TMS370C050/850 


Memory Address 
7000h-7FFFh 


Internal 


Internal 


Internal 


External 


Ports A,B,C,D 


Digital I/O 


Digital I/O 
Function At 
Function Qt 


Function Bt 


Function B* 


Predecoded CS 
(Chip Selects) 


No 


Optional 


No 


No 


Procedure to 
enter the mode 


1. Place logic 
on the MC pin 


1. Place logic 
on the MC pin 


1. Place logic 1 
on the MC pin 


1. Place logic 1 
on the MC pin 


2. Take the RESET 
pin active low, 
then release 
RESET 


2. Take the RESET 
pin active low, 
then release 
RESET 

3. Set Digital I/O 
registers to 
Function At/Bt 


2. Take the RESET 
pin active low, 
then release 
RESET 

3. Enable internal 
memory 
(ClearSCCR1.2) 


2. Take the RESET 
pin active low, 
then release 
RESET 



tFunction A: Port D = chip select signals CSE1, CSE2, C SH1, CSH2 , CS H3, an d CSPF (see Section 4.2). 
^Function B: Port D = expansion memory control signals OCF, EDS, and WAIT (see Section 4.2). 



3-22 



Memory Operating Modes 





MICROCOMPUTER 
SINGLE CHIP MODE 




MICROCOMPUTER 

WITH EXTERNAL 

EXPANSION 




MICROPROCESSOR 

WITH INTERNAL 
PROGRAM MEMORY 




MICROPROCESSOR 
MODE 




OOOOh 
OOFFh 


ON CHIP 




ON CHIP 




ON CHIP 




ON CHIP 




0100h 
OFFFh 


R^S3vm" ' 


ffESSlVSJ"--'- 


- -f?ESSIVHi. - ". 


- -~;;Risi^wof -_ 




1000h 
lOBFh 


ON CHIP 


ON CHIP 


ON CHIP* 


ON CHIP* 




10C0h 
10FFh 


NOT AVAILABLE 


EXTERNALt 


EXTERNAL 


EXTERNAL 




1100h 
lEFFh 


RKS5WED 


RESH«^I- 


m^^^/m ' _ 


" '' m^^o- ' - 




1F00h 
IFFFh 


ON CHIP 


ON CHIP 


ON CHIP 


ON CHIP 




2000h 
3FFFh 


NOT AVAILABLE 


EXTERNAL^ 


EXTERNAL 


EXTERNAL 




4000h 
61-HFh 


RESP^ysi _ 


i^BSBM£> :- 


- HESSiVED - 


EXTERNAL 




7000h 
7FFFh 


ON CHIP 


ON CHIP 


ON CHIP 


EXIhHNAL 




BOOOh 
FFFFh 


NOT AVAILABLE 


EXTERNAL^ 


EXTERNAL 


EXTERNAL 





^PRECODED CHIP SELECT OUTPUTS AVAILABLE ON EXTERNAL EXPANSION BUS. 
*1020h-102Fh EXTERNAL 

Figure 3-11. Memory Operating Modes 



3-23 



Memory Operating Modes 



3-24 



Introduction 



TMS370 Family Devices 



CPU and Memoiy Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module MR 



Analog-To<Dlgital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Infomiation 



Appendixes 



4. System and Digital I/O Configuration 

This section discusses system and I/O configuration. First, the features and 
options are described; then, the register and bits that control the configuration 
are described. Lastly, examples of how to set configuration are given. 

This section covers the following topics: 

Section Page 

4.1 System Configuration 4-2 

4.1.1 Privilege Mode 4-2 

4.1.2 Oscillator Fault 4-3 

4.1 .3 Automatic Wait States 4-3 

4.1.4 Powerdown and Idle Modes 4-4 

4.1.4.1 Standby Mode 4-5 

4.1.4.2 Halt Mode 4-6 

4.1.4.3 Oscillator Power Bit 4-6 

4.1.5 System Control Registers 4-7 

4.2 Digital I/O Configuration 4-11 

4.2.1 Microcomputer Mode 4-16 

4.2.2 Microprocessor Mode 4-16 



4-1 



System Configuration 



4.1 System Configuration 



The system configuration is controlled and monitored by the first three regis- 
ters of Peripheral File Frame 1 . These registers' names, designations, and 
Peripheral File register number (PF) are: 

Name Designation Address PF 

System Control and Configuration Register 
System Control and Configuration Register 1 
System Control and Configuration Register 2 

These registers are shown in Figure 4-1. The "PF" numbers are used by 
Peripheral File instructions, for example mov #OOh,POiO. 



SCCRO 


101 Oh 


P010 


SCCR1 


lOllh 


P011 


SCCR2 


1012h 


P012 



PERIPHERAL FILE FRAME 1: SYSTEM CONFIGURATION AND CONTROL REGISTERS 



ADDR 



PF 



1010h P010 



1011h P011 



1012h P012 



BIT 7 


BIT 6 


BITS 


BIT 4 


BIT 3 


BIT 2 


BIT 1 


BIT 


COLD 
START 


OSC 

POWER 


PF AUTO 
WAIT 


OSC FLT 
FLAG 


MC PIN 
WPO 


MC PIN 
DATA 





jiPlfiC 
MODE 





— 





AUTOWAIT 

DISABLE 





MEMORY 
DISABLE 


— 





HALT/ 
STANDBY 


pwtami/ 

IDLE 


OSC FLT 

f?STENA 


BUS 

S'lEBT 


CPU 

STE8T 


OSC FLT 

DISABLE 


INT1 

NMf 


PRIVI- 
LEGE 
DISABLE 



SCCRO 



SCCR1 



SCCR2 



Figure 4-1. System Configuration and Control Registers 



The bits shown in Figure 4-1 in shaded boxes are Privilege Mode bits, that is, 
they can only be written to in the Privilege Mode. 



4.1.1 Privilege Mode 



The TMS370 architecture allows you to configure the system and peripherals 
by software to meet the requirements of a variety of applications. The Privilege 
Mode of operation ensures the integrity of the system configuration once 
defined for an application. 

Following a hardware reset, the processor operates in the Privilege Mode. In 
this mode, peripheral file registers have unrestricted read/write access. The 
application program may configure the system during the initialization 
sequence following reset. As the last step of a system initialization, set the 
PRIVILEGE DISABLE (SCCR2.0) to enter the nonprivilege mode and prevent 
changes to specific control bits within the peripheral file. 

Table 4-1 shows the system configuration bits which are write- protected 
during the nonprivilege mode. These bits should be configured by software 
prior to exiting the Privilege Mode. The bits shown in the shaded part of Table 
4-1 are discussed in later sections which cover the peripheral modules. 



4-2 



System Configuration 



Table 4-1 . Privilege-Mode Configuration Bits 



REGISTER 


BIT 


SCCR1 


MEMORY DISABLE 
AUTOWAIT DISABLE 


SCCR2 


PRIVILEGE DISABLE 

POWERDOWN/IDLE 

HALT/STANDBY 

INT NMI 

OSC FLT DISABLE 

OSC FLT RST ENA 


T1CLT1 


WD IMPUT SELECT (2-0) 
WD OVERFL TAP SEL 


SPIPRI 


SPI PRIOftlTV 


SCIPRI 


SCI TX PRIORITY 


SC! RX PRIORITY 


T1PRI 


T1 PRIORITY 


T2PRI 


T2 PRIORITY 


ADPRI 


AD PRIORITY 



The only way to change the privilege bits after leaving the privilege mode is 
to reset the processor and then program the control registers. The write protect 
override (WPO) used for the EEPROM, has no effect on the privileged bits. 



4.1.2 Oscillator Fault 



The processor contains circuitry to monitor the oscillator operation and to 
indicate whenever the oscillator runs outside the normal operating range. The 
oscillator fault detection circuit will always trigger below 20 kHz and never 
above 500 kHz. 

Whenever this circuitry detects oscillator operation below the trigger level, the 
circuit stops the processor. The oscillator monitoring circuit can also pull the 
RESET pin low causing external devices to reset along with the processor. 
Three bits control and monitor the operation of the Oscillator Fault circuitry: 
OSC FLT FLAG, OSC FLT DISABLE, and OSC FLT RST ENA. These bits are 
described further in Section 4.1 .5. 



4.1.3 Automatic Wait States 



If an application system uses peripherals or expansion memory with slower 
access time than the TMS370 processor, wait states are required. In some 
systems this involves complex additional circuitry, but the TMS370 series 
provides for the automatic addition of wait states which can slow the 
processor's access time to a compatible period. 

In addition, the TMS370 series has a WAIT pin which can hold the processor 
in a wait state indefinitely. Two bits control the insertion of the Automatic 
wait state: the PF AUTO WAIT bit and the AUTOWAIT DISABLE bit. The PF 
AUTO WAIT bit controls the higher four frames (64 bytes) of the peripheral 
file so that these frames can be migrated off-chip. The AUTOWAIT DISABLE 
controls all other external memory. 

When the AUTOWAIT DISABLE bit equals 1, any access to external memory 
(excluding the PF file) takes 2 system clock cycles to complete. When 



4-3 



System Configuration 



AUTOWAIT DISABLE equals 0, the access takes 3 cycles. The reset value of 
this bit selects the slower 3-cycle access. 

When the PF AUTO WAIT bit equals 1, memory access to the external 
peripheral files takes 4 system clock cycles. When the PF AUTO WAIT equals 
0, the memory is treated like any external memory and the AUTOWAIT 
DISABLE bit selects the number of cycles per access as either 2 or 3 cycles. 
Table 1 3-1 summarizes the effects of the Wait State Control bits. 



Table 4-2. Wait State Control Bits 



Wait State 
Control Bits 


No. of Clock Cycles 
per Access 


PF Auto 
Wait 


Autowait 
Disable 


PF 
File 


External 
Memory 








3 


3 





1 


2 


2 


1 





4 


3 


1 


1 


4 


2 



An external device can pull the WAIT input pin low and cause the processor 
to wait an indefinite number of clock cycles for its data. When the wait line 
is released, the processor resynchronizes wit h the rising edge of the clock out 
signal and continues with the program. The WAIT pin is sampled only during 
external memory cycles. 



Note: 



When constructing an applicati on ci rcuit with expansion memory, do not 
forget to connect an unneeded WAIT line to Vcc. 



4.1.4 Powerdown and Idle Modes 

Each TMS370 device has two low-power modes and an Idle mode. The 
powerdown modes reduce the operating power by reducing or stopping the 
activity of various modules whenever processing is not needed. The processor 
has two types of powerdown modes, the Halt mode and the Standby mode. 

The Standby mode stops the internal clock in every module except the Timer 
1 module. The Timer 1 module continues to run and can bring the processor 
out of the Standby mode. 

The Halt mode stops the internal clock which stops processing in all the 
modules providing the lowest power consumption. 

Bits 6 and 7 of SCCR2 select the Halt, Standby, or Idle modes. The Idle mode 
(which is not a low-power mode) is a state which waits for the next interrupt. 
Executing an IDLE instruction causes the processor to enter one of the two 
powerdown modes or the simple Idle mode depending on SCCR2.6 and 
SCCR2.7. The powerdown and Idle mode selection bits are summarized in 
Table 4-3 



4-4 



System Configuration 



Table 4-3. Powerdown/ldle Control Bits 



Powerdown Control Bits 


Mode 
Selected 


Pwrdwn/ 

Idle 
(SCCR2.6) 


Halt/ 

Standby 

(SCCR2.7) 


1 





Standby 


1 


1 


Halt 





xt 


Idle 



tdon't care 



These modes and the methods of exiting the modes are discussed further in 
Section 4.1.4.1 and Section 4.1.4.2. 

In the Standby and Halt mode, the following information is retained: 

• The CPU registers: 

PC 

Status 
- Stack pointer 

• The contents of the RAM 

• The Digital output data registers 

• The Digital output ports remain active 

• Control and status registers of all the modules including the timer con- 
tents and the watchdog counter. 

If the Serial Peripheral Interface (SPI) or Serial Communications Interface 
(SCI) is in the process of receiving or transmitting data, that data may be lost. 
The results of an A-to-D conversion in process will be invalid when a power- 
down mode is entered. 

The watchdog mode (described in Section 7) should be used with caution in 
the powerdown modes since the watchdog stops counting in both power- 
down modes. If the program executes an IDLE instruction without the inter- 
rupts enabled (described in Section 4.1.4.1 and Section 4.1.4.2), then only a 
reset can start the processor running again. 



4.1.4.1 Standby Mode 



The Standby mode uses less power than the normal operating mode but more 
than the Halt mode. The Standby mode stops the clocks to every module 
except the Timer 1 module. The Timer 1 module can bring the processor out 
of this low power mode if the interrupts are enabled. To enter this mode set 
the PWRDWN/IDLE bit (SCCR2.6) and clear the HALT/STANDBY bit 
(SCCR2.7). The next execution of an IDLE instruction causes the processor 
to enter the Standby mode. 



4-5 



System Configuration 



The processor can exit the Standby mode by one of the following four 
methods. 

• Reset 

• External Interrupt 1 , 2, or 3 if enabled 

• Low level on the RXD pin if, the SCI RX interrupt and receiver are ena- 
bled (described in Section 9) 

• Timer 1 interrupt if enabled (described in Section 7) 

For additional Standby Mode power savings, see Section 4.1 .4.3. 

4.1.4.2 Halt Mode 

The Halt mode stops all internal operations (including Timer 1 ) and uses the 
least power of the low power modes. Timer 1 can not bring the processor out 
of this low-power mode. To select the Halt mode, set the PWRDWN/IDLE bit 
(SCCR2.6) and the HALT/STANDBY bit (SCCR2.7); then execute an IDLE 
instruction. 

The processor can exit the Halt mode by the following three methods. 

• Reset 

• External Interrupt 1, 2, or 3 if enabled 

• Low level on the RXD pin, if the SCI RX interrupt and receiver are ena- 
bled 

4.1.4.3 Oscillator Power Bit 

The OSC POWER bit (SCCR0.6) allows additional Stand-by mode power 
savings. When in effect, this feature reduces the oscillator drive current and 
disables the oscillator fault detection circuitry. The OSC POWER bit can be 
used effectively between 2 MHz and 12 MHz. For power reduction specifi- 
cations, see Tables 1 5-3 and 1 5-1 3. 



4-6 



System Configuration 



4.1.5 System Control Registers 



Each System Control register is summarized in the following charts with 
definitions 

System Control and Configuration Register (SCCRO) 
[Memory address - 101 Oh] 



Bit#- 


7 


6 


5 


4 


3 


2 


1 





P010 


COLD 
START 


osc 

POWER 


PF 
AUTO 
WAIT 


OSC 

FLT 

FLAG 


MODE 

PIN 

WPO 


MC 

PIN 

DATA 


— 


jJP/MC 
Mode 



RC 



RP-0 



RW-0 RW-t 



R-t 



R-t 



R-t 



R = Read, W=Write, P=Write only in Privilege mode, C=Clear only, 
-n= Value after RESET, f= see bit description 

Bit - kiP/pC MODE. Microprocessor/Microcomputer Mode 

This bit indicates the current operating mode (as described in Section 3.4). 

= Currently operating in microcomputer mode. 

1 = Currently operating in microprocessor mode. 

Bit 1 - Reserved. Read data is indeterminate. 

Bit 2 - MC PIN DATA. Mode Control Pin Data. 

This bit shows the current status of the MC pin. 

= Voltage on the MC pin is a logic level. 

1 = Voltage on the MC pin is a logic 1 level. 

Bit 3 - MC PIN WPO. Mode Control Pin Write Protect Override status. 

This bit indicates whether or not the voltage on the MC pin is enough for WPO 
functions. (If this bit is set, then bit 2 is also set.) 

= Voltage on the MC pin is not enough to override write protection. 

1 = Voltage on the MC pin is enough for write-protect operation override. 

Protected bits in Data EEPROM and Program EEPROM can now be writ- 
ten to. Override voltage is nominally 12 volts. 

Bit 4 - OSC FLT FLAG. Oscillator Fault Flag. 

This flag is reset upon an initial power-up reset. A reset under power does not 
affect this flag. Therefore, this bit can be be polled to determine the source of 
a reset. 

= No oscillator fault found. 

1 = Oscillator Fault found. Oscillator period is now or was out of correct 

operating range. The Oscillator fault detect circuit triggers somewhere 
within the range of 20 kHz to 500 kHz. 

Bit 5 - PF AUTO WAIT. Peripheral File Automatic Wait Cycle. 

= Any access to the peripheral file will take 2 system clock cycles with no 

System Auto Wait (bit 4 of SCCR1 =1 ), or 3 system clock cycles with the 
System Auto Wait on (bit 4 of SCCR1 =0). (See Section 4.1 .3, page 4-3.) 

1 = Any access to the upper 4 frames of the peripheral file (address lOCOh to 

lOFFh) will take 4 system clock cycles to complete. This eases interface 
requirements for peripheral devices slower than the TMS370 processor. 
Normal full speed operation consists of 2 system clock cycles per access. 



4-7 



System Configuration 



Bit 6 - OSC POWER.Oscillator Power. 

This bit controls an oscillator power reduction feature. When this feature is in 
effect, the oscillator drive current is reduced and the oscillator fault detection 
circuitry is powered down. Current reduction is most useful in the Standby 
mode. For power reduction specifications, see Tables 15-3 and 15-13. 

= no oscillator drive current reduction. 

1 = oscillator drive current reduction. 
Bit 7 - COLD START. 

This bit does not change during a reset under power. 

= No power-up reset occurred since last writing a to this bit. 

1 = Power-up reset has occurred since last writing a to this bit, indicating 

one cause of a system reset. The Watchdog Overflow Flag and the 
Oscillator Fault Flag indicate two other causes of a system reset. A pro- 
gram may take different actions depending upon the source of the reset. 

Only writing a to this bit can clear the COLD START flag. 

System Control and Configuration Register 1 (SCCR1) 
[Memory Address - lOllh] 



Bit# 



P011 



7 


6 


5 


4 


3 


2 


1 





— 


— 


— 


AUTOWAIT 
DISABLE 


— 


MEMORY 
DISABLE 


— 


— 



RP-0 RP-+ 

R = Read, P=write only in privilege state, -n= Value after RESET (tsee bit description) 
Bits 0,1,3,5,6,7 - Reserved. Read data is indeterminate. 

Bit 2 - MEMORY DISABLE. 

This bit enables or disables the internal Program Memory (memory addresses 
7000h-7FFFh). This bit does not affect Data EEPROM or internal RAM. RESET 
initializes this bit to the state of the MC pin. Changes to this bit can occur only 
in the privilege state. 

= Enable internal Prog ram Memory and access internal memory at these 

locations. The EDS memory signal will not appear during access to 
locations 4000h-7FFFh. 

1 = Disable internal Program Memory and make all memory accesses to these 

locations access external memory. An operat ion o n these locations gen- 
erates an external memory bus cycle with the EDS memory signal validat- 
ing the access. This bit disables the Program EEPROM control register, 
PEECTL (described in Section 6.2 on page 6-9), if applicable. 

Bit 4 - AUTOWAIT DISABLE. Automatic Wait State Disable. 

This bit, which is cleared at reset, causes an extra cycle to be added to all 
external bus accesses in order to accommodate slower memory. 

= Enable the Autowait feature and make external bus access 3 system clock 

cycles long. 

1 = Disable the Autowait feature and make external bus access 2 system clock 

cycles long. 

Changes to this bit can occur only in the privilege state. If the Peripheral File 
Autowait bit in SCCRO is set, external peripheral the AUTOWAIT DISABLE bit. 



4-8 



System Configuration 



Bit# 



P012 



System Control and Configuration Register 2 (SCCR2) 
[Memory Address - 1012h] 



HALT/ 
STANDBY 


PWR- 
DWN/ 
IDLE 


OSC 

FLT RST 

ENA 


BUS 
STEST 


CPU 
STEST 


OSC 

FLT 

DISABLE 


INT1 
NMI 


PRIV- 
ILEGE 
DISABLE 



RP-0 



RP-0 



RP-0 



RP-0 



RP-1 



RP-0 



RP-0 



RS-0 



R = Read, P=Write only in privilege state, S=Set only, -n= Value after RESET 

Bit - PRIVILEGE DISABLE. Privilege Mode Disable. 

Many bits controlling the system configuration can only be changed while in 
the privilege mode. After setting the system configuration bits, write a 1 to the 
Privilege Disable bit to disable the privilege mode and lock out any changes 
to the privilege protected bits. Only a Reset can clear the Privilege Disable bit. 

= System is not operating in the privilege mode. 

1 = System is operating in the privilege mode. 

Bit 1 - INT1 IMMI. Interrupt 1, Non-Maskable Interrupt. 

This bit determines whether Interrupt 1 is maskable or non-maskable (NMI). 
When Interrupt 1 is non-maskable, it is the second highest priority interrupt 
(Reset is highest) and unaffected by the interrupt mask and level bits 
(described in Section 5.1.2) The NMI mode disables the enable and priority 
select bits of the Interrupt 1 control register. The program can change this bit 
only in the privilege mode. 

= Interrupt 1 is maskable. 

1 = Interrupt 1 is non-maskable (NMI). 

Bit 2 - OSC FLT DISABLE. Oscillator Fault Disable. 

This bit controls circuitry which monitors the oscillator. If this circuitry is ena- 
bled and the oscillator falls outside of the correct voltage and frequency range, 
the processor enters an Oscillator Fault Halt. The oscillator fault circuitry will 
trigger below 20 kHz and may trigger anywhere between 20 kHz and 500 kHz 
500 kHz. The only exit from this halt state is a Reset. If the Oscillator Fault 
Reset Enable bit (SCCR2.5) is 1 , entry to the Fault Halt triggers a system reset. 
Changes to this bit can occur only in the privilege state. 

= the oscillator fault circuitry is enabled. 

1 = the oscillator fault circuitry is disabled; no attempt is made to halt or reset 

the processor if the oscillator falls out of range. 

Bit 3 - BUS STEST. 

This bit must be cleared (0) to ensure proper operation. 

Bits 4 - CPU STEST. 

This bit must be cleared (0) to ensure proper operation. 

Bit 5 - OSC FLT RST EIMA. Oscillator Fault Reset Enable. 

This bit determines whether or not a system reset is generated when an oscil- 
lator fault is detected. Changes to this bit can occur only in the privilege mode. 

= A Reset will not be generated if the oscillator falls below the correct 

operating range. (The monitor circuit also depends upon the Oscillator 
Fault Disable bit.) 

1 = A Reset is generated whenever the oscillator frequency falls below the 

correct operating range if SCCR2.2 is cleared. 



4-9 



System Configuration 



Bit 6 - PWRDWN/IDLE. Powerdown/ldle. 

This bit determines the mode entered by the CPU when an Idle instruction is 
executed. Changes to this bit can occur only in the privilege mode. 

= The processor will enter a idle mode when the program executes an IDLE 

instruction. The processor waits at the IDLE instruction until any enabled 
interrupt occurs. The processor then enters the interrupt routine and 
returns to the instruction after the Idle instruction. The idle is not a low- 
power mode. 

1 = The processor will enter a low power mode when the program executes 

an IDLE instruction. The HALT/STANDBY bit determines the type of low 
power mode. 

Bit 7- HALT/STANDBY. 

The following descriptions apply only if the Powerdown/ldle bit is set, other- 
wise the Halt/Standby bit has no effect. See Section 4.1.4 for a description of 
the Halt and Standby modes. Changes to this bit can occur only in the privi- 
lege mode. 

= When an IDLE instruction is executed, the processor will enter the Standby 

mode which stops program execution and disables the system clock to all 
"nonessential" peripherals. The system clock to the Timer 1 continues to 
run and the timer can generate an interrupt to bring the processor out of 
the Standby mode. 

1 = When an IDLE instruction is executed, the processor will enter the Halt 

mode which stops the internal oscillator and suspends the system and 
peripheral operations. This mode provides the lowest power consumption. 



4-10 



Digital I/O Configuration 



4.2 Digital I/O Configuration 



On TMS370 devices, the power, reset, MC, and crystal pins are dedicated to 
one function. Every other pin may be programmed to be a general purpose 
input and/or output, or a special function pin. Some of these pins are associ- 
ated with the functions of the peripheral modules. 

On TMS370Cx50 devices, 32 of a possible 55 I/O pins are dedicated to Ports 
A, B, C and D; each port has 8 pins each. 

On TMS370Cx10 devices, 13 of a possible 22 I/O pins are dedicated to Ports 
A and D. Port A contains 8 pins and Port D contains 5 pins. 

Frame 2 of the peripheral file (memory addresses 1020h-102Fh) contain the 
control registers for reading, writing and configuring Ports A, B, C, and D. 
These registers are shown in Figure 4-2. 



PERIPHERAL FILE FRAME 2: DIGITAL PORT CONTROL REGISTERS 



ADDR 


PF 


1020h 


20 


1021h 


21 


1022h 


22 


1023h 


23 


1024h 


24 


1025h 


25 


1026h 


26 


1027h 


27 


1028h 


28 


1029h 


29 


102Ah 


2A 


102Bh 


2B 


102Ch 


2C 


102Dh 


2D 


102Eh 


2E 


102Fh 


2F 



BIT 7 


BIT 6 


BIT 5 


BIT 4 


BIT 3 


BIT 2 


BIT1 


BIT 


RESERVED 


PORT A CONTROL REGISTER 2 


PORT A DATA 


PORT A DIRECTION 


RESERVED 


PORT B CONTROL REGISTER 2 


PORT B DATA 


PORT B DIRECTION 


RESERVED 


PORT C CONTROL REGISTER 2 


PORT C DATA 


PORT C DIRECTION 


PORT D CONTROL REGISTER 1 


PORT D CONTROL REGISTER 2 


PORT D DATA 


PORT D DIRECTION 



AP0RT1 

AP0RT2 

ADATA 

ADIR 

BP0RT1 

BP0RT2 

BDATA 

BDIR 

CP0RT1 

CP0RT2 

CDATA 

CDIR 

DP0RT1 

DP0RT2 

DDATA 

DDIR 



Figure 4-2. Digital Port Control Registers 



4-11 



Digital I/O Configuration 



Each port has four control registers associated with it. They are: 

Port X Control Register 1 (XP0RT1 ) 
Port X Control Register 2 (XP0RT2) 
Port X Data (XDATA) 
PortX Direction (XDIR) 

he same bit position of each of these register affects the corresponding bit 
in the port. For example, Bit of registers DP0RT1, DP0RT2, DDATA and 
DDIR control Port D, bit 0. This is illustrated in Figure 4-3. 



7 -I- -" r r- T - 

1 1 1 11 1 1 1 

BIT 7 1 BIT 6 ! BIT 5 ! BIT 4 I BIT 3 i BIT 2 • BIT 1 ■ BIT i 
1 1 1 1 1 1 1 1 
1 1 1 1 1 1 1 1 


. 


1 


1 I M ,i .1 


Br 


■ 7 


Br 


■ 6 


BIT 5 


BIT 4 


BIT 


3 


BIT 


2 


BIT 1 


BIT 

























































































































































PORT X 



PORT D CONTROL 
REGISTER 1 
(DP0RT1 ONLY) 



PORT D CONTROL 
REGISTER 2 (DP0RT2) 



PORT D DATA (DDATA) 



PORT D DIRECTION (DDIR) 



Figure 4-3. Port Control Register Operation 



Bits from the XP0RT1 and XP0RT2 registers determine the function of the 
corresponding port pin, either a I/O, data, address, or control signal depending 
on the port. The same bit from the XDIR register determines the direction 
(input or output) if the pin has been defined as a I/O pin. The same bit from 
the XDATA register is the bit to write to or read from if the pin has been 
defined as a I/O pin. 

Figure 4-4 shows the function that each pin can serve depending on which 
port contains the pin. Definitions of the memory expansion signals of Function 
A and Function B follow the figure. 



4-12 



Digital I/O Configuration 









FUNCTION 
A 


FUNCTION 

B 
(/iP MODE) 




INPUT 


OUTPUT 


PORT PIN 


XP0RT1 = 0^ 

XP0RT2 = 

XDATA = y 

XDIR = 


XP0RT1 = 0^ 
XP0RT2 = 
XDATA = q 
XDIR = 1 


XP0RT1 = 0^ 
XP0RT2 = 1 
XDATA = X 
XDIR = X 


XP0RT1 = 1^ 
XP0RT2 = 1 
XDATA = X 
XDIR = X 


A 0-7 


DATA IN y 


DATA OUT q 


DATA BUS 


RESERVED 


B 0-7 


DATA IN y 


DATA OUT q 


LOW ADDR 


RESERVED 


C 0-7 


DATA IN V 


DATA OUT q 


HI ADDR 


RESERVED 


D 
D 1 
D 2 
D 3 
D 4 
D 5 
D 6 
D 7 


DATA IN y 
DATA IN y 
DATA IN y 
DATA IN y 
DATA IN y 
DATA IN y 
DATA IN y 
DATA IN y 


DATA OUT q 
DATA OUT q 
DATA OUT q 
DATA OUT q 
DATA OUT q 
DATA OUT q 
DATA OUT q 
DATA OUT q 


UBE2 

CSH3 
CSH2 
CLKOUT 
R/W 
CSPF 
CSH1 
CSEI 


OCF 

CLKOUT 
R/W 

EDS 
WAIT 



XP0RT1 = 1 
XP0RT2 
XDATA 
XDIR 
^DPORT ONLY 



ii} 



NOT DEFINED 



Figure 4-4. Port Configuration Registers Set-Up 



LOW ADDR/HI ADDR - External memory address bus. Output only. 
DATA BUS - External data bus. Input and output. 



EDS - 



CSHI 



CSH2 - 



CSH3 - 



CSEI - 



External Data strobe: This sign al g oes low during external memory 
operations. The rising edge of EDS validates the r ead input data and 
the write data is available after the falling edge of EDS. 

Chip Select Half 1 : This signal has the same timing as EDS but it only 
goes active during access to the upper half of memory (locations 
8000h-FFFFh). Used to select banks of memory. Setting this pin to 
a high-level general-purpose output disables the bank. 

Chip Select Half 2: This signal has the same timing as EDS but it only 
goes active during access to the upper half of memory (locations 
8000h-FFFFh). Used to select a second bank of memory. Setting 
this pin to a high-level general-purpose output disables the bank. 

Chip Select Half 3: This signal has the same timing as EDS but it only 
goes active during access to the upper half of memory (locations 
SOOOh-FFFFh). Used to select a third bank of memory. Setting this 
pin to a high-level general-purpose output disables the bank. 

Chip Select Eighth 1: This signal has the same timing as EDS but it 
only goes active during accesses to an eighth of memory (locations 
2000h-3FFFh). Used to select banks of memory. Setting this pin to 
a high-level general-purpose output disables the bank. 



4-13 



Digital I/O Configuration 



CSE2 - Chip Select Eighth 2: This signal has the same timing as EDS but it 
only goes active during accesses to an eighth of memory (locations 
2000h-3FFFh). Used to select a second bank of memory. Setting 
this pin to a high-level general-purpose output disables the bank. 



CSPF - Chip Select Peripheral File: This signal has the same timing as EDS 
but it only goes active during access to external frames of the pe- 
ripheral file (locations lOCOh-IOFFh). 

CLKOUT - Clock Output: Outputs one quarter of the crystal or external oscil- 
lator frequency. Used to synchronize external peripherals. 

R/W - Read or Write operation: Goes high at the beginning of read oper- 
ations and low during write operations. 



WAIT - WAIT input: An external, low signal applied to this pin, when sam- 
pled, causes the processor to hold the information on the expansion 
bus for 1 or more extra clock ou t cyc les. This pin is sampled during 
the rising edge of CLKOUT after EDS goes active. 

OCF - Opcode Fetch: Goes low at the beginning of a memory read opera- 
tion that fetches the first byte of an instruction. It then resumes its 
high level at the end to the Opcode fetch cycle. 

The Pre-decoded chip selects allow the TMS370 to access external addresses 
with a minimum of external logic. In many cases no external logic is necessary 
between the TMS370 and the peripheral device because of the pre-decoded 
chip selects and the non-multiplexed bus. Another advantage of the chip 
selects is the abi lit y to do e asy m emory bank selection. Without bank 
selection, the CSHI, CSEl, and CSPF signals can easily access about 40 kilo- 
bytes of memory in the three different areas. With bank selection, the proces- 
sor can access 1 1 2 kilobytes of memory. 



4-14 



Digital I/O Configuration 



Example 4-1. Digital Ports Set-up Example 

To illustrate configuring the Digital Ports, assume that a TMS370C050 is to operate in the 
expanded microcomputer mode, and that 2 kilobytes of memory is needed at 2000h to 
27FFh. The top half of the figure below shows the port configuration wanted. Port A is set 
as the external data bus. Port B is the low-order byte of the address bus. Bits through 2 
of Port C are the high-order address bits of the eleven bits necessary to access 2 kilobytes 
of memory. Bits 4 through 7 of Port C are set as I/O input. In Port D, bit 7 is the chip select 
signal to access 2000h to 3FFFh; and bit 4 is used for external memory control signal R/W. 
The remaining bits of Port D are used as I/O output. 



PORT 
A 



BIT 7 


BIT 6 


BITS 


BIT 4 


BIT 3 


BIT 2 


BIT 1 


BITO 








r>ATA ni le 








1 1 1 1 1 1 1 1 



-1 1 r- 

ADDRESS BUS- 



1/0 IN ■ 



ADDRESS . 
BUS 



CSE1 -^1/0 OUT-^ R/W 



I/O OUT 



PORT A CONTROL REGISTERS 



1021h 
1022h 
1023h 

1025h 
1026h 
1027h 

1029h 
102Ah 
102Bh 

102Ch 
102Dh 
102Eh 
102Fh 



1 


1 


1 


1 


1 


1 


1 


1 


X 


x 


X 


X 


X 


X 


X 


X 


x 


X 


X 


X 


X 


X 


X 


X 



PORT B CONTROL REGISTERS 



1 


1 


1 


1 


1 


1 


1 


1 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 



PORT C CONTROL REGISTERS 


















1 


1 


1 


X 


X 


X 


X 


X 


X 


X 


X 

















X 


X 


X 



PORT D CONTROL REGISTERS 



























1 








1 














X 


q 


q 


X 


q 


q 


q 


q 


X 


1 


1 


X 


1 


1 


1 


1 



MOV #OFFh, P021 
MOV )»OFRi, P025 

MOV #007h, P029 

MOV #0. P02B 

MOV #0, P02C 
MOV #090h, P02D 

MOV #OFFh, P02E 



The bottom half of the above figure shows the port control registers set up to establish the 
configuration shown in the top half of the figure. To determine the bits needed to set the 
registers, use Figure 4-4. For example, to set Port A as the data bus, find Port A in the left 
hand column of Figure 4-4. Look across the row to find "Data bus", then follow the column 
up to find 

1 

X 
X 

in the column heading. These are the bits needed to set each Port A bit as a data bus. 

The assembly language instructions on the right of the preceding figure show one method 
of setting up the registers to the left. The "Pxxx" operand indicates peripheral file access (See 
Section 12 for more information on peripheral file instructions). 



4-15 



Digital I/O Configuration 



4.2.1 Microcomputer Mode 



Initializing the device to the microcomputer mode forces Ports A,B,C and D 
to General Purpose high impedance inputs. The program can set the control 
bits to change the function of the port pins to one of four functions: General 
Purpose Output, General Purpose Input, Function A, or Function B. 

When changing a pin from an general-purpose input pin to an output pin, 
write to the Data register first to set up the data and then set the data direction 
register. This prevents unknown data on the pin from interfering with the 
external circuitry. 



4.2.2 Microprocessor Mode 



Initializing the TMS370Cx50 to the microprocessor mode forces Ports A,B,C 
and D to Function B as shown in Figure 4-4. Port A is the data bus. Port B 
is the low-order-address bus and Port C is the high-order-address bus in this 
mode. The TMS370Cx10 is not defined for operation in the memory expan- 
sion modes so the device must be powered up in the Microcomputer mode. 

When operating in the microprocessor mode, any access to the Port peripheral 
frame, 1 020-1 02F, is decoded as external address. Memory accesses to this 
frame can control external hardware which emulates the digital I/O functions. 
Write operations to this frame still update the internal registers which is useful 
when operating in microcomputer mode with internal memory disabled. 

The TMS370 in the microcomputer mode can individually reconfigure any 
address, data, or control signal to use only the necessary signals and leave the 
other signals on the port for general purpose I/O operations. 

Figure 4-5 shows an example of the TMS370C850 interfaced to 1 1 2 kilobytes 
of external memory. The Function-A chip-select signals are used to enable 
one of three banks of EPROM, an external peripheral device, and one of two 
banks of static RAM. In this example, all eight bits of port A are used as the 
data bus, all eight bits of port B are used as the address LSB, and seven port 
C bits are used to complete the 1 5 bit address bus. 



4-16 



Digital I/O Configuration 



-vcc 



U1 



R/W 
CSE2 
CSET 
CSPF 
CSH3 



ADDRESS 0-14 

DATA 0-7 

MC 




vss 



U1 - TMS370C850 8-BIT MICROPROCESSOR 
U2, U3, U4 - TMS370C850 32K x 8 EEPROM 
U5 - UNSPECIFIED 64 BYTE MEMORY 
U6, U7 - HM6264-15 8K x 8 RAM 



Figure 4-5. System Interface Example 



4-17 



Digital I/O Configuration 



4-18 



introduction 



TMS370 Famiiy Devices 



CPU and iVIemory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module Ml* 



Analog-To-Digitai Converter Module 



Assembly Language instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer information 



Appendixes 



5. Interrupts and System Reset 

This section covers the following topics: 

Section Page 

5.1 Interrupts 5-2 

5.1.1 Interrupt Operation 5-2 

5.1.2 External Interrupts 5-5 

5.1.3 Interrupt Control Registers 5-8 

5.1.4 Multiple Interrupt Servicing 5-11 

5.2 Resets 5-1 2 



5-1 



Interrupts 



5.1 Interrupts 



The TMS370 programmable interrupt structure allows flexible on-chip and 
external interrupt configurations to meet real-time interrupt-driven application 
requirements. 

Whenever an internal or external circuit requests an enabled interrupt, the 
processor finishes the current instruction and then fetches, from the Interrupt 
Table, the address of the appropriate interrupt service routine. The processor 
then pushes the contents of the program counter and status register onto the 
stack and begins execution at the interrupt service routine address found in the 
Interrupt Table. When the interrupt service routine completes, the program 
executes a RTI (Return from Interrupt) instruction which pops the previous 
status-register and program-counter contents from the stack. The processor 
resumes execution from the point of interruption. 



5.1 .1 Interrupt Operation 



The hardware interrupt structure includes two selectable priority levels as 
shown in Figure 5-1 . Interrupt level 1 has a higher priority than interrupt level 
2. The two priority levels can be independently masked by clearing the global 
interrupt enable bits (IE1 and IE2) of the Status Register (described in Section 
3.2.2 on page 3-4). 

During system initialization, the application program can assign each system 
interrupt independently to either the high or low priority level. The program 
can reassign priority levels at any time except for those priority levels which 
are protected by the Privilege Mode. Within each level, hardware determines 
the interrupt priority. 

The processor services the pending interrupts upon completion of current 
instruction execution, depending on their interrupt mask and priority condi- 
tions. The processor services all enabled Level 1 interrupts before servicing 
any Level 2 interrupts. Within each level, the processor services the highest 
priority interrupts first. The hardware priorities are shown in Table 5-1. 



5-2 



Interrupts 



TIMER 1 



CO 

oo 

2 




OVERFLOW 
COMPARE 
EXT EDGE 
COMPARE 
IN CAPTURE 
WATCHDOG 




'T1 PRI 



EXT INT 1 



INT1 



' INT1 PRI 



CPU 



IE1 



IE2 



o-^ 
o-^ 



NON- 
MASKABLE 
INTERRUPT 

PRIORITY 
LOGIC 



LEVEL 1 INT 
LEVEL 2 INT 



Figure 5-1. Interrupt Control 



TMS370Cx50 devices have ten hardware system interrupts as shown in Table 
5-1. TMS370Cx10 devices have the first six interrupts shown non-shaded in 
this table. Each system interrupt has a dedicated interrupt vector located near 
the end of program memory (locations 7FECh-7FFFh) which contains the 
address of the interrupt service routine. A system interrupt may have multiple 
interrupt sources (for example, SCI RX has two interrupt sources). 

The application program can individually enable or disable all of the interrupt 
sources using local interrupt enable control bits in the associated peripheral 
file. Also, software can read each interrupt source's flag bit in order to deter- 
mine which interrupt source generated the system interrupt. 

The processor acknowledges an interrupt if its flag bit equals 1 and the inter- 
rupt is enabled. The interrupt service routine must clear all appropriate flag 
bits before leaving the routine to avoid immediately re-entering the same 
interrupt service routine. 

Interrupts are sampled and arbitrated by the CPU during every opcode fetch. 
If one or more requests are pending (and the appropriate enable bits are set 
in the Status register for maskable interrupts), then at the normal completion 
of the opcode fetch, the interrupt context switch begins. The new opcode is 
discarded and the program counter is rewound to point to the discarded 
instruction. Thus, at the completion of the interrupt service routine, the dis- 
carded instruction is fetched again. The context switch routine proceeds as 
follows. 

1) Increment the Stack Pointer (SP) and store the contents of the Status 
register (ST) at the location pointed to by the SP. 

2) Set the ST to OOh (disables further interrupt recognition). 

3) Obtain the identity of the interrupting peripheral. 

4) Rewind the Program Counter to point to the aborted opcode. 

5) Increment SP and store the original PC high byte at the location pointed 
to bytheSP. 



5-3 



Interrupts 



6) Get address (high byte) of interrupt service routine and store it in the 
PC high byte (PCH). 

7) Increment SP and store the original PC (low byte) at the location 
pointed to by SP. 

8) Get the interrupt-service-routine address (low byte) and store it in the 
PC low byte (PCL). 

9) Resume instruction execution with the new PC contents. 

It takes a minimum of 1 5 cycles from the time that an interrupt is triggered, to 
the reading of the first instruction of the interrupt service routine. The time 
depends on the instruction in progress when the interrupt is asserted and at 
what point during an instruction the interrupt is asserted. The worst case 
occurs if the interrupt occurs near the start of a Divide instruction; the pro- 
cessor may require up to 78 clock cycles to enter the interrupt service routine. 
If wait states are needed, the appropriate number of cycles must be added. 
Also, an external interrupt (INT1, INT2, or I NTS) requires 2 extra clock cycles 
to synchronize before the processor can detect it. 



Table 5-1 . Hard\/vare System Interrupts 



Interrupt Source 




Interrupt Flag 


System 
Interrupt 


Vector 
Address 


Priority f 


External RESET 
Watchdog Overflow 
Oscillator Fault Detect 


COLD START 

WD OVRFL INT FLAG 

OSC FLT FLAG 


RESETt 


7FFEh. 7FFFh 


1 


External INT1 


INT1 FLAG 


INT1T 


7FFCh, 7FFDh 


2 


External INT2 


1NT2 FLAG 


INT2t 


7FFAh. 7FFBh 


3 


External INT3 


INT3 FLAG 


INT3t 


7FF8h. 7FF9h 


4 


SPI RX/TX Complete 


SPI INT FLAG 


SPIINT 


7FF6h, 7FF7h 


5 


Timer 1 Overflow 
Timer 1 Compare 1 
Timer 1 Compare 2 
Timer 1 External Edge 
Timer 1 Input Capture 
Watchdog Overflow 


T1 OVRFL INT FLAG 
T1C1 INT FLAG 
T1C2 INT FLAG 
T1EDGE INT FLAG 
T1 IC INT FLAG 
WD OVRFL INT FLAG 


T1INT; 


7FF4h, 7FFSh 


6 


■ 6Cl fix Data Register W:' 
SCI RX Break Detect 


BRKDT FLAG 


" muTf 


7FF2h, .7FF3h 


7;- 


SCI TX Data Register Empty 


TXRDY FLAG 


TXtNT 


?FFOh. 7FF1h 


8 


Timer 2 Ovefflow 
Timer 2 Compare 1 
Tlrner 2 Compare 2 
Timer 2 External Edge 
Timer 2 input Capture 1 
Timer Z Input Capture 2 


TaC1 \m FLAG 
T2C2 INT FLAG 
T2EDQE INT FLAG 
TaCHHTFUQ 
TaC2INtFUG 


Tgim" 


7FEEH, ' 7FEFh 


9 


A-D Conversion Complete 


AD INT FiAG 


ADINT 


'7FE(ih, 7FS5h 


ld 



^Releases microcontroller from STANDBY and HALT low-power modes. 
'Releases microcontroller from STANDBY low-power mode. 
§ Relative priority within an Interrupt level. 



5-4 



Interrupts 



5.1.2 External Interrupts 



External pins INT1, INT2 and INT3 allow external devices to interrupt the 
program and enter a specific interrupt service routine. The INT1, INT2, and 
INT3 control registers in peripheral file frame 1 govern the software config- 
uration of the external interrupts. Figure 5-2 shows these registers. 



PERIPHERAL FILE FRAME 1: EXTERNAL INTERRUPT CONTROL REGISTERS 



ADDRESS PF 
1017h P017 



1018h P018 



1019h P019 



BIT 7 


BIT 6 


BIT 5 


BIT 4 


BIT 3 


BIT 2 


BIT 1 


BIT 


INT1 
FLAG 


INT1 
PIN DATA 











INT1 
POLARITY 


INT1 
PRIORITY 


INT1 
ENABLE 


INT2 
FLAG 


INT2 
PIN DATA 





INT2 
DATA DIR 


INT2 
DATA OUT 


INT2 
POLARITY 


INT2 
PRIORITY 


INT2 
ENABLE 


INT3 
FLAG 


iNT3 
PIN DATA 





INT3 
DATA DIR 


INT3 
DATA OUT 


INT3 
POLARITY 


!NT3 
PRIORITY 


INT3 
ENABLE 



INT1 



INT2 



INT3 



Figure 5-2. Peripheral File Frame 1 - External Interrupt Control Registers 



Software can configure each external interrupt individually, through the inter- 
rupt polarity bits, to trigger on either a rising edge or a falling edge. If the 
interrupt function is not required, the software can configure external inter- 
rupts INT2 and INT3 to be general purpose input/output pins, and INT1 to 
be an input pin. 

INT1 can be programmed to be a maskable or non-maskable interrupt. When 
INT1 is non-maskable, it cannot be masked by the individual or global mask 
bits. Remember that the INT1 NMI bit (SCCR2.1) is protected during non- 
privileged operation and should be configured during the initialization 
sequence following reset (see INT1 NMI bit description on page 4-9). 

The application program must configure the following bits for each interrupt 
to function correctly. The INT PRIORITY bit configures the interrupt as either 
a level 1 or a level 2 interrupt. The INT POLARITY bit selects the trigger as 
either a falling edge or a rising edge. The INT ENABLE bit allows the request 
to be transmitted to the CPU if either the I El or IE2 enable bit, whichever is 
appropriate, is enabled. 

The INT FLAG indicates that the selected edge (rising or falling) has occurred. 
If the enables are set, an interrupt is requested. This bit remains a 1 until the 
software or a RESET clears it. The INT FLAG bit is useful for programs which 
poll the interrupt flag instead of generating a system interrupt. 

The INT PIN DATA bit shows the level presently on the interrupt pin. This 
also allows the use of this bit as a simple input pin if the interrupt function is 
not needed. 



5-5 



Interrupts 



On interrupts 2 and 3, the INT DATA DIR determines if the pin functions as a 
general purpose output or as an input/interrupt pin. If you select the general 
purpose output function, then the value written by software to the INT DATA 
OUT bit determines the level of the output. 

All external interrupts can bring the processor out of both the halt and the 
standby low-power modes if the interrupt enable and the interrupt level mask 
are enabled. 



P017.6 




NMI 



1 = RISING "* 


D 

> Q 

CLR 


= FALLING 



P017.2 



POLARITY 




P017.7 P017.1 

OTHER LEVEL 2 INTERRUPTS —^ 
OTHER LEVEL 1 INTERRUPTS 



'STATUS REGISTER 
GLOBAL INTERRUPT 
ENABLE BITS 



Figure 5-3. Interrupt 1 Block Diagram 



5-6 



Interrupts 



P018.6 
P019.6 



P018.3 
P019.3 



INPUT 

PIN 

DATA 



INT 

PIN 



DATA 
OUT 



OTHER LEVEL 2 INTERRUPTS— 
OTHER LEVEL 1 INTERRUPTS-, 



l90 



P018.0 
P019.0 



Hd 

1 = RISING 



DATA 
DIR 



-OK 
I o- 

j = FALLING 



CLR 



ENABLE 



P018.4 
P019.4 



POLARIPr' 



P018.2 
P019.2 



-<yio- 



WRITE READ 
INT FLAG 



PRIORITY 
SELECT 



P018.1 
P019.1 



P018.7 
P019.7 



IE2 



sr 






IE1 



ST 



WAKE-UP 
CIRCUITRY 



LEVEL 2 INT REG 



LEVEL 1 INT REG 



STATUS REGISTER GLOBAL 
INTERRUPT ENABLE BITS 



Figure 5-4. Interrupts 2 and 3 Block Diagram 



5-7 



Interrupts 



5.1.3 Interrupt Control Registers 



Interrupt 1 Control Register (IIMT1) 
[Memory Address - 1017h] 



Bit# 



P017 



7 


6 


5 


4 


3 


2 


1 





INT1 
FLAG 


INT1 

Pin 

DATA 


... 


... 


... 


INT1 
POLARITY 


INT1 
PRIORITY 


INT1 
ENABLE 



RC-0 



R-0 



RW-0 



RW-0 RW-0 



BitO 



Bit 1 - 



R=Read, W=Write, C=Clear only, -n= Value after RESET 

INT1 ENABLE. Interrupt 1 Enable. 

This bit enables the interrupts for the INT1 pin. 

1 = Enable INT1 interrupts. 
= Disables INT1 interrupts. 

INT1 PRIORITY. Interrupt 1 priority. 

This bit determines interrupt level of the INT1 pin; either a high, level-1 inter- 
rupt or a low, level-2 interrupt. 



1 = Level 2 interrupt (low level). 

= Level 1 interrupt (high level). 

Bit 2 - INT1 POLARITY. Interrupt 1 Polarity. 

This bit determines whether INT1 triggers on a rising edge or a falling edge. 

1 = Triggers on a rising edge (low-to-high transition) 

= Triggers on a falling edge (high-to-low transition) 

Bits 3,4,5- Reserved. Read data is indeterminate. 

Bite - INT1 PIN DATA. Interrupt 1 Pin Data. 

This bit displays the current condition of the INT1 pin. 

1 = High level input voltage (V|h) at the INTl pin. 
= Low level input voltage (V|l) at the INTl pin. 

Bit 7 - INTl FLAG. Interrupt 1 Flag. 

This bit indicates that the selected transition on INTl has occurred. An inter- 
rupt can occur as long as this bit remains set, thus the application program 
must clear this bit during the interrupt handling routine. This bit is not affected 
by the Interrupt 1 Enable bit. 



5-8 



Interrupts 



Bit# 



P018 



RC-0 



R-0 



Interrupt 2 Control Register (INT2) 
[Memory Address - 1018h] 



INT2 
FLAG 


INT2 

PIN 

DATA 


— 


INT2 

DATA 

DIR 


INT2 
DATA 
OUT 


INT2 
POLARITY 


INT2 
PRIORITY 


INT2 
ENABLE 



RW-0 RW-0 RW-0 RW-0 



RW-0 



R = Read, W=Write, C=Clear only, -n= Value after RESET 

Bit - INT2 ENABLE. Interrupt 2 Enable. 

This bit enables the interrupts for the INT2 pin. 

1 = Enable INT2 interrupts. 

= Disables INT2 interrupts. 

Bit 1 - INT2 PRIORITY. Interrupt 2 Priority. 

This bit determines the interrupt level of the INT2 pin; either a high, level-1 
interrupt or a low, level-2 interrupt. 

1 = Level 2 interrupt (low level). 

= Level 1 interrupt (high level). 

Bit 2 - INT2 POLARITY. Interrupt 2 Polarity. 

This bit determines whether INT2 triggers on a rising edge or a falling edge. 

1 = Triggers on a rising edge (low-to-high transition). 

= Triggers on a falling edge (high-to-low transition). 

Bit 3 - INT2 DATA OUT. Interrupt 2 Data Out. 

If software configures the INT2 pin as an output pin (!NT2 DATA DIR = 1), 
then the value that the software writes to the INT2 DATA OUT bit determines 
the value of that output pin. 

Bit 4 - IIMT2 DATA DIR. Interrupt 2 Data Direction. 

The INT2 pin can be configured as either an output pin or as an input/interrupt 
pin. 

1 = INT2 pin is an output pin. 

= INT2 pin is an input/interrupt pin. 

Bit 5 - Reserved. Read data is indeterminate. 

Bit 6 - IIMT2 PIIM DATA. Interrupt 2 Pin Data. 

This bit displays the current value of the INT2 pin. 

1 = High-level input voltage (Vm) at the INT2 pin. 
= Low-level input voltage (ViJ at the INT2 pin. 

Bit 7 - INT2 FLAG. Interrupt 2 Flag. 

This bit indicates that the selected transition on INT2 has occurred. An inter- 
rupt can occur as long as this bit remains set, thus the program must clear this 
bit during the interrupt handling routine. This bit is not affected by the INT2 
ENABLE bit. 



5-9 



Interrupts 



Bit#- 



P019 



RC-0 



R-0 



Interrupt 3 Control Register (INT3) 
[Memory Address - 1019h] 



(NTS 
FLAG 


INT3 

PIN 

DATA 


— 


iNT3 

DATA 

DIR 


INT3 
DATA 
OUT 


INT3 
POLARITY 


INT3 
PRIORITY 


INT3 
ENABLE 



RW-0 RW-0 RW-0 RW-0 



RW-0 



R=Read, W=Write, C=Clear only, -n= Value after RESET 

Bit - IIMT3 ENABLE. Interrupt 3 Enable. 

This bit enables the interrupts for the INT3 pin. 

1 = Enable INT3 interrupts. 

= Disables INT3 interrupts. 

Bit 1 - INT3 PRIORITY. Interrupt 3 priority. 

This bit determines the interrupt level of the INT1 pin; either a high, level-1 
interrupt or a low, level-2 interrupt. 

1 = Level-2 interrupt (low level). 

= Level-1 interrupt (high level). 

Bit 2 - INT3 POLARITY. Interrupt 3 Polarity. 

This bit determines whether INT3 triggers on a rising edge or a falling edge. 

1 = Triggers on a rising edge (low-to-high transition). 

= Triggers on a falling edge (high-to-low transition). 

Bit 3 - INT3 DATA OUT. Interrupt 3 Data Out. 

If software configures the INT3 pin as an output pin (INT3 DATA DIR=1), 
then the value that the software writes to the INT3 DATA OUT bit determines 
the value of that output pin. 

Bit 4 - IIMT3 DATA DIR. Interrupt 3 Data Direction. 

The INT3 pin can be configured as either an output pin or as an input/interrupt 
pin. 

1 = INT3 pin is an output pin. 

= INT3 pin is an input/interrupt pin. 

Bit 5 - Reserved. Read data is indeterminate. 

Bit 6 - INT3 PIN DATA. Interrupt 3 Pin Data. 

This bit displays the current condition of the INT3 pin. 

1 = High-level input voltage (V|h) at the INT3 pin. 
= Low-level input voltage (V|l) at the INT3 pin. 

Bit 7 - INT3 FLAG. Interrupt 3 Flag. 

This bit indicates that the selected transition on INT3 has occurred. An inter- 
rupt can occur as long as this bit remains set, thus the program must clear this 
bit during the interrupt handling routine. This bit is not affected by the Inter- 
rupt 3 Enable bit. 



5-10 



Interrupts 



5.1.4 Multiple Interrupt Servicing 

When servicing an interrupt, the processor automatically clears the global 
interrupt enable bits I El and IE2. This prevents all other interrupts from being 
recognized during the execution of the interrupt service routine. Once the 
service routine is completed by executing the RTI (Return from Interrupt) 
instruction, the old Status Register contents are popped from the stack. This 
returns the IE1 and IE2 to their original conditions and allows any pending 
interrupts to be recognized. 

An Interrupt service routine can allow nested interrupts by executing the El NT, 
EINTL or EINTH instructions to set the global Interrupt Enable bits in the 
Status register. This permits other interrupts to be recognized during the ser- 
vice routine execution. When a nested interrupt service routine completes, it 
returns to the previous interrupt service routine when the RTI instruction exe- 
cutes. Too many nested interrupts could overflow the stack causing program 
failure. 



5-11 



Resets 



5.2 Resets 



The TMS370 has three possible reset sources: a low input to the RESET pin, a 
programmable watchdog timer timeout (described in Section 7.3, 7-17), or a 
programmable oscillator fault failure (described in Section 4.1.2, 4-3). After 
the occurrence of a reset, the program can interrogate the status bits (shown 
in Table 5-2) to determine the source of the reset in order to take appropriate 
action. If non e of the sources, indicated in Table 5-2, caused the interrupt 
then the RESET pin was pulled low by external hardware. 



Table 5-2. Reset Sources 



Register 


Address 


PF 


Bit# 


Control Bit 


Source of Reset 


SCCRO 


101 Oh 


P010 


7 


COLD START 


Determines Cold or Warm start reset. 


SCCRO 


101 Oh 


P010 


4 


OSC FLT FLAG 


Indicates oscillator out of range. 


Tl CTL2 


104Ah 


P04A 


5 


WDOVRFLINTFLAG 


Indicates watchdog timer timeout. 



The RESET pin sta rts the hardware initialization and ensures an orderly soft- 
ware startup. The RESET pin is an input/output pin. A low level pul se initi ates 
the reset sequence. The microcontroller is held in reset until the RESET pin 
goes inactive (high). If the reset input signal remains low f or less than eight 
system clock cycles, the processor holds the external RESET pin low for eight 
system clock cycles to reset external system components. 



Note: 

TMS370 family members with on-chip EEPROM require external RESET 
control during power transitions. The external RESET pin must be active 
(low) while Vcc 's below its minimum specified operating level, thereby 
ensuring the integrity of EEPROM contents. An active RESET prevents 
the EEPROM contents from being corrupted by improper instruction exe- 
cution due to insufficient Vqc supply voltage and ensures that the 
EEPROM write control registers (DEECTL, PEECTL) power up in the 
correct state when Vcc returns to its specified operating range. 



An application must activate the RESET pin at powerup, with an external input 
or a RC power-up reset circuit. Recall that the basic operating mode, micro- 
computer or micr oproce ssor, is determined by the vol tage le vel applied to the 
MC pin when the RESET pin goes inactive (high). The RESET pin can be pulled 
low at any time during operation to start the reset sequence immediately. 



5-12 



Resets 



The sequence of events during reset is as follows: 

1 ) Initialize CPU registers: ST=00h, SP-01 h. 

2) Initialize registers A and B to OOh (no other RAM is changed). 

3) Read the contents of 7FFFh and store in the PC low byte (PCL). 

4) Read the contents of 7FFEh and store in the PC high byte (PCH). 

5) Start user program execution with an opcode fetch from the address 
pointed to by the PC. 

When the Watc hdog o verflow or the Oscillator Fault detection circuit gener- 
ates a reset, the RESET pin is pulled low in order to reset other external com- 
ponents in the system. 

During a reset, RAM contents (except for Register A and Register B) are 
unchanged and the majority of the peripheral file bits are set to with the 
exception of the bits shown Table 5-3. 



Table 5-3. Control-Bit States Following Reset 



Register 


Control Bit 


Powerup 

Micro- 
computer 


Warm Reset 


Micro- 
computer 


Micro- 
processor 


SCCRO 


mP/mC Mode 
MC PIN DATA 
COLD START 
OSC FLT FLAG 




1 






t 
t 




PORTit 


all 8 bits 










P0RT2t 


all 8 bits 










71 CTL2 


WD OVRFL FLAG 





t 




TXCTL 


TX EMPTY 
TXRDY 


1 
1 


1 
1 




ADSTAT 


AD READY 


1 


1 


1 



tStatus bit corresponding to the active reset source is set, else no effect. 
tRefers to Port Control Registers A, B, C, and D. 



5-13 



Resets 



MANUAL 
RESET 



H 




TO OTHER DEVICES' RESETS 



51 kD 



TMS370 



0.47;iF 



-»► RESET IN 



h-— RESET OUT 



Figure 5-5. Typical Reset Circuit 



5-14 



introduction 



TMS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPO Module mv 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



6. EEPROM Modules 



This section discusses the architecture and programming of the Data EEPROM 
modules on all TMS370 devices and the Program EEPROM module on 
TMS370C8xO devices. Additional information about the EEPROM modules is 
included in Section 13, Design Aids and Section 15, Electrical Specifications. 

This section covers the following topics: 

Section Page 

6.1 Data EEPROM Module 6-2 

6.1.1 Control Registers 6-2 

6.1.1.1 Write Protection Register (WPR) 6-2 

6.1.1.2 Data EEPROM Control Register (DEECTL) 6-4 

6.1.2 Programming the Data EEPROM 6-5 

6.1.3 Write Protection Register Operation 6-8 

6.2 Program EEPROM Module 6-9 

6.2.1 Program EEPROM Control Register (PEECTL) 6-10 

6.2.2 Programming the Program EEPROM 6-11 

6.2.3 Write Protection of Program EEPROM 6-12 



6-1 



Data EEPROM Module 



6.1 Data EEPROM Module 



The TMS370 Data EEPROM module is a 256-byte array configured into eight 
32-byte blocks at addresses, 1 FOOh-1 FFFh. This module also contains a volt- 
age generator which provides a special precise programming voltage to the 
EEPROM array. This special voltage helps Increase the reliability of the 
EEPROM and allows the TMS370 to program the EEPROM with a single Vqc 
voltage source. Each EEPROM module contains a voltage generator so a rou- 
tine can simultaneously program a byte of Data EEPROM and a byte of Pro- 
gram EEPROM without conflict. 

Reading the EEPROM module is identical to reading other internal memory 
and takes two system clock cycles. The CPU can fetch data and execute in- 
structions from the EEPROM arrays. The Data EEPROM module can be pro- 
grammed on either a byte or single-bit basis. The memory can also be 
protected from inadvertent writing with a write-protect feature. 

The Data EEPROM is controlled by the DEECTL register and the Write Protect 
Register (WPR). The Data EEPROM control register (DEECTL) contains the 
bits needed to initiate and monitor EEPROM programming. The Write Pro- 
tection Register (WPR) contains the write protection bits for each 32-byte 
block of Data EEPROM. 

6.1.1 Control Registers 

The Data EEPROM can be write protected, block by block (32 bytes), with the 
WPR register. The DEECTL register determines the mode of programming and 
when programming is initiated. 

6.1.1.1 Write Protection Register (WPR) 

The WPR register provides write protection for Data EEPROM contents. The 
WPR is located in BLKO of the Data EEPROM at address 1 FOOh; therefore, the 
WPR itself is write protected whenever BLKO is protected. 

There are eight blocks of equal size in the Data EEPROM array. Each bit in the 
WPR corresponds to one of the blocks. Programming a bit in this register to 
a 1 protects the corresponding block. Figure 6-1 shows the block protected 
by each bit. 

Once block is protected, the write-protection configuration can not be 
altered unless write protection is overridden by placing the microcomputer into 
the Write Protection Override mode (12 volts on the MC pin). There is no 
write protection during a Write Protection Override, and the WPR is consid- 
ered a normal data location within the Data EEPROM array during this time. 



6-2 



Data EEPROM Module 



Write Protection Register (WPR) 
[Memory Address - IFOOh] 









MSB 














LSB 


1F00h 


WRITE PROTECT REGISTER 




BLK7 


BLK6 


BLK5 


BLK4 


BLK3 


BLK2 


BLK1 


BLKO 




BLKO 


1 








1F20h 


BLK1 




WRITE PROTECT REGISTER 


1F40h 


BLK2 


^ = NORMAL WRITE ACCESS 

1 = WRITE PROTECT BLOCK 


1F60h 


BLK3 




1F80h 


BLK4 




1FA0h 


BLK5 




1FC0h 


BLK6 




1FE0h 
IFFFh 


BLK7 





Figure 6-1. Write Protection Bits 



6-3 



Data EEPROM Module 



6.1.1.2 Data EEPROM Control Register (DEECTL) 

The DEECTL Register is located in the peripheral file at address P01A 
(101 Ah). Data EEPROM programming is controlled through this register. The 
following figure illustrates the bit definitions for the DEECTL register. 

Data EEPROM Control Register (DEECTL) 
[Memory Address - 101 Ah] 

Bit # - 
P01A 



7 


6 


5 


4 


3 


2 


1 





BUSY 


— 


— 


— 


— 


AP 


W1W0 


EXE 



R-t 



RW-0 



RW-0 



RW-0 



R = Read, W=Write, -n= Value after RESET (t-see Bit 7 description) 

Bit 0- EXE. Execute. 

Set this bit to initiate the write operation defined by the remaining control 
register bits. Clear this bit to terminate a programming operation in progress. 
If the application program reads a Data EEPROM location while the EXE bit is 
set, the processor reads the data being programmed into the EEPROM. If 
software attempts a write to the EEPROM while the EXE bit is set, the data byte 
is ignored. 

= Inactive. 

1 = Active. 

Bit 1 - W1 WO. Writel /WriteO. 

This bit determines whether the Ones or Zeroes programming mode is to be 
used (see Section 6.1.2, page 6-4). This bit is write protected whenever the 
EXE bit is set. 

= Write zeros. 

1 = Write ones. 

Bit 2- AP. Array Program. 

Set this bit to program the entire array with the value specified by the W1W0 
bit in a single programming cycle (refer to Section 15 for timing). Blocks 
protected in the WPR register are not programmed. This bit is write protected 
whenever the EXE bit is set. 

If BLKO is unprotected and W1W0 is zero, this function clears the WPR; any 
array locations previously protected will lose their protection, but their contents 
are not altered during the current programming cycle. 

= Array programming disabled. 

1 = Array programming enabled. 

Bit 3-6 Reserved. Read data is indeterminate. 

Bit 7 - BUSY. 

This bit is set during Data EEPROM programming to indicate that an operation 
is in progress. Reading any location of the EEPROM during programming 
returns the data being programmed. In order to let the EEPROM voltages sta- 
bilize, the BUSY bit is set for 128 cycles: 

1 ) after a reset, 

2) after an exit from a power-down state, and 

3) after programming the EEPROM. 

If an attempt is made to access the EEPROM during this 128 cycle period, the 
Data EEPROM holds execution of the processor by asserting the WAIT signal 
until the 128 cycles is complete. 

= EEPROM array is ready for access. 

1 = EEPROM array is not ready for access. 



6-4 



Data EEPROM Module 



6.1.2 Programming the Data EEPROM 

The procedure for programming the Data EEPROM is controlled by the 
DEECTL (P01A) and the WPR (1 FOOh) registers. Individual bits are pro- 
grammed to a 1 or under the control of the W1 WO bit and the EXE bit in the 
DEECTL register. When the W1 WO bit is set, bit positions set to 1 in the data 
byte are programmed to 1 in the EEPROM byte; zeros are not changed. When 
the W1 WO bit is cleared, bit positions set to in the data byte are programmed 
to in the EEPROM byte; ones are not changed. The EXE bit initiates 
EEPROM programming when set and disables programming when cleared. 
The WPR (1 FOOh) register must have the corresponding protection bit cleared 
or be in the WPO mode to enable a Data EEPROM write operati on. (To enter 
the WPO mode, place 12 volts to the MC pin while the RESET pin is a logic 
1.) 

To load the data byte into the EEPROM module, perform a memory write 
operation to the EEPROM at the desired address. The data byte is latched in 
the module, ready for the Execute command (EXE bit=1 ). 

Following the memory cycle to the EEPROM address, write 03h (for 
W1W0=1) or 01 h (for W1W0=0) to the DEECTL register to set the W1W0 
and EXE bits. The W1W0 and the EXE bits must remain unchanged for the 
duration of the EEPROM timing parameter of tw(PGM)B to insure proper 
programming. When the program time has elapsed, reset the EXE bit with 
another write operation to the DEECTL register. 

If W1W0=1, then the data which now resides in the programmed EEPROM 
location is the logical OR of the previous data stored in the location and the 
data written to the location. If W1W0=0, then the data which now resides in 
the programmed EEPROM location is the logical AND of the previous data 
stored in the location and the data written to the location. 

If a data value cannot be achieved by writing only ones or zeros, first perform 
the write-ones operation and follow it with a write zeros operation (or write 
zeros followed by write ones). Figure 6-2 illustrates these operations. In the 
programming operations, only the EEPROM bits that do not match the data 
bits are programmed. Therefore, there is no need to read the EEPROM value 
to determine what bits to program. 



6-5 



Data EEPROM Module 



DATA BYTE (5A) 



WRITE ONES (W1W0 = 1) < EEPROM BYTE (1F60h) X 



RESULT (LOGICAL OR) X 



WRITE ZEROS (W1W0 = 0) < 



DATA BYTE (5A) [o 
EEPROM BYTE {1F60h) [x 



RESULT (LOGICAL AND) [o 



omToI 



ME 



x|i|x| 



oTTTd 



xHH 



omo] 



Figure 6-2. EEPROM Programming Example 



The software should end the programming operation before entering a HALT 
or STANDBY state. When the microcomputer is in the HALT or STANDBY 
low-power mode, all operations of the data EEPROM module are stopped and 
all DEECTL bits are cleared. Any EEPROM programming operation in progress 
is aborted when the halt is entered, and the data at the address being pro- 
grammed is indeterminate. 



6-6 



Data EEPROM Module 



Example 6-1. Data EEPROM Programming Example 

The following subroutine loads the data byte 5A into the Data EEPROM 
location 1 F60h. Figure 6-2 illustrates the result of this subroutine. 



(a) 


DATA 


MOV 


#5Ah,A 






MOV 


A,lF60h 


(b) 




MOV 


#03,P01A 


(c) 




MOVW 


#2778, R017 


(d) 


DELAY 1 


INCW 


#-l,R017 


(e) 




JC 


DELAY 1 


(f) 




MOV 


#0,P01A 


(g) 




MOV 


#01,P01A 


(h) 




MOVW 


#2778, R017 


(i) 


DELAY 2 


INCW 


#-l,R017 


(J) 




JC 


DELAY2 


(k) 




MOV 


#0,P01A 



Write 5A to location lF60h 

Write Ones: W1W0=1, EXE=1 
Begin tw(PGM)B delay (10 ms) 

Decrement R017 

Jump to DELAY 1 if R017>0 
Clear DEECTL. EXE=0 
Write zeros: W1W0=0 EXE=1 
Begin tw(PGM)B delay (10 ms) 

Decrement R017 

Jump to DELAY2 if R017>0 
Clear DEECTL. EXE=0 



Load the value 5A into the Data EEPROM address 1 F60h (a). Begin a Write 
Ones programming sequence by (b) setting the W1W0 and EXE bits in the 
DEECTL register to a 1 . The programming delay parameter tw(PGM)B 
(1 ms for this example - see Section 1 5 for required timing) is taken care of 
with a delay loop (d,e). The number of loops required is #2278 (c), and can 
be derived in the following manner: 

1 ) Delay loop (d,e) requires 1 8 cycles to complete if a jump is taken. 

2) An operating frequency of 20 MHz results in a system cycle time of 
200 ns. 

3) The number of loops required is calculated as follows: 

loop count = tv\/(PGM) B / (system cycle time X delay loop cycle count) 

loop count = 1 ms / (200 ns X 1 8) = 1 ms / 3.6 |js = 2778 

Note: alternatively, a timer may be used for this delay. 

After the delay, clear the EXE bit (f), and continue the Write Zeros routine 
(g through k). The value "5A" has now been programmed into location 
1 F60h of the Data EEPROM. 

The BUSY bit is set during EEPROM programming to indicate an operation in 
progress. Reading any location of the Data EEPROM during programming 
returns the data being programmed. In order to let the EEPROM voltages sta- 
bilize, the BUSY bit remains set for 128 cycles: 

• after a reset, 

• after exit from a power-down state, and 

• after programming the EEPROM. 

If an attempt is made to access the EEPROM during this 128 cycle period, the 
Data EEPROM holds execution of the processor by asserting the WAIT signal 
until the 128 cycles is complete. 



6-7 



Data EEPROM Module 



6.1 .3 Write Protection Register Operation 

The Write Protection Register (WPR) allows the application program to guard 
any or all of the eight blocks of EEPROM shown in Figure 6-1, page 6-3. 
Each block has a representative bit in the WPR. The blocks to be protected 
have their corresponding bit set in the WPR. Block zero contains the WPR. 
Therefore, once the bit for block zero (BLKO) is set, WPR can no longer be 
changed unless the Write Protect Override mode is entered. 

The following example illustrates programming the WPR. In this example, the 
program protects blocks and 2. See Section 13 for more examples of pro- 
gramming the EEPROM module. 



DELAY 



MOV 


#05, A 


MOV 


A,lF00h 


MOV 


#3,P01A 


MOVW 


#2778, ROll 


INCW 


#-l,R011 


JC 


DELAY 


MOV 


#G,P01A 



Protect bits for BLKO and BLK2 
Set DEECTL to program I's 
Set WIWO and EXE bits 
10 ms delay loop 



;Clear WIWO and EXE bits 



6-8 



Program EEPROM Module 



6.2 Program EEPROM Module 

The following is a description of the Program EEPROM module used in the 
TI\/IS370 family. This module serves in place of the 4-kilobyte program ROM 
within the TMS370C850 and TMS370C810 for systems in prototype or small 
production runs. 

The module consists of a 4-kilobyte array of EEPROM at address locations 
7000h through 7FFFh. The CPU can fetch data and execute instructions from 
this memory space. Programming control logic for the Program EEPROM is 
located at address 1 01 Ch (P01 C). 

The CPU accesses the array with normal memory read cycles. Write cycles to 
the Program EEPROM require a special sequence of events. This sequence is 
similar as that for the Data EEPROM, except that the PEECTL register (P01 C) 
is used for control and there is no Write Protection Register for the Program 
EEPROM. 

The Program EEPROM module can only be written to when the TMS370 
device is operating in the Write Protect Override mode (12 volts on the MC 
pin). A read access to the Program EEPROM during a WPO write operation, 
returns the data being programmed. 



6-9 



Program EEPROM Module 



6.2.1 Program EEPROM Control Register (PEECTL) 

The PEECTL register, at address lOICh in the peripheral file, controls pro- 
gramming of the Program EEPROM. The following figure illustrates the bit 
definitions for the PEECTL. 



Program EEPROM Control Register (PEECTL) 
[Memory Address - 101Ch] 



Bit# 



P01C 



7 


6 


5 


4 


3 


2 


1 





BUSY 


— 


— 


— 


— 


AP 


W1W0 


EXE 



R-t 



BitO- 



Bitl- 



Bit2- 



RW-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET (t-see Bit 7 description) 



EXE. Execute. 

Set this bit to initiate the write operation defined by the other control register 

bits. Clear this bit to terminate the operation. 

= Inactive. 

1 = Active. 

W1W0. Writel/WriteO. 

This bit determines whether the Ones or Zeroes programming mode is to be 

used. This bit is write protected when EXE=1. 

= Write zeros. 

1 = Write ones. 

AP. Array Program. 

Set this bit to program the entire array with the value specified by the W1 WO 

bit. With this function, large sections of EEPROM can be altered in a fraction 

of the time necessary to program byte by byte. This bit is write protected when 

EXE=1. 

= Array programming disabled. 

1 = Array programming enabled. 

Bit 3-6 Reserved. Read data is indeterminate. 

Bit 7 - BUSY. 

This bit is set during EEPROM programming to indicate that an operation is in 
progress. Reading any location of the EEPROM during programming returns 
the data being programmed. In order to let the EEPROM voltages stabilize, the 
BUSY bit is set for 1 28 cycles: 

1 ) after a reset, 

2) after an exit from a power-down state, or 

3) after programming the EEPROM. 

If an attempt is made to access the EEPROM during this 128 cycle period, the 
Program EEPROM holds execution of the processor by asserting the WAIT 
signal until 128 cycles complete. 

= EEPROM array is ready for access. 

1 = EEPROM array is not ready for access. 



6-10 



Program EEPROM Module 



6.2.2 Programming the Program EEPROM 

The procedure to program this EEPROM module is similar to the procedure 
described in Section 6.1 .2 with the following differences. 

• The PEECTL register (address P01C in the peripheral file) controls the 
Program EEPROM. 

• There is no write-protection register. The Program EEPROM is write 
protected at all times unless the TMS370 device is in the Write Pro- 
tection Override mode. 

The programming sequence is: 

1 ) External hardware puts 1 2 volts on the MC pin to enter the WPO mode. 

2) Write a data byte to the desired address in the Program EEPROM. 

3) Write the command byte (03h for programming ones or 01 h for pro- 
gramming zeros) to the PEECTL register at address lOICh. 

4) Wait for the programming delay time, tw(PGM)B (see Section 15, 
Device Specifications). 

5) Write OOh to the PEECTL register to clear the EXE bit. 

6) Repeat steps 3 through 6 as necessary to complete the programming. 

7) External hardware returns the MC pin to its normal value (logic 1 for 
microprocessor mode or logic for the microcomputer mode). 

When the AP bit is set, the entire Program EEPROM is programmed to all ones 
or all zeros in a single write sequence. When W1W0=0, all zeros are pro- 
grammed to the entire Program EEPROM. When W1W0 = 1, all ones are pro- 
grammed to the entire Program EEPROM. This function is useful for 
block-erase operations. Issue this command by writing 05h to the PEECTL 
register to set the AP and EXE bits. 

When the TMS370 is in the HALT or STANDBY low-power mode, all oper- 
ations of the Program EEPROM are stopped. All programming operations 
should be completed before entering a HALT or STANDBY state. Any 
EEPROM programming operation, in progress at the time that the halt is 
entered, is aborted. The data at the address being programmed is indetermi- 
nate. 



6-11 



Program EEPROM Module 



6.2.3 Write Protection of Program EEPROM 

The Program EEPROM memory is always write protected unless the device is 
put into the Writ e Prote ct Override (WPO) mode by applying 12 volts to the 
MC pin while the RESET pin is a logic 1 . When the device is in the WPO mode, 
all Program and Data EEPROM memory can be overwritten. 



6-12 



Introductiort 



TMS370 (=amily Deyif^ei 



CPU and Memory diisahizatio^^^^^^ 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module 



Analog-TO'Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



7. Timer 1 Module 



This section discusses the architecture and programming of the Timer 1 mod- 
ule on all TMS370 devices. 

This section covers the following topics: 

Section Page 

7.1 Timer 1 Overview 7-2 

7.1 .1 Introduction 7-2 

7.1.2 Major Components 7-2 

7.1.3 Operating Modes Overview 7-6 

7.2 Timer 1 - 16-Bit, General Purpose Timer 7-7 

7.2.1 General-Purpose-Timer Operating Modes 7-7 

7.2.2 Clock Prescaler/External Clock Source 7-11 

7.2.3 Edge Detection 7-13 

7.2.4 General Purpose Counter 7-14 

7.2.5 Compare Register 7-14 

7.2.6 Capture/Compare Register 7-15 

7.2.7 Interrupts 7-1 5 

7.3 Watchdog Timer 7-17 

7.3.1 Watchdog Counter 7-17 

7.3.2 Power-up RESET 7-1 9 

7.3.3 Reset Frequency 7-20 

7.3.4 Overflow Flag 7-20 

7.4 Low-Power Modes 7-21 

7.4.1 Halt 7-21 

7.4.2 Standby 7-21 

7.5 Control Registers 7-22 

7.5.1 Timer 1 Counter Control Register 1 7-24 

7.5.2 Timer 1 Counter Control Register 2 7-25 

7.5.3 Timer 1 Counter Control Register 3 7-27 

7.5.4 Timer 1 Counter Control Register 4 7-29 

7.5.5 Timer 1 Port Control Registers 7-31 

7.5.5.1 Timer 1 Port Control Register 1 7-31 

7.5.5.2 Timer 1 Port Control Register 2 7-32 

7.5.6 Timer 1 Interrupt Priority Control Register 7-33 



7-1 



Timer 1 Overvie^A/ 



7.1 Timer 1 Overview 



The Timer 1 module of the TMS370 family provides enhanced timer resources 
to perform real-time system control. The Timer 1 Overview contains the fol- 
lowing subsections: 

7.1.1 Introduction: Describes Timer 1 functions and features. 

7.1.2 Major Components: Illustrates Timer 1 system components. 

7.1.3 Operating Modes Overview: Describes operating modes of the 
Timer 1 module. 



7.1.1 Introduction 



This module contains a general-purpose timer (T1) and a Watchdog timer 
(WD). Both T1 and WD allow program selection of input clock sources 
(real-time, external event, or pulse accumulate) with multiple 16-bit registers 
(input capture and compare) for special timer function control. These timers 
provide the capabilities for: 

System Requirements Timer Resource 

Real-Time System Control Interval Timers with Interrupts 

Input Pulse Width Measurement Pulse Accumulate or Input 

Capture Functions 

External Event Synchronization Event Count Function 

Timer Output Control Compare Function 

Pulse-Width Modulated Output PWM Output Function 

Control 

System Integrity Watchdog Function 

FEATURES 

• 16-bit General Purpose Counter 

- 16-bit Compare Register 

- 16-bit Capture/Compare Register 

- External Clock Source / Event Counter / Pulse Accumulator 

- Internal or External Counter Reset 
Programmable Pulse Width Modulated (PWM) Output 

• Selectable Edge Detection Input 

• Programmable Interrupts 

• Three I/O Pins 

• Watchdog Timer 



7-2 



Timer 1 Overvie\A/ 



7.1.2 Major Components 

The Timer 1 Module consists of three major blocks as shown in Figure 7-1 : 

Prescaler/Clock Source, which determines the independent clock sources 
for the general purpose timer and the watchdog timer. 

16-bit General Purpose Counter which provides capture, compare and 
event functions. 

• The capture function latches the counter value on the occurrence of an 
external input. 

• The event function keeps a cumulative total of the transitions on the 
T1 EVT pin. 

• The compare function triggers when the counter matches the contents 
of a compare register. 

16-bit Watchdog Counter which software can reconfigure as a simple 
counter/timer, an event counter, or a pulse accumulator if the watchdog fea- 
ture is not needed. 

The Timer 1 Module contains additional blocks as follows: 

Interrupts 

The module can be programmed to issue interrupts on the occurrence of a: 

• capture, 

• compare equal, 

• counter overflow, or 

• external edge detect. 

I/O Pins 

The Timer 1 Module has three I/O pins which can be dedicated for timer 
functions or as general purpose 1/0 pins. They are: 

• T1 EVT 

• T1IC/CR 

• T1 PWM 

When these pins are dedicated to the timer module, T1 EVT is an input to the 
event counter or the external clock source; T1 IC/CR is an input to the input 
capture, counter reset, or PWM circuit; and T1 PWM is the Pulse Width Mod- 
ulation output. 



7-3 



Timer 1 Overview 



T1 Bn- ^ . 

PIN L->^^ 



T1 IC/CR r-v_ 

pinL-^ 



D 



MUX 



8-BIT 
PRESCALE 



D 



MUX 



EDGE 
DETECT 



ie-BIT 

CAPT/COMP 

REG 



7^ 



16-BIT 
COUNTER 



16 



\y 



16-BIT 

COMPARE 

REG 



16-BIT 

WATCHDOG 

COUNTER 

(AUX. TIMER) 



PWM 
TOGGLE 



INTERRUPT 
LOGIC 



INTERRUPT 
LOGIC 



Figure 7-1. Timer 1 Block Diagram 



Table 7-1. Timer 1 I/O Pin Definitions 



T1 PWM 
PIN 



• pm • 


WM. com Am yoDE 


CAPTtM^COMPARE MODS 


T1IC1/CR 

T1PWM 

T1EVT 


COUNTER RESET INPUT 

PWM OUTPUT 

EXTERNAL EVENT INPUT OR 
PULSE ACCUMULATE INPUT 


INPUT CAPTURE 1 INPUT 

PWM OUTPUT 

EXTERNAL EVENT INPUT OR 
PULSE ACCUMULATE INPUT 



Note: pins may be used as general purpose I/O if not dedicated for timer functions. 



7-4 



Timer 1 Overview 



Control Registers 

Seven addressable control registers govern Timer 1. These registers: 

® select the operating mode, 

© enable interrupts, 

© configure status flags, 

configure the I/O pins, and 

© select the prescaier tap. 

Timer 1 control registers (shown in Table 7-2 and described further in 
Section 7.5) are located at addresses P040 (1040h) to P04F (104Fh) in the 
Peripheral File. The location and name of each register is shown in Table 7-2. 

Table 7-2. Timer 1 and Watchdog Counter Memory Map 



Peripheral 

File 
Location 


Symbol 


Name 


P040 
P041 


T1CNTR 


Counter - MSB 
Counter - LSB 


P042 
P043 


TIC 


Compare Register - MSB 
Compare Register - LSB 


P044 
P045 


T1CC 


Capture/Compare Register - MSB 
Capture/Compare Register - LSB 


P046 
P047 


WDCNTR 


Watchdog Counter - MSB 
Watchdog Counter - LSB 


P048 


WORST 


Watchdog Reset Key 


P049 


T1 CTL1 


Timer 1 Control Register 1 


P04A 


T1 CTL2 


Timer 1 Control Register 2 


P04B 


T1 CTL3 


Timer 1 Control Register 3 


P04C 


T1 CTL4 


Timer 1 Control Register 4 


P04D 


T1PC1 


Timer 1 Pin Control 1 


P04E 


T1PC2 


Timer 1 Pin Control 2 


P04F 


T1PRI 


Timer 1 Priority 



7-5 



Timer 1 Overview 



7.1.3 Operating Modes Overview 

The general-purpose Timer 1 module has two modes of operation: the Dual 
Compare Mode and the Capture/Compare Mode. 

Dual Compare Mode 

The counter is configured to provide two compare registers, external or soft- 
ware reset of the counter, internal or external clock source, and a program- 
mable Pulse Width Modulated (PWM) output. The PWM output may be 
configured to toggle on selected events. 

Capture/Compare Mode 

The counter is configured to provide one input capture register and one com- 
pare register for use with the general purpose timer. The compare register may 
be used to provide periodic interrupts to the TMS370 CPU. The capture reg- 
ister may be configured to capture the current counter value upon either edge 
of an external input. 



7-6 



Timer 1 - 16-Bit, General Purpose Timer 



7.2 Timer 1 - 16-Bit, General Purpose Timer 

This section describes the elements of the 1 6-bit General Purpose Tinner (T1 ). 
The function of each block within T1 is discussed in general and for each 
mode of operation. Section 7.2 contains the following subsections: 

7.2.1 General-Purpose Timer Operating Modes: Explains theory of oper- 
ating modes. 

7.2.2 Clock Prescaler/Externa! Clock Source: Illustrates operation of the 
Prescaler and clock source selection circuitry. 

7.2.3 Edge Detection: Explains operation of the External Edge Detection 
circuitry for both operating modes. 

7.2.4 General Purpose Counter: Explains operation of the free running 
Timer 1 up counter. 

7.2.5 Compare Register: Explains operation of the 16-bit Compare regis- 
ter. 

7.2.6 Capture/Compare Register. Explains operation of the Capture/ 
Compare register during both operating modes. 

7.2.7 Interrupts: Explains interrupting capability for both operating 
modes. 

7.2.1 General-Purpose-Timer Operating Modes 

The General Purpose Timer operation mode determines whether the 
Capture/Compare register functions as a capture register in the Capture/ 
Compare mode or as a compare register in the Dual Compare mode. The T1 
MODE bit (T1CTL4.7) selects the mode as follows: 

T1 MODE = - Dual Compare Mode 
T1 MODE = 1 - Capture/Compare Mode 

Dual Compare Mode 

The Dual Compare Mode provides two compare registers, an external- 
resettable counter, and a timer output pin. These allow the timer to act as as 
interval timer, a PWM output, simple output toggle, or many other timer 
functions. 

The Dual Compare mode as shown in Figure A-3 continuously compares the 
contents of the two compare registers to the current value of the 16-bit 
counter. If a timer compare register equals the counter, the circuit sets the 
associated interrupt flag to 1 and toggles the T1 PWM output pin if enabled, 
and/or generates a Timer 1 interrupt. 

A compare-equal condition from compare register 1 can also initiate a counter 
reset. A programmable-interval timer function (selected by using the compare 
equal condition to generate a system interrupt combined with the counter 
reset function) generates a periodic interrupt. 



7-7 



Timer 1 - 16-Bit, General Purpose Timer 



Either compare function may be used to toggle the T1 PWM output pin when 
a compare-equal condition occurs, while the other compare function may be 
used for another system timing function. Using both compare functions to 
control the T1 PWM pin allows direct PWM generation with minimal CPU 
software overhead. 

In typical PWM applications, the compare register is loaded with the periodic 
interval and configured to allow counter reset on a compare-equal condition, 
and the Capture/Compare register is loaded with the pulse width to be gen- 
erated within that interval. The program pulse width may be changed by the 
application program during the timer operation to alter the PWM output. For 
high-speed control applications, a minimum pulse width of 200 ns and a 
period as low as 400 ns can be maintained when using a clock of 20 MHz. 

In addition, the PWM output can be used to support time-critical control 
applications. Typically, in these applications an external input (T1IC/CR) is 
used to: 

1 ) reset the counter, 

2) generate a timer interrupt, and 

3) toggle the T1 PWM pin to start the PWM output. 

The compare function then toggles the output after the programmed pulse 
width has elapsed. 

The input edge detect function is enabled under program control by the T1 CR 
DET ENA bit, and upon the next occurrence of the selected edge transition: 

1) the T1 EDGE INT FLAG bit is set, 

2) a timer interrupt is generated (if T1 EDGE INT ENA =1 ), and 

3) the T1 PWM output pin is toggled (if T1 CR OUT ENA = 1 ). 

The T1EDGE POLARTIY bit selects the active input transition. In the Dual 
Compare mode, the edge detect function must be re-enabled after each valid 
edge detect. 

The clock input to the counter is either the internal system clock, with or 
without prescale, or the external clock (T1EVT). The clock pulse to the 
counter is always synchronized with the system clock. 

The counter is free-running except when it receives a reset pulse from one of 
the following sources: 

1 ) a 1 written to the T1 SW RESET (T1 CTL2.0) bit, 

2) a compare equal condition from the dedicated T1 compare function, 

3) system RESET, or 

4) an external pulse on the T1 IC/CR pin (Dual Compare mode). 

The counter rolls over to OOOOh if not reset prior to a count of FFFFh. When 
this rollover occurs, the counter sets the T1 OVRFL INT FLAG (T1 CTL2.3) 
and generates an interrupt (if T1 OVRFL INT ENA {T1CTL2.4} is set), and 
continues counting. 



7-8 



Timer 1 - 16-Bit, General Purpose Timer 



PRESCALE 
CLOCK 
SOURCE 



16-BIT LSB 

CAPT/COMP 

REG MSB 



S^ 



COMPARE 



7^ 



LSB 16-BIT 
MSB COUNTER 



RESET 



6 



T1 S/W 
RESET-J 
4A.0 



T1C1 
RST ENA 

4C.1>v^ 



T1CR 
RST ENA 



16 



COMPARE 2 



4B.1 



FLAG 



4B.6 



T1C2 



INT ENA 



I COMPARE ="] - 



COMPARE 1 



4B.0 



FLAG 



4B.5 



T1C1 



INT ENA 



16-BIT LSB 

COMPARE 

REG ^^SB 



T1 

IC/CR O 
PIN 



EDGE 
SELECT 



T1 EDGE DET 
ENA 



T1 OVRFL 
INT 



4A.4 



FLAG 



-o/o- 



4A.3 



T1 OVRFL 
INT ENA 



T1 EDGE 
'POLARITY 4C.2 



T1 EDGE 
INT 



4B.2 



FLAG 



■^c 



4B.7 



T1EDGE 



INT ENA 



OUTPUT 
ENABLE 



iCA,,/^ 



T1C2 
OUT ENA 
4C.6 



-cy^ 



T1C1 
OUT ENA 



4C.3 



o^o- 



T1CR 
OUT ENA 



T1 PWM 
PIN 



4F.6 



o^ 



LEVEL 1 INT 



LEVEL 2 INT 



Figure 7-2. Dual Compare Mode 



7-9 



Timer 1 - 16-Bit, General Purpose Timer 



Capture/Compare Mode 

In the Capture/Compare mode (T1 MODE = 1), Timer 1 provides one input 
capture register for external timing and pulse-width measurement, and one 
compare register for use as a programmable interval timer. In this mode, the 
compare register functions the same as in the Dual Compare mode described 
previously, including the ability to toggle the PWM pin. The capture/compare 
register functions in this mode as a 16-bit input capture register, as shown in 
Figure A-5. On the occurrence of a valid input on the T1 IC/CR pin: 

1 ) the current counter value is loaded into the 1 6-bit input capture register, 

2) the T1 EDGE INT FLAG is set, and 

3) a timer interrupt is generated (if T1 EDGE INT ENA = 1 ). 

The input detect function is enabled by the T1EDGE DET ENA bit, with 
T1EDGE POLARITY selecting the active input transition. In the 
Capture/Compare mode, the edge detect function, once enabled, remains 
enabled following a valid edge detect. 



CLOCK 
PRESCALER 



16-BIT LSB 

CAPT/COMP 

REG MSB 



7?^ 



LSB 16-BIT 
MSB COUNTER 



RESET 



C) 




45 
44 



•ST- 



COMPARE 



16-BIT LSB 

COMPARE 

REG MSB 



T1 ,_^ 
IC/CR L> 
PIN 



EDGE 
SELECT 



EDGE DETECT 
ENA 

^o 



COMPARE 



I FLAG 



4B.5 



O VERFLO W 
— I FLAG I — 

4A.3 



4C.0 
-EDGE POLARITY 4C.2 



E XT EDG E 
— I FLAG h - 
4B.7 



48. 
INT ENA 



4A.4 
— cy'o — 

INT ENA 



4B.2 

— <y/o— 
INT ENA 




4F.6 



<^ 



LEVEL 1 INT 



LEVEL 2 INT 



Figure 7-3. Capture/Compare Mode 



7-10 



Time 



r 1 - 16-Bit, General Purpose Timer 



7.2.2 Clock Prescaler/External Clock Source 

This block, as illustrated in Figure A-4, allows selection of the clock inputs to 
the General Purpose Counter and the Watchdog Counter independently. Each 
counter has three bits in the T1CTL1 Register (see Section 7.5.1) which 
determine whether the counter is clocked by one of the prescaled system clock 
values or the external clock source (T1 EVT). 

The counter clock sources are as follows: 

system clock with no prescale. 

no clock, in which the counter is stopped. 

external source synchronized with the system clock (event counter 
operation). 

system clock while the external input is high (pulse accumulation), 
one of four taps from the prescaler which provide a system clock divided 
by 4, 1 6, 64, or 256. 

The external clock input to the module (T1 EVT) must not exceed CLKIN/8. 
If the application does not require the external clock, the T1 EVT pin may be 
reconfigured as a digital I/O pin. 



EVENT 



FREQUENCY 
(CU<!N) 



T1 EVT_ 
PIN 




Figure 7-4. Timer 1 System Clock Prescaler 



7-11 



Timer 1 - 16-Bit, General Purpose Timer 



The event input is not routed through the prescaler; thus the Timer 1 module 
can use different taps of the prescaler for Timer 1 and the Watchdog Timer. 

The maximum counter duration using the internal clock is determined by the 
internal system clock time (SYSCLK) and the prescale tap (T). These 
relationships are shown below: 

Maximum Counter Duration (seconds) = 2'' ^ * PS * SYSCLK 

Counter Resolution = PS * SYSCLK 

where: SYSCLK = 4 / CLKIN 

PS = 1 for no prescale 

= 4 for divide by 4 

= 16 for divide by 16 

= 64 for divide by 64 

= 256 for divide by 256 

Table 7-3 gives the real-time counter overflow rates for various crystal and 
prescaler values. 

Software can also configure the overflow rates for the Watchdog Counter as 
shown in Table 7-3 or the value shown divided by two if the WD OVRFL TAP 
SEL bit (T1CTL1.7) is set (see Section 7.3). This bit effectively sets the 
Watchdog Counter as either a 15-bit counter when set or a 16-bit counter 
when cleared. 



Table 7-3. Counter Overflow Rates 













CRYSTAL OSCILLATOR 














FREQUENCY (MHz) 






2.0 


4.0 


10 


20 


Select 


Select 


Select 


Divide 




System Clock Period (ns) 




2 


1 





BY 


2000 


1000 400 


200 











2l6 


0.131t 


0.066 


0.026 


0.013 








1 


(P.A.) 


t 


t 


t 


t 





1 





(Event) 


t 


t 


t 


t 





1 


1 


<|VJ" 


t 


t 


t 


t 


1 








0.524 


0.262 


0.105 


0.052 


1 





1 


220 


2.10 


1.05 


0.419 


0.210 


1 


1 





222 


8.39 


4.19 


1.68 


0.839 


1 


1 


1 


224 


33.6 


16.8 


6.71 


3.355 



tJime is given in seconds. 
l^Not applicable. 



The event counter input senses a low-to-high transition on the T1 EVT pin 
while in the event-counter mode, and senses a high level (true) on the pin 
while in the pulse-accumulator mode. 

The pulse accumulator mode keeps a cumulative count of SYSCLK pulses 
gated by the T1 EVT signal as shown in Figure 7-5 



7-12 



Timer 1 - 16-Bit, General Purpose Timer 



T1EVT 



SYSCLK 



COUNTER 
VALUE 




Figure 7-5. Pulse Accumulation 



7.2.3 Edge Detection 



The edge detection circuitry senses an active pulse transition on the Timer 1 
Input-Capture/Counter-Reset pin (T1IC/CR), and provides appropriate out- 
put transitions to the rest of the module. The T1EDGE POLARITY bit 
(T1CTL4.2) determines whether the active transition is low-to-high or high- 
to-low. The module sets the T1 EDGE INT FLAG (T1 CTL3.7) when an active 
transition is detected. The program must reset this flag. 

Dual Compare Mode 

In this mode, the program must set the T1 EDGE DET ENA bit (T1 CTL4.0) to 
re-enable the circuit after each edge detection. Writing a one to this bit, ena- 
bles the detect circuit to look for the next correct level transition. After this 
active transition occurs, the T1 EDGE DET ENA bit (T1 CTL4.0) is cleared. 

When the Edge Detection circuit is enabled and detects the appropriate edge 
transition, the T1 EDGE INT FLAG bit (T1 CTL3.7) is set. 

When the T1 CR RST ENA bit (T1 CTL4.1 ) is set, the T1 EDGE INT FLAG resets 
the counter. If the T1 CR OUT ENA bit (T1 CTL4.3) is set, the T1 EDGE INT 
FLAG toggles the T1 PWM output latch. 

The T1 EDGE POLARITY bit (T1CTL4.2) determines which edge polarity (ris- 
ing or falling) is detected. 



7-13 



Timer 1 - 16-Bit, General Purpose Timer 



Capture/Compare Mode 

When the appropriate (rising or falling) transition is detected, the Edge 
Detection circuit signals the capture register to load the current counter value 
if the T1 EDGE DET ENA bit is set. The T1 EDGE POLARITY bit (T1 CTL4.2) 
determines which edge of the signal on the T1 EVT pin to detect. 

The input detect function is enabled by the T1EDGE DET ENA bit, with 
T1EDGE POLARITY selecting the active input transition. In the 
Capture/Compare mode, the edge detect function, once enabled, remains 
enabled following a valid edge detect. 



7.2.4 General Purpose Counter 



The counter is a free-running, 1 6-bit up-counter, clocked by the output of the 
Prescaler/Clock source. During initialization, the counter is loaded with OOOOh 
and begins its up-count. If the counter is not reset before reaching FFFFh, the 
counter rolls over to OOOOh and continues counting. Upon counter roll-over, 
the T1 OVRFL INT FLAG (T1 CTL2.3) is set, and a timer interrupt is generated 
if the T1 OVERFL INT ENA (T1 CTL2.4) bit is set (see note, page 7-22). 

The counter may be reset to OOOOh during counting by either: 

1 ) a 1 written to the T1 SW RESET (T1 CTL2.0) bit, 

2) a compare equal condition from the dedicated T1 compare function, 

3) system RESET, or 

4) an external pulse on the T1 IC/CR pin (Dual Compare mode). 

The designer may select through software (T1EDGE POLARITY bit) which 
external transition on the T1 IC/CR pin, low-to-high or high-to-low, will reset 
the counter. 



7.2.5 Compare Register 



The Compare Register circuit consists of a 16-bit wide, read/write data regis- 
ter and logic to compare the counter's current value with the value stored in 
the compare register. The program can access the 16-bit compare register at 
P042 (Compare Register MSB) and P043 (Compare Register LSB) in the 
Peripheral File frame (see note, 7-22). 

When the counter's value matches the compare register value, the following 
events occur: 

1 ) the T1 CI INT FLAG bit (T1 CTL3.5) is set, 

2) the compare register generates a counter reset signal if the T1C1 RST 
ENA bit (T1 CTL4.4) is set, 

3) the output latch to T1 PWM toggles if CMP 1 is enabled, and 

4) an interrupt is generated if enabled (T1C1 INT ENA). 

The Compare Register is initialized to OOOOh following RESET. 



7-14 



Timer 1 - 16-Bit, General Purpose Timer 



Note: 

If the counter is programmed to reset when its value equals the content 
of the compare register, the reset occurs on the following counter clock 
cycle (after prescale). However, the compare flag is set and the interrupt 
event occurs during the clock cycle that incremented the counter to the 
compare equal value. Thus, there could be a delay of up to 256 system 
clock cycles (depending on the prescale tap in use) from the time the 
event is recognized by the program until the counter actually resets to 
zero. If the program writes to the compare register during this interval, the 
counter may not be reset on the following counter clock. 



7.2.6 Capture/Compare Register 



The Capture/Compare register for Timer 1 is a 16-bit wide register which can 
serve one of two functions depending on the operating mode. The 
Capture/Compare register is located at address P044 (Capture/Compare reg- 
ister MSB) and P045 (Capture/Compare register LSB) in the Peripheral File 
(see note, 7-22). 

Dual Compare Mode 

In the Dual Compare mode, the 16-bit Capture/Compare Register acts as a 
compare register. This compare register functions exactly as the one described 
in Section 7.2.5 except that it cannot reset the counter. When an output 
compare equal occurs, the T1 C2 INT FLAG bit (T1 CTL3.6) is set. 

In the Dual Compare mode, the Capture/Compare register is a read/write 
register. Compare logic generates a pulse when the the counter value matches 
the Capture/Compare Register value. This pulse: 

1 ) sets the T1 C2 INT FLAG bit (T1 CTL3.6), 

2) clocks the output latch to T1 PWM if the T1 C2 OUT ENA bit (T1 CTL4.5) 
is enabled, and 

3) generates an interrupt (T1 C2) if T1 C2 INT ENA (T1 CTL3.1 ) is enabled. 

Capture/Compare Mode 

In this mode, the edge detection signal captures the current counter content, 
loads it into the 16-bit Capture/Compare register, and sets the T1EDGE INT 
FLAG bit (T1CTL3.7). 



7-15 



Timer 1 - 16-Blt, General Purpose Timer 



7.2.7 Interrupts 



Dual Compare 

In dual compare mode, four separate events can generate an interrupt. These 
interrupts are: 

1) compare equal from Compare Register 1 if the T1 CI INT EN A bit 
(T1 CTL3.0) is set, 

2) compare equal from Compare Register 2 if the T1 C2 INT ENA bit 
(T1 CTL3.1 ) is set, 

3) counter overflow if the T1 OVRFL INT ENA bit (T1 CTL2.4) is set, or 

4) edge detect is set if the T1 EDGE INT ENA bit (T1 CTL3.2) is set. 

Capture/Compare 

In the Capture/Compare mode, three separate events can generate an inter- 
rupt. These interrupts are: 

1 ) output compare equal if the T1 CI INT ENA bit (T1 CTL3.0) is set, 

2) counter overflow if the T1 OVRFL INT ENA bit (T1 CTL2.4) is set, and 

3) input capture acknowledge if the T1EDGE INT ENA (T1CTL3.2) bit is 
set. 



Note: 

All set and enabled interrupt flags must be cleared before exiting the T1 
interrupt routine. If the flags are not reset then the processor will enter the 
T1 interrupt routine again before continuing with the mainstream program. 
If the bit flag bits are never reset then the program will lock up. 



7-16 



Watchdog Timer 



7.3 Watchdog Timer 

The Watchdog Timer, shown in Figure A-6, consists of the following blocks: 

• 16-bit, Watchdog/Event Counter which provides up to 2^^ clock cycles 
between counter resets depending on the prescaler tap used. The pro- 
gram can read the contents of this counter at locations P046 (MSB) and 
P047 (LSB) in the Peripheral File. 

• Prescaled clock input selection or external clock, the same as the General 
Purpose Timer. 

• Watchdog Reset key which provides protection against illegal resets. 

• An Overflow flag which the program may read following RESET to 
determine if the Watchdog caused the reset. 

• Programmable interrupt and system RESET. 



46 
47 



CLOCK 
PRESCALER 



16-BIT 
"WATCHDOG COUNTER" 



n 



48 



RESET 



WATCHDOG 

OVERFLOW 

FLAG 



4A.5 



WD OVRFL 
TAP SEL 



WATCHDOG RESET KEY 



4A.7 

-Cr^O- 



WD OVRFL 
RST ENA 




SYSTEM 
RESET 



INTERRUPT 



Figure 7-6. Watchdog Timer 



7.3.1 Watchdog Counter 



The watchdog timer is a free-running 16-bit resettable up-counter clocked by 
the output of the Prescaler/Clock source. The timer is software configured as 
either a watchdog timer to protect against system software failures and cor- 
ruption, or as a simple counter/timer if the watchdog function is not desired. 
The 16-bit up-counter is programmable (with the WD OVRFL TAP SEL bit) 
to set the initial count at either OOOOh or 8000h. The current value of the 
watchdog timer may be read at anytime during its operation (see note, page 
7-22). 

Watchdog Mode 

In the Watchdog mode (WD OVRFL RST ENA - 1 ), the WD timer generates 
a system reset if the counter overflows or if the WD timer is reinitialized by an 
incorrect value. The required re-initialization frequency is determined by the 
system clock frequency, the prescaler/clock source selected, and whether the 
WD OVRFL TAP SEL bit is set for 1 5 or 1 6 bit counter rollover. 

With a 20 MHz clock, the watchdog-timer overflow rates range from 6.55 ms 
to 3.35 seconds. These values are selected prior to entering the watchdog 



7-17 



Watchdog Timer 



mode because once the software enables the watchdog reset function 
(WD OVRFL RST ENA = 1), subsequent writes to these control bits are 
ignored. Writes to these watchdog control bits can occur only following a 
powerup reset, which enhances watchdog-timer system integrity. 

The watchdog timer is re-initialized by writing a predefined value to the 
watchdog reset key (WORST) located in the peripheral file at P048. The 
correct reset key alternates between 55h and AAh, beginning with 55h fol- 
lowing the enable of the watchdog reset function. Writes of the correct value 
must occur prior to the timer overflow period. 

A write of any value other than the correct predefined value to the watchdog 
reset key is interpreted as a lost program and a system reset is initiated. A 
watchdog-timer overflow or incorrect reset key sets the WD OVRFL INT FLAG 
bit to 1 and may be interrogated by the program following system reset to 
determine the source of the reset. 

Non-Watchdog Mode 

In the Non-Watchdog mode (WD OVRFL RST ENA = 0), the watchdog timer 
may be used as an event counter, pulse accumulator, or as an interval timer. 
In this mode, the system reset function is disabled. The watchdog timer may 
be re-initialized by writing any value to the watchdog reset key (WDRST). In 
real-time control applications, the timer overflow rates are determined by the 
system clock frequency, the prescaler/clock source value selected, and the 
value of the WD OVRFL TAP SEL bit. If the WD counter is not reset before 
overflowing , the counter rolls over to either OOOOh or 8000h, as determined 
by the WD OVERFL TAP SEL bit, and continues counting. Upon counter 
overflow, the WD OVRFL INT FLAG is set and a timer interrupt is generated 
if the WD OVRFL INT ENA bit set. Alternatively, an external input on the 
T1 EVT pin may be used with the watchdog timer to provide an additional 
1 6-bit event counter or pulse accumulator. 



7-18 



Watchdog Timer 



7.3.2 Power-up RESET 

After a system power-up RESET, the Watchdog Counter resets to the non- 
watchdog mode configured as a simple up-counter with the system clock (no 
prescale) as its input. Thus, if the watchdog mode is used, the program must 
explicitly enable it (by setting WD OVRFL RST ENA). The Watchdog Counter 
resets to OOOOh when the WD OVRFL RST ENA bit (T1 CTL2.7) is set. 

Example 7-1. Watchdog Initialization Example 

The following routine initializes the Watchdog Timer to generate a system 
reset when the counter overflows. The Watchdog counter is set to 16 bits in 
length and the full 8-bit prescale tap is used. 



;Set up Watchdog Timer for a 24-bit countdown time. 

OR #70h,P049 ;Set the Watchdog Overflow Tap to 16 bits 
and select the /256 prescale value 

OR #C0h,P049 ; Watchdog Timer Reset is enabled along 
with clearing and enabling the 
Watchdog Timer interrupt. 



The Watchdog Timer has now been initialized to cause a 
system RESET if the counter is not reset before reaching 
FFFFh. To reset the counter, the code must write an 
alternating 55h and AAh, starting with 55h, to the 
Watchdog Timer Reset Key register (P048) , e.g.: 



MOV #55h,P048 ;First write to WD RESET KEY 
MOV #0AAh,P048 ;Next write to WD RESET KEY 
MOV #55h,P048 ;Next write to WD RESET KEY 



7-19 



Watchdog Timer 



7.3.3 Reset Frequency 



When the Watchdog timer overflows, it pulls the RESET line low to cause a 
system reset and sets the WD OVRFL INT FLAG bit (T1 CTL2.5). The required 
reset frequency of the watchdog timer is determined by the value of the clock 
prescaler selected to clock the Watchdog Counter and by the choice of 
whether the overflow tap is set for a 1 5 or 1 6 bit counter. The program must 
set these choices before entering the watchdog mode. 

The overflow tap is selected by the WD OVRFL TAP SEL bit (T1CTL1.7). 
When WD OVRFL TAP SEL is cleared, the Watchdog Counter is a full 16 bit 
counter. When WD OVRFL TAP SEL is set, the most-significant bit remains 
set, the Counter behaves as a 15-bit counter, and overflow occurs twice as 
often as in the 16-bit configuration. 

The watchdog overflow rates are the same as given In Table 7-3, page 7-12 
when configured as a 16-bit counter (WD OVRF TAP SEL = 0). Divide the 
rates in Table 7-3 in half when the timer is configured as a 15-bit counter 
(WD OVRFL TAP SEL = 1). 



7.3.4 Overflow Flag 



Watchdog Mode When the Watchdog Counter initiates a RESET, it sets the 
WD OVRFL INT FLAG bit (T1CTL2.5). The program may read this flag after 
a RESET to determine the source of the RESET. The program must clear this 
flag by writing a zero to the WD OVRFL INT FLAG bit. 

Non-Watchdog Mode Upon overflow, the module sets the WD OVRFL INT 
FLAG bit (T1CTL2.5). This causes an interrupt if the WD OVRFL INT ENA 
bit (T1 CTL2.6) is set. 



7-20 



Low-Po\A/er Modes 



7.4 Low-Power Modes 



7.4.1 Halt 



The Timer 1 module supports extended operating states which aid in reducing 
power consumption during periods of inactivity. These two states are the Halt 
and the Standby modes. For more information on Powerdown modes, see 
Section 4.1 .4, page 4-4. 



The Halt Mode is entered when the CPU executes an IDLE instruction while 
the Halt/Standby bit (SCCR2.7) and the Powerdown/IDLE bits (SCCR2.6) 
are set. During the Halt Mode, the Timer 1 Module clears the interrupt enable 
bits, but holds the pre- Halt status of all other storage elements. 

The module holds the state of the each external pin constant regardless of 
whether the pins are used as general purpose port pins or as dedicated I/O 
pins. That is, inputs remain inputs, output low levels remain low, and output 
high levels remain high. 

When the Halt state terminates, the Timer 1 Module continues where it left 
off. 



7.4.2 Standby 



Standby Mode is entered by the CPU executing a IDLE instruction when the 
Powerdown/ldle (SCCR2.6) bit is set and the Halt/Standby bit (SCCR2.7) 
is cleared. During the Standby Mode, the Watchdog Counter clock input is 
halted while the rest of the Timer 1 Module remains fully functional. 



7-21 



Control Registers 



7.5 Control Registers 



Seven registers control the configuration of Timer 1 global functions, prescale 
values, watchdog timing, optional uses for the associated I/O pins, and other 
counter functions. The bits shown in shaded boxes in Figure 7-7 are Privilege 
Mode bits, that is, they can only be written to in the Privilege Mode. 



Note: 

Special circuitry prevents 16-bit registers from changing in the middle of 
a 16-bit read or write operation. When reading a 16-bit register, read the 
least-significant byte (LSB) first to lock in the value and then read the 
most-significant byte (MSB). When writing to a 1 6-bit register, write the 
MSB first and then write the LSB. The register value does not change 
between reading or writing the bytes when done in this order. While 
accessing a 16-bit register, do not read or write from a second 16-bit 
register within this module and expect a correct value for the first register's 
MSB. The 1 6-bit read/write operation actually occurs when accessing the 
LSB. 

Read: LSB then MSB 
Write: MSB then LSB 



7-22 



Control Registers 



PERIPHERAL FILE FRAME 4: TIMER 1 CONTROL REGISTERS 



ADDR 
1040h 
1041h 
1042h 
1043h 
1044h 
1045h 
1046h 
1047h 
1048h 



PF 
040 
041 
042 
043 
044 
045 
046 
047 
048 



1049h 049 



104Ah 04A 



BIT 7 


BIT 6 


BIT 5 


BIT 4 


BIT 3 


BIT 2 


BIT1 


BITO 


BIT 15 COUNTER MSB BIT 8 


BIT 7 COUNTER LSB BIT 


BIT 15 COMPARE REGISTER MSB BIT 8 


BIT 7 COMPARE REGISTER LSB BIT 


BIT 15 CAPTURE/COMPARE REGISTER MSB BIT 8 


BIT 7 CAPTURE/COMPARE REGISTER LSB BIT 


BIT 15 WATCHDOG COUNTER MSB BIT 8 


BIT 7 WATCHDOG COUNTER LSB BIT 


WATCHDOG RESET KEY 


WD OVRFL 
TAP SEL 


'iSfiifil-' 


sELigii:: 


WD INPUT 
SELECT 





T1 INPUT 
SELECT 2 


T1 INPUT 
SELECT 1 


T1 INPUT 
SFI FCT 


WD OVRFL 
RST ENA 


WD OVRFL 
INT ENA 


WD OVRFL 
INT FLAG 


T1 OVRFL 
INT ENA 


T1 OVRFL 
INT FLAG 


— 





T1 
SW RESET 



MODE: DUAL COMPARE REGISTERS WITH EVENT COUNTER 



104Bh 04B 



104Ch 04C 



T1EDGE 
INT FLAG 


T1C2 
INT FLAG 


T1C1 
INT FLAG 


— 


— 


T1EDGE 
INT ENA 


T1C2 
INT ENA 


T1C1 
INT ENA 


T1M0DE 
= 


T1C1 
OUT ENA 


T1C2 
OUT ENA 


T1C1 
RST ENA 


T1CR 
OUT ENA 


T1EDGE 
POLARITY 


T1CR 
RST ENA 


T1EDGE 
DET ENA 



MODE: SINGLE CAPTURE AND COMPARE REGISTERS 



104Bh 04B 



104Ch 04C 



104Dh 04D 



104Eh 04E 



104Fh 04F 



T1EDGE 
INT FLAG 





T1C1 
INT FLAG 








T1EDGE 
INT ENA 





T1C1 
INT ENA 


T1M0DE 
= 1 


T1C1 
OUT ENA 


— 


T1C1 
RST ENA 





T1EDGE 
POLARITY 





T1EDGE 
DET ENA 






— 


— 





T1EVT 
DATA IN 


T1EVT 
DATA OUT 


T1EVT 
FUNCTION 


T1EVT 
DATA DIR 


T1PWM 
DATA IN 


T1PWM 
DATA OUT 


T1PWM 
FUNCTION 


T1PWM 
DATA DIR 


T1IC/CR 
DATA IN 


T1IC/CR 
DATA OUT 


T1IC/CR 
FUNCTION 


T1IC/CR 
DATA DIR 


lillili 

liiiiii 


T1 
PRIORITY 





— 











— 



T1CNTR 

TIC 

T1CC 

WDCNTR 

WORST 

T1CTL1 

T1CTL2 

T1CTL3 
T1CTL4 

T1CTL3 
T1CTL4 

T1PC1 
T1PC2 
T1PRI 



Figure 7-7. Peripheral File Frame 4 - Timer 1 Control Registers 



7-23 



Control Registers 



7.5.1 Timer 1 Counter Control Register 1 

The T1 CTL1 Register controls the prescaler inputs to the Watchdog counter 
and the general purpose counter. The bit assignments and definitions follow: 

Timer 1 Control Register 1 (T1CTL1) 
[IVIemory address - 1049h] 

Bit # • 
P04g 

_T 

RP-0 RP-0 RP-0 RP-0 RW-0 

R=Read, W=Write, P=Write Protected when WD OVRFL RST ENA=1, 



7 


6 


5 


4 


3 


2 


1 





WD 

OVRFL 

TAP SEL 


WD 

INPUT 

SELECT 2 


WD 

INPUT 

SELECT 1 


WD 

INPUT 

SELECT 


— 


T1 

INPUT 

SELECT 2 


T1 

INPUT 

SELECT 1 


T1 

INPUT 

SELECT 



RW-0 RW-0 

-n=Value after RESET 



Bits 0-2 - T1 INPUT SELECT 0-2. Timer 1 Input Select 0-2. 

These three bits select one of eight possible clock sources for the Timer 1 
general purpose counter. These sources are: 

the system clock with no prescale (system clock) 
- the system clock when the external input T1 EVT is high (pulse 
accumulation) 

an external source synchronized with the system clock (event input) 
no system clock source (no clock input) 

one of four taps from the 8-bit prescaler which provides the system clock 
divided by either 4, 16, 64, or 256 

The combinations are shown below. 



Bits - 
Bits 4-6 



Bit 7 - 



2 


1 





Counter Clock Source 












1 


system clock 
pulse accumulation 





1 
1 
1 
1 


1 
1 




1 
1 




1 



1 



1 


event input 
no clock input 
system clock / 4 
" /16 
" / 64 
" / 256 



Reserved. Read data is indeterminate. 

WD INPUT SELECT 0-2. Watchdog Input Select 0-2. 

These three bits select one of eight possible clock sources for the Watchdog 
counter. These sources and the bit combinations to select the sources are the 
same as listed above for the General Purpose Counter. Once the WD OVRFL 
RST ENA bit is set, the values of these bits can only be changed after a 
Power-Up RESET. 

WD OVRFL TAP SEL. Watchdog Overflow Tap Select. 
This bit determines whether the Watchdog Counter is to operate as a 15 bit or 
a 16 bit counter. The default is the full 16 bits of the counter. If a shorter 
Watchdog Counter overflow rate is desired, the most significant bit of the 
counter can be forced to remain at a 1. This, in effect, changes the Watchdog 
Counter to a 15-bit counter with an overflow period 1/2 that of a 16 bit 
counter. This tap select feature, combined with the clock prescaler, allows 
Watchdog overflow rates from 2^^ to 2^4 system clock cycles. This bit is 
cleared by a) a Power-Up RESET, or b) any RESET while WD OVRFL RST 
ENA=0 (Non-Watchdog Mode). 

= 16-bit Watchdog Counter overflow. 

1 = 15-bit Watchdog Counter overflow. 



7-24 



Control Registers 



7.5.2 Timer 1 Counter Control Register 2 

The T1 CTL2 register controls the Timer 1 and Watchdog overflow interrupts, 
and contains the Timer 1 software reset bit. A summary of the bit assignments 
and definitions is shown below. 



Bit# 



P04A 



Timer 1 Counter Control Register 2 (T1CTL2) 
[Memory Address - 104Ah] 



7 


6 


5 


4 


3 


2 


1 





WD 

OVRFL 

RST ENA 


WD 
OVERFL 
INT ENA 


WD 
OVERFL 
INT FLAG 


T1 
OVRFL 
INT ENA 


T1 

OVRFL 

INT FLAG 


— 


— 


T1 

SW 

RESET 



RS-0 



RW-0 



RC-t 



RW-0 



RC-0 



S-0 



R = Read, S=Set Only, W=Write, C=Clear Only, 
t-see bit 5 description 



-n=Value after RESET, 



Bit - T1 SW RESET. Timer 1 Software Reset. 

This bit is always read as a zero; however, when a one is written to this bit, the 
counter resets to OOOOh on the next system clock cycle. 



This bit is cleared 



Bit 1,2 - Reserved. Read values are indeterminate. 

Bit 3 - T1 OVRFL INT FLAG. Timer 1 Overflow Interrupt Flag 

This bit indicates the status of the T1 Overflow Interrupt, 
by RESET or by writing a zero to it. 

= General Purpose Overflow interrupt inactive. 

1 = General Purpose Overflow interrupt pending. 

Bit 4 - T1 OVRFL IIMT ENA. Timer 1 Overflow Interrupt Enable. 

This bit controls the Timer 1 Overflow interrupting capability. 

= Disable Interrupt. 

1 = Enable Interrupt. 

Bit 5 - WD OVRFL INT FLAG. Watchdog Overflow Interrupt Flag. 

This bit indicates the status of the Watchdog overflow interrupt. Clear this bit 
by writing a zero to it. This bit is NOT cleared following a Watchdog initiated 
RESET. Thus it may be read and cleared, to determine the cause of the RESET. 
This bit is cleared by power-up RESET or by any reset if WD OVRFL RST 
ENA = 0. Once the WD OVRFL RST ENA bit is set, the values of these bits 
can only be changed after a Power- Up RESET. 

= Watchdog Interrupt Inactive 

1 = Watchdog Counter has overflowed or the incorrect value is written to the 

Watchdog Reset Key register while in Watchdog mode. 

Bit 6 - WD OVRFL INT ENA. Watchdog Overflow Interrupt Enable. 

This bit controls the Watchdog Overflow interrupting capability. Once the WD 
OVRFL RST ENA bit is set, the values of these bits can only be changed after 
a Power-Up RESET. 

= Watchdog Interrupt Disabled. 

1 = Watchdog Interrupt Enabled. 



7-25 



Control Registers 



Bit 7 - WD OVRFL RST ENA Watchdog Overflow Reset Enable. 

This bit controls the ability of a Watchdog overflow to generate a RESET. When 
set, this bit determines the function of the Watchdog Counter; either as a the 
Watchdog Counter, or as a simple up counter or event counter/pulse accu- 
mulator. Once set, this bit can only be cleared by a Power-Up RESET, and 
locks the values of other WD bits so they can only be changed during 
Power-up RESET. 

= Watchdog Counter does not initiate a RESET upon overflow. 

1 = Watchdog Counter does initiate a RESET upon overflow. 



7-26 



Control Registers 



7.5.3 Timer 1 Counter Control Register 3 

The T1 CTL3 register controls the edge-detect and compare interrupts. The 
six active bits in this register serve different functions for each mode, as shown 
below: 

Timer 1 Control Register 3 (T1CTL3) 
[Memory Address - 104Bh] 



Bit# 



P04B 



RC-0 



Mode: Dual Compare 

4 3 2 



T1EDGE 

INT 

FLAG 


T1C2 

INT 

FLAG 


T1C1 

INT 

FLAG 


— 


— 


T1EDGE 
INT 
ENA 


T1C2 
INT 
ENA 


11 CI 
INT 

ENA 



RC-0 



RC-0 



RW-0 



RW-0 



RW-0 



Bit# 



P04B 



RC-0 



Mode: Capture/Compare 
5 4 3 2 



T1EDGE 

INT 

FLAG 


— 


T1C1 

INT 

FLAG 


— 


— 


T1EDGE 
INT 
ENA 


— 


11 CI 
INT 
ENA 



RC-0 



RW-0 



RW-0 



R = Read, W=Write, C=Clear Only, -n=\/alue after RESET 

Bit - T1C1 INT ENA. Timer 1 Compare 1 Interrupt Enable. 

This bit determines whether or not the compare register flag can generate an 
interrupt. 

= Disable interrupt. 

1 = Enable interrupt. 

Bit 1 - T1C2 INT ENA. Timer 1 Compare 2 Interrupt Enable. 

Dual Compare mode only: This bit determines whether or not the 
Capture/Compare register flag can generate an interrupt. 

= Disable interrupt. 

1 = Enable interrupt. 

Capture! Compare Mode: Read data is indeterminate. 

Bit 2 - T1EDGE INT ENA. Timer 1 Edge Interrupt Enable. 

This bit determines whether or not the active edge input to the T1IC/CR pin 
generates an interrupt. The T1EDGE DET ENA bit (T1 CTL4.0) must be set 
before an edge can be detected. 

= Disable interrupt. 

1 = Enable interrupt. 

Bits 3,4 - Reserved. Read data is indeterminate. 



Bit 5 - T1C1 INT FLAG. Timer 1 Compare 1 Interrupt Flag. 

This bit is set when the compare register first matches the counter value, 
cleared by writing a zero to this bit, or during RESET. 

= Interrupt inactive. 

1 = Interrupt pending. 



It is 



7-27 



Control Registers 



Bit 6 - T1C2 INT FLAG Timer 1 Compare 2 Interrupt Flag. 

Dual Compare Mode: This bit is set when the Capture/Compare register first 
matches the counter value. It is cleared by writing a zero to this bit or by 
RESET. 

= Interrupt inactive. 

1 = Interrupt pending. 

Capture/ Compare Mode: Reserved. Read data is indeterminate. 

Bit 7 - T1EDGE INT FLAG. Timer 1 Edge Interrupt Flag. 

This bit indicates when an external pulse transition of the correct polarity is 
detected on the Timer 1 Input-Capture/Counter- Reset (T1IC/CR) pin. This 
bit also indicates an input capture in the Capture/Compare mode. The 
T1 EDGE INT FLAG is cleared by writing a zero to the bit, or during RESET. 

= no transition 

1 = transition detected 



7-28 



Control Registers 



7.5.4 Timer 1 Counter Control Register 4 

The T1 CTL4 register controls the mode of operation, and various functions of 
the Timer 1 input and output pins. The bits in this register serve different 
functions depending on the mode, as shown below: 

Timer 1 Counter Control Register 4 (T1CTL4) 
[Memory Address - 104Ch] 



Bit# 



P04C 



RW-0 



Mode: Dual Compare 

4 3 2 



T1 

MODE 

=0 


T1C1 
OUT 
ENA 


T1C2 
OUT 
ENA 


T1C1 
RST 

ENA 


T1CR 
OUT 

ENA 


T1 

EDGE 

POLARITY 


T1CR 
RST 
ENA 


T1EDGE 
DET 

ENA 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 RW-0 



RW-0 



Bit# 



P04C 



RW-0 



RW-0 



Mode: Capture/Compare 
5 4 3 2 



T1 

MODE 

= 1 


T1C1 
OUT 
ENA 


— 


T1C1 
RST 
ENA 


— 


T1 

EDGE 

POLARITY 


— 


T1EDGE 
DET 
ENA 



RW-0 



RW-0 



RW-0 



R- Read, W- Write, -n = Value after RESET 

The function of the bits are as follows. 

Bit - T1EDGE DET ENA. Timer 1 Edge Detect Enable. 

Dual Compare Mode: This bit enables the edge detection circuit to sense the 
next level transition on the Timer 1 T1 IC/CR pin. This bit is cleared after the 
selected transition is detected or during RESET. 

= Edge detect disabled 

1 = Edge detect enabled. 

Capture/ Compare Mode: This bit enables the input capture circuit to capture 
the current counter value upon the next level transition on the counter 
reset/input capture pin, as determined by the T1 EDGE POLARITY bit. This bit 
remains unchanged after the selected transition is detected. 

= Input capture disabled. 

1 = Input capture enabled. 

Bit 1 - T1CR RST ENA. Timer 1 External Reset Enable. 

Dual Compare Mode: This bit determines whether or not an external signal 
can reset the counter. 

= Disable external reset of the counter. 

1 = Enable external reset of the counter on the next valid edge detect. 

Capture! Compare Mode: Reserved. Read data is indeterminate. 

Bit 2 - T1 EDGE POLARITY. Timer 1 Edge Polarity. 

This bit determines the transition direction on the Timer 1 T1 IC/CR pin to 
trigger a capture or counter reset, depending on the counter mode selected. 

= Trigger on a high-to-low transition. 

1 = Trigger on a low-to-high transition. 



7-29 



Control Registers 



Bit 3 - T1CR OUT ENA. Timer 1 External Edge Output Enable. 

Dual Compare Mode: This bit determines whether or not the input signal on 
the T1 IC/CR pin can toggle the output signal on the T1 PWM pin. 

= Disable pulse to toggle output. 

1 = Enable pulse to toggle output. 

Capture! Compare Mode: Reserved. Read data is indeterminate. 

Bit 4 - T1C1 RST ENA. Timer 1 Compare 1 Reset Enable. 

When this bit is set and the Compare Register 1 is equal to the Counter, the 
Counter will reset on the next counter increment. 

= Disable counter reset upon compare equal. 

1 = Enable counter reset upon compare equal. 

Bit 5 - T1C2 OUT ENA. Timer 1 Output-Compare Output Enable 2. 

Dual Compare Mode: When this bit is set and the Compare Register 2 is equal 
to the Counter, the T1 PWM pin toggles (when configured as a PWM pin). 

= Disable pulse to toggle output. 

1 = Enable pulse to toggle output. 

Capture/Compare Mode: Reserved. Read data is indeterminate. 

Bit 6 - T1C1 OUT ENA. Timer 1 Output-Compare Output Enable 1. 

When this bit is set and the Compare Register 1 is equal to the Counter, the 
T1 PWM pin toggles (when configured as a PWM pin). 

= Disable pulse to toggle output. 

1 = Enable pulse to toggle output. 

Bit 7 - Tl MODE. Timer 1 Mode Select. 

This bit selects the General Purpose Counter mode. 

= Dual compare mode 

1 = Capture/Compare mode. 



7-30 



Control Registers 



7.5.5 Timer 1 Port Control Registers 

Port Control Registers T1 PCI and T1 PC2 are organized to allow all functions 
for a pin to be programmed in one write cycle. Each module pin is controlled 
by a nibble in one of the PCRs. A summary of the Port Control Register 
functions and bit assignments is shown below. 

7.5.5.1 Timer 1 Port Control Register 1 

The T1 PCI register controls the I/O functions of the Timer 1 Module, T1 EVT 
pin. 

Timer 1 Port Control Register 1 (TIPCI) 
[Memory Address - 104Dh] 

Bit#- 7 6 5 4 3 2 1 

P04D 



— 


... 


... 


... 


T1EVT 

DATA 

IN 


T1EVT 
DATA 
OUT 


T1EVT 
FUNCTION 


T1EVT 

DATA 

DIR 



BitO 



Bit 1 



Bit 2 



Bit 3 



R = Read, W=Write, 



R-0 RW-0 

-n=\/alue after RESET 



RW-0 RW-0 



T1EVT DATA DIR. Timer 1 Event- Pin Data Direction. 

This bit selects the T1 EVT pin as an input or output, if the T1 EVT FUNCTION 

bit = 0. 

= Enable T1 EVT pin as data input. 

1 = Enable T1 EVT pin as data output. 

T1EVT FUNCTION. T1 EVT Pin Function Select. 
This bit determines the function of the T1 EVT pin. 

= T1 EVT is a general-purpose digital I/O port. 

1 = T1 EVT is the event-input pin. 

T1 EVT DATA OUT. T1 EVT Pin Data Out. 

This bit contains the data to be output on the T1 EVT pin if the following con- 
ditions are met: 

a. T1EVT DATA DIR = 1. 

b. T1 EVT FUNCTION = 0. 

T1 EVT DATA IN. T1 EVT Pin Data In. 

This bit contains the data present on the T1 EVT pin. A write operation to this 

bit has no effect. 

Bits 4-7 Reserved. Read data is indeterminate. 



7-31 



Control Registers 



7.5.5.2 Timer 1 Port Control Register 2 

The T1 PC2 register controls the I/O functions of the Timer 1 Module, 
TIIC/CRandTIPWM pins. 

Timer 1 Port Control Register 2 (T1 PC2) 
[iVIemory Address - 104Eh] 

Bit#- 
P04E 



• 7 


6 


5 


4 


3 


2 


1 





T1PWM 

DATA 

IN 


T1PWM 
DATA 
OUT 


T1PWM 
FUNCTION 


T1PWM 

DATA 

DIR 


T1IC/CR 

DATA 

IN 


T1IC/CR 

DATA 

OUT 


T1IC/CR 
FUNCTION 


T1IC/CR 

DATA 

DIR 



R-0 



RW-0 



RW-0 



RW-0 



R-0 



RW-0 



RW-0 



RW-0 



BitO- 



Bitl 



Bit 2 



Bits 



Bit4- 



Bit5- 



Bit6 



R = Read, W=Write, -n= Value after RESET 

T1IC/CR DATA DIR. T1IC/CR Pin Data Direction. 

This bit selects the T1 IC/CR pin as an input or output, if the T1 IC/CR Function 

bit = 0. 

= Enable T1 IC/CR pin data input. 

1 = Enable T1 IC/CR pin data output. 

T1IC/CR FUIMCTIOIM. T1IC/CR Pin Function Select. 
This bit determines the function of the T1 IC/CR pin. 

= the T1 IC/CR pin is a general-purpose digital I/O port 

1 = the T1 IC/CR pin is the input capture/counter reset pin. 

T1 IC/CR DATA OUT. T1 IC/CR Pin Data Out. 

This bit contains the data output on pin T1 IC/CR if the following conditions 

are met: 

a. T1 IC/CR DATA DIR = 1. 

b.TI IC/CR FUNCTION = 0. 

Tl IC/CR DATA IN. T1 IC/CR Pin Data In. 

This pin contains the data input on pin Tl IC/CR. A write operation to this bit 

has no effect. 

T1PWM DATA DIR. Tl PWM Pin Data Direction. 

This bit selects the Tl PWM pin as an input or output if the Tl PWM 

FUNCTION bit = 0. 

= Enable Tl PWM pin data input. 

1 = Enable Tl PWM pin data output. 

Tl PWM FUNCTION. Tl PMW Pin Function Select. 
This bit determines the function of the Tl PWM pin. 

= the Tl PWM pin is a general-purpose digital I/O port 

1 = the Tl PWM pin is the PWM output. 

Tl PWM DATA OUT. Tl PWM Pin Data Out. 

This bit contains the data to be output on the Tl PWM pin if the following 

conditions are met: 

a. T1PWM DATA DIR = 1 

b.TI PWM FUNCTION = 

This bit may be used to preset the PWM output level. 



Bit? 



Tl PWM DATA IN. Tl PWM Pin Data In 1 . 
This bit contains the data input on pin Tl PWM. 
has no effect. 



A write operation to this bit 



7-32 



Control Registers 



Note: 

See Section 1 3.5.1 , page 1 3-22 for examples of PWM pin initialization. 



7.5.6 Timer 1 Interrupt Priority Control Register 

The T1 PRI register controls the level of the Timer 1 interrupt. Software can 
write to this register only in the privilege mode. During normal operation this 
is a read-only register. 



Timer 1 Interrupt Priority Control Register (TIPRI) 
[Memory Address - 104Fh] 



Bit#- 
P04F 



7 


6 


5 


4 


3 


2 


1 





T1 
STEST 


T1 
PRIORITY 


— 


— 


— 


— 


— 


— 



RP-0 RP-0 

R = Read, P= Privileged Write, -n=Value after RESET 

Bits 0-5 Reserved. Read data is indeterminate. 

Bit 6 - T1 PRIORITY. Timer 1 Interrupt Priority Select. This bit determines the level 
of the interrupt generated by Timer 1. 

= Interrupts are Level 1 (high priority) requests. 

1 = Interrupts are Level 2 (low priority) requests. 

Bit 7 - T1 STEST. This bit must be cleared (0) to ensure proper operation. 



7-33 



Control Registers 



7-34 



Introduction 



TMS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Beset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface ISCI) Port 



Serial Peripheral Interface (SPI) Module BH 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



8. Timer 2 Module 



This section discusses the architecture and programming of the Timer 2 mod- 
ule on TMS370C050 and TMS370C850 devices. 

This section covers the following topics: 

Section Page 

8.1 Timer 2 Overview 8-2 

8.2 Timer 2 Operation 8-5 

8.2.1 Operation Modes 8-5 

8.2.2 Clock Sources 8-8 

8.2.3 Timer 2 Edge Detection Circuitry 8-9 

8.2.4 16-Bit Resettable Up Counter 8-9 

8.2.5 Compare Register 8-10 

8.2.6 Capture Register (Dual Capture Mode only) 8-11 

8.2.7 Capture/Compare Register 8-11 

8.2.8 Timer-2 I/O Pin Functions 8-12 

8.2.9 Timer 2 Interrupts 8-12 

8.2.10 Power-Down Modes 8-13 

8.3 Timer 2 Control Registers 8-14 

8.3.1 Timer 2 Control Register 1 8-16 

8.3.2 Timer 2 Control Register 2 8-17 

8.3.3 Timer 2 Control Register 3 8-19 

8.3.4 Timer 2 Port Control Registers 8-21 

8.3.4.1 Timer 2 Port Control Register 1 8-21 

8.3.4.2 Timer 2 Port Control Register 2 8-22 

8.4 Timer 2 Interrupt Priority Control Register 8-23 



8-1 



Timer 2 Overview 



8.1 Timer 2 Overview 



The Timer 2 module (T2), available on TMS370C050 and TMS370C850 
devices, adds an additional timer for these devices that provides event count, 
input capture, and compare functions. Figure 8-1 shows a block diagram of 
the Timer 2 Module. 



System Requirements 

Real-Time System Control 
Input Pulse Width Measurement 

External Event Synchronization 
Timer Output Control 
Pulse-Width Modulated Output 
Control 



Timer Resource 

Interval Timers with Interrupts 
Pulse Accumulate or Input 
Capture Functions 
Event Count Function 
Compare Function 
PWM Output Function 



The Timer 2 Module has three I/O pins which may be reconfigured as general 
purpose I/O Pins for use by other parts of the microcomputer. They are: 



T2EVT 

T2IC1/CR 

T2IC2/PWM 



When these pins are dedicated to the timer module, T2EVT is an input to the 
event counter or the external clock source, T2IC1/CR is an input to the 
counter reset, input capture, or PWM circuit, and T2IC2/PWM is the Pulse 
Width Modulation output or a second input capture. 

The Timer 2 Module consists of the following blocks as shown in Figure 8-1 . 

16-bit resettable up counter, 

16-bit Compare Register with associated compare logic, 

16-bit Capture Register, 

16-bit Capture/Compare Register. 

he General Purpose Counter operates in one of two modes. The mode of 
operation determines whether the Capture/Compare Register functions as a 
compare register (in the Dual Compare mode) or as a capture register (the 
Dual Capture mode). 

Timer 2 has maskable interrupts for two input captures, two output compares, 
counter overflow and external edge detect. 



8-2 



Timer 2 Overview 



T2IC1/CR PIN O- 



EDGE 
DETECT 



T2IC2/PWM PIN O- 
(DUAL 
CAPTURE 
MODE) 



EDGE 
DETECT 



16-BIT 
CAP/COMP REG 



16-BIT 
CAPTURE REG 



'^^ 



INT 
LOGIC 



T2EVT PIN 



CLOCK 
SELECT 



ie-BIT 
COUNTER 



16-BIT 
COMPARE REG 



PWM 
TOGGLE 



T2IC2/PWM PIN 
(DUAL 
COMPARE 
MODE) 



Figure 8-1. 16-Bit Programmable General Purpose Timer 2 



FEATURES 

• 16- BIT, General Purpose Counter 

- Compare Mode: Dual 16- Bit Compare Registers 

- Capture Mode: Dual Capture and one Compare Register 

- External Clock Source / Event Counter / Pulse Accumulator 

- Internal or External Counter Reset 

- Programmable Pulse Width Modulated Output 

• Selectable Edge Detection Input 
9 Programmable Interrupts 

• Three programmable I/O Pins 

Timer 2 Operating Modes: 

Dua/ Compare Mode: The counter is configured to provide dual compare 
registers, external or software reset of the counter, internal or external clock 
source, and a programmable Pulse Width Modulated (PWM) output. The 
T2IC2/PWM pin may also be configured to toggle upon an external input 
edge. The external clock source may be selected for use as an event counter 
or pulse accumulator. 



8-3 



Timer 2 Overvie\A/ 



Dual Capture Mode: The counter is configured to provide dual input capture 
registers and one compare register for use as a general purpose timer. The 
Compare Register may be used to provide periodic interrupts to the rest of the 
microcomputer. Each capture register may be configured to capture the current 
counter value upon either edge of an external input. 

Timer 2 Controi Registers 

The Timer 2 Control registers are located at addresses 1060h to 106Fh, with 
locations 1068h and 1069h reserved. The functions of these locations are 
shown in Figure 8-2. 



Peripheral 

File 
Location 


Symbol 


Name 


P060 
P061 


T2CNTR 


T2 Counter - MSB 
T2 Counter - LSB 


P062 
P063 


T2C 


T2 Compare 1 Register - MSB 
T2 Compare 1 Register - LSB 


P064 
P065 


T2CC 


T2 Capture 1 /Compare Register 2 - MSB 
T2 Capture 1 /Compare Register 2 - LSB 


P066 
P067 


T2IC 


Capture Register 2 - MSB 
Capture Register 2 - LSB 


P068 




Reserved 


P069 




Reserved 


P06A 


T2CTL1 


Timer 2 Controi Register 1 


P06B 


T2CTL2 


Timer 2 Control Register 2 


P06C 


T2CTL3 


Timer 2 Control Register 3 


P06D 


T2PC1 


Timer 2 Pin Control 1 


P06E 


T2PC2 


Timer 2 Pin Control 2 


P06F 


T2PRI 


Timer 2 Priority 



Figure 8-2. Timer 2 Memory Map 



8-4 



Timer 2 Operation 



8.2 Timer 2 Operation 



The 16-bit general purpose timer, T2, is composed of a 16-bit resettable 
counter, 16-bit Compare Register witii associated compare logic, a 16-bit 
Capture Register, and a 16-bit register that functions as a capture register in 
one mode and a compare register in the other mode. In the following para- 
graphs, the functions of each block within T2 is discussed in general and for 
each mode of operation. 



8.2.1 Operation Modes 



The Timer 2 Module mode of operation is determined by the T2 MODE bit 
(T2CTL3.7). 

T2 MODE = - Dual Compare Mode. 
T2 MODE = 1 - Dual Capture Mode. 

Dual Compare Mode 

In this mode, as illustrated in Figure A-7, the timer has two compare registers, 
an external-resettable counter, and a timer output pin. These allow the timer 
to act as an interval timer, a PWM output, simple output toggle, or many other 
timer functions. In this mode, the Capture/Compare Register functions as a 
1 6-bit read/write compare register. The operation of T2 is identical to T1 while 
operating in the Dual Compare mode with the exception of the clock sources. 



8-5 



Timer 2 Operation 



T2 IC1/ 



CR M SELECT 



6C.0 
EDGE1 POLARIPr' 6C.2 




LEVEL 1 INT 
LEVEL 2 INT 



Figure 8-3. Dual Compare Mode 



8-6 



Timer 2 Operation 



Dual Capture Mode 

In the Dual Capture Mode, illustrated in Figure A-8, T2 is configured to pro- 
vide one compare register for use as a programmable interval timer, and two 
input capture registers for external input timing and pulse width measurement. 
In this mode the Capture/Compare Register functions as 16-bit input capture 
register. Each capture input pin (T2IC1/CR and T2IC2/PWM) has an input 
edge detect function enabled by the associated DET ENA control bit, with the 
associated POLARITY bit selecting the active input transition. 

On the occurrence of a valid input on the T2IC1/CR or T2IC2/PWM pin, the 
current counter value is loaded into the 16-bit Capture/Compare Register or 
16-bit input Capture Register, respectively. In addition, the respective input 
capture INT FLAG is set and a timer interrupt is generated if the respective INT 
ENA is set. 



LSB 

MSB 



CLOCK 
SOURCE 



ie-BIT LSB 

CAPT/COMP ,— - 

REG 1 MSB 



16-BIT 
COUNTER 



RESET 



6 



S/W RESET. 

eA.o 



CMP 1 

RESET ENA 

6C.4 

o\o 



LSB 



16-BIT 
CAPTURE 
REG 2 MSB 



67 



16 



SZ. 



COMPARE 



TV 



LSB 



16-BIT 
COMPARE .,„„ 
REG MSB 



T2 101/ ,^ 
CR O 
PIN 



EDGE1 
SELECT 



EDGE 1 
DETECT ENA 1 

6C.0 
^o 



T2 IC2/ ^_^ 
PWM O 
PIN 



EDGE2 
SELECT 



r POLARITY 1 
6C.2 EDGE 1 

DETECT ENA 2 
6C.1 
o/o 



COMPARE 1 6B.0 



FLAG] 



6B.5 



INT ENA 



OVERFLOW 



[FLAG 



6A.3 



6A.4 

INT ENA 



EXT EDGE 1 



FLAG] 



6B.7 



6B.2 
-o-'o — 

INT ENA 



POLARITY 2 
6C.3 



EXT EDGE 2 



Lflag 



6B.6 



6B.1 

-<yo — 

INT ENA 



8F.6 



<^ 



LEVEL 1 INT 



LEVEL 2 INT 



Figure 8-4. Dual Capture Mode 



8-7 



Timer 2 Operation 



8.2.2 Clock Sources 



Timer 2 clock sources are illustrated in Figure 8-5. The T2 INPUT SELECT 
bit (T2CTL1 .1 ) and the T2 INPUT SELECT 1 bit (T2CTL1 .2) select one of four 
clock sources: 

• system clock, 

• no clock (in which the counter is stopped), 

• external clock synchronized to the system clock (event counter), or 

• system clock when external input is high (pulse accumulation). 

The maximum counter duration with an internal clock is based on the internal 
system clock time (SYSCLK) as follows: 

Maximum Counter Duration = 2''^ * SYSCLK 
Counter Resolution = SYSCLK 

where; SYSCLK = 4 / CLKIN 

The external event frequency input to the module may not exceed CLKIN/8. 
All external event inputs are synchronized with the system clock. 

When using the system clock input, the 16-bit timer generates an overflow 
rate of 13.1 ms with 200 ns resolution (CLKIN = 20 MHz). 

Event Counter Mode 

Using this clock source, the general purpose timer is programmable as a 1 6-bit 
event counter. An external low-to-high transition on the T2EVT pin is used to 
provide the clock for the internal timer. The T2EVT external clock frequency 
may not exceed the system clock frequency divided by 2. 

Pulse Accumulator Mode 

Using this clock source, the general purpose timer is programmable as a 1 6-bit 
pulse accumulator. An external input on the T2EVT pin is used to gate the 
internal system clock to the internal timers. While T2EVT input is logic one 
(high), the timer is clocked at the system clock rate and counts system clock 
pulses until the T2EVT pin returns to logic zero. 



T2EVT PIN O- 




SELECT 

Figure 8-5. Timer 2 Clock Sources 



8-8 



Timer 2 Operation 



8.2.3 Timer 2 Edge Detection Circuitry 

This edge detection circuitry senses an active pulse transition on the input pins 
and provides appropriate output transitions to the rest of the module. 

Dual Compare Mode 

The edge detection circuitry is connected to the module's T2IC1/CR pin. In 
this mode, the program must re-enable the Timer 2 Module after each edge 
detection by setting the T2EDGE1 DET ENA bit (T2CTL3.0). 

When the Timer 2 module detects an active transition (while enabled), the 
module performs the following actions: 

1) clears the T2EDGE DET ENA bit, 

2) sets the external edge flag, T2EDGE1 INTERRUPT FLAG (T2CTL2.7), 

3) resets the counter if T2EDGE1 RST ENA bit (T2CTL3.1 ) is set, and 

4) toggles the output flip-flop if the T2EDGE1 OUT ENA bit (T2CTL3.3) 
is set. 

In the Dual Compare mode, the T2EDGE1 POLARITY bit (T2CTL3.2) deter- 
mines whether the active transition is low-to-high or high-to-low. 

Dual Capture Mode 

Edge detection circuitry is connected to both the T2IC1/CR pin and the 
T2IC2/PWM pin. 

When the Edge 1 Detect circuit detects an active edge transition on the 
T2IC1/CRpin: 

1 ) the Capture/Compare Register is loaded with the current counter value, 
and 

2) the T2EDGE1 INT FLAG bit is set. 

When the Edge 2 Detect circuit detects an active edge transition on the 
T2IC2/PWM pin: 

1 ) the Capture Register is loaded with the current counter value, and 

2) the T2EDGE2 INT FLAG bit is set. 

The T2EDGE1 POLARITY bit (T2CTL3.2) and the T2EDGE2 POLARITY bit 
(T2CTL3.3) determine the transition (rising or falling) to be detected. 



8-9 



Timer 2 Operation 



8.2.4 16-Bit Resettable Up Counter. 

The counter is a free-running, 16-bit, read-only, up-counter clocked by the 
system clock, external event, or system clock while an external event is active 
(pulse accumulate). During initialization, the counter is loaded with OOOOh 
and begins its up-count. If the counter is not reset before reaching FFFFh, the 
counter rolls over to OOOOh and continues counting. Upon counter roll-over, 
the T2 OVRFL INT FLAG (T2CTL1 .3) is set, and a timer interrupt is generated 
if the T20VRFL INT ENA bit (T2CTL1 .4) is set. 

The counter may be reset to OOOOh during counting by either: 

1 ) writing a 1 to the T2 SW RESET bit (T2CTL1 .0), 

2) a compare equal condition from the dedicated T2 compare function, 

3) System RESET, or 

4) an external pulse on the T2IC/CR pin (Dual Compare mode only). 

The designer may select by software (T2CR POLARITY bit) which external 
transition, low-to-high or high-to-low, on the T2IC1/CR pin will cause the 
counter to be reset. 

Special circuitry prevents the contents of the T2CNTR register from changing 
in the middle of a 1 6-bit read operation. See the note in Section 8.3. on page 
8-14 

8.2.5 Compare Register 

The Compare Register circuit consists of a 16-bit wide, read/write data regis- 
ter (T2C) and logic to compare the counter's current value with the value 
stored in the Compare Register. 

Special circuitry prevents the T2C register from changing in the middle of a 
16-bit read or write operation. See the note in Section 8.3. on page 8-14 

The compare logic sets T2C1 INT FLAG (T2CTL2.5) as soon as the value in 
the timer matches that in the Compare Register. Once T2C1 INT FLAG is set 
by a compare-equal condition, then cleared, it will not be set again if the same 
compare-equal condition still exists, i.e., the same compare-equal condition 
can only set the T2C1 INT FLAG once. This flag causes various events to 
occur depending on the mode of operation and which enable bits are set. 

On a compare equal condition, the T2 module: 

1 ) sets the T2C1 INT FLAG bit (T2CTL2.5), 

2) generates an interrupt if the T2C1 INT ENA bit (T2CTL2.0 ) is set, and 

3) resets the counter if T2C1 RST ENA bit (T2CTL3.4) is set. 

In Dual Compare Mode only: 

4) toggles the PWM output pin if the T2C1 OUT ENA bit (T2CTL3.6) is 
set. 



8-10 



Timer 2 Operation 



8.2.6 Capture Register (Dual Capture Mode only) 

The Capture Register is a 16-bit wide, read-only, data register (T2IC). This 
register captures the counter values when an input capture pulse (pin 
T2IC2/PWM) is received. The Capture Register can be read at addresses 
P066 (MSB) and P067 (LSB) of the Peripheral File. Writes to this register 
are ignored. Thus, the Capture Register retains the last counter value captured 
until another input capture pulse loads a new value in the register. 

On receipt of a capture pulse, the following events occur: 

1 ) value of counter is loaded into the Capture Register, 

2) the module sets the T2EDGE2 INT FLAG bit (T2CTL2.6) to indicate that 
the Capture Register has latched the current counter value, and 

3) the module generates an interrupt if the T2C2 INT ENA bit (T2CTL2.1 ) 
is set. 

Special circuitry prevents the T2IC register from changing in the middle of a 
16-bit read or write operation. See the note in Section 8.3. on page 8-14 

8.2.7 Capture/Compare Register. 

The Capture/Compare Register (T2CC) for Timer 2 is a 16-bit wide register 
which can be programmed to serve one of two functions. In the Dual Capture 
Mode this register functions as a capture register and in the Dual Compare 
Registers Mode, it functions as a compare register. The Capture/Compare 
Register is located at addresses P064 (MSB) and P065 (LSB) of the Periph- 
eral File. 

Special circuitry prevents the T2CC register from changing in the middle of a 
16-bit read or write operation. See the note in Section 8.3 on page 8-14. 

Dual Compare Mode 

In the Dual Compare mode, the Capture/Compare Register becomes a 
read/write compare register. This compare register's functions are similar to 
the dedicated Compare Register except that it can not reset the counter. 

In this mode, the current counter value and the current Capture/Compare 
register value are directed to compare logic which generates a pulse when the 
two values match. This pulse is used to: 

1 ) set the T2C2 INT FLAG bit (T2CTL2.6), 

2) toggle the PWM output pin if the T2C2 OUT ENA bit (T2CTL3.5) is set, 
and 

3) generate an interrupt if the T2C2 INT ENA bit (T2CTL2.1 ) is set. 



8-11 



Timer 2 Operation 



Dual Capture Mode 

In the Dual Capture Mode, the Capture/Compare Register becomes a read- 
only capture register. When an external pulse appears on pin T2IC1/CR, the 
following events occur if the T2EDGE1 DET ENA bit (T2CTL3.0) is set. 

1 ) the current counter value is latched into the Capture/Compare register. 

2) the T2EDGE1 INT FLAG bit (T2CTL2.7) is set. 

3) an interrupt is generated if the T2EDGE1 INT ENA bit (T2CTL2.2) is set. 



8.2.8 Timer-2 I/O Pin Functions 



The Timer 2 module has three I/O pins which may be dedicated as timer 
functions or used as general purpose I/O pins. The definitions of these pins 
are contained in the two Port Control Registers located at addresses P06E and 
P06D of the Peripheral File. 

Table 7-1 defines the functions of the three Timer-2 I/O pins for both oper- 
ating modes. 

Table 8-1. Timer 2 I/O Pin Definitions 



mi 


-mM.<;mmfm.w>m . 


DUAL COMPARE MOW 


T2IC1/CR 

T2IC2/PWM 

T2EVT 


COUNTER RESET INPUT 

PWM OUTPUT 

EXTERNAL EVENT INPUT OR 
PULSE ACCUMULATE INPUT 


INPUT CAPTURE 1 INPUT 

INPUT CAPTURE 2 INPUT 

EXTERNAL EVENT INPUT OR 
PULSE ACCUMULATE INPUT 



8.2.9 Timer 2 Interrupts 



Interrupts may be enabled to occur upon an input capture, output compare 
equal, counter overflow and/or upon an external edge detect. 

Dual Compare Mode: 

In this mode, interrupts are generated when any of the following events occur: 

1 ) when a compare equal condition occurs for the dedicated Compare 
Register if the T2C1 INT ENA bit (T2CTL2.0) is set, 

2) when a compare equal condition occurs for the Capture/Compare 
Register if the T2CC2 INT ENA bit (T2CTL2.1 ) is set, 

3) when the counter overflows if the T2 OVERFL INT ENA bit (T2CTL1 .4) 
is set, or 

4) when an External Edge detect occurs if the T2EDGE1 DET ENA and 
T2EDGE1 INT ENA h\ts are set (T2CTL3.0 and T2CTL2.2 respectively). 



8-12 



Timer 2 Operation 



Dual Capture Mode: 

In this mode, interrupts are generated when any of the following events occur: 

1 ) when a compare equal condition occurs for the dedicated Compare 
Register if the T2C1 INT ENA bit (T2CTL2.0) is set, 

2) when the counter overflows if the T2 OVERFL INT ENA bit (T2CTL1 .4) 
is set, 

3) when an External Edge 1 detect occurs if the T2EDGE1 DET ENA and 
T2EDGE1 INT ENA bits are set (T2CTL3.0 and T2CTL2.2), or 

4) when an External Edge 2 detect occurs if the T2EDGE2 DET ENA and 
T2EDGE2 INT ENA bits are set (T2CTL3.1 and T2CTL2.1). 



Note: 

All set and enabled interrupt flags must be cleared before exiting the T2 
interrupt routine. If the flags are not reset, then the processor will enter the 
T2 interrupt routine again instead of continuing the mainstream program. 
If the flag bits are never reset then the program will lock up. 



8.2.10 Power-Down Modes 



This module supports the power-down modes which aid in reducing power 
consumption during periods of inactivity. In both the Halt and Standby modes, 
no clocks or external inputs are recognized. 

The low-power modes are entered when an IDLE instruction is executed by 
the CPU if the POWERDOWN/IDLE bit (SCCR2.6) is set. During the low- 
power mode, the Timer 2 Module holds the pre-idle status of all storage ele- 
ments. The module's external pins are held constant regardless of the pin 
function, i.e., inputs remain inputs, output low levels remain low, and output 
high levels remain high. When the idle state is exited, the I/O Timer Module 
continues where it left off. 



8-13 



Timer 2 Control Registers 



8.3 Timer 2 Control Registers 

Peripheral File registers control the Timer 2 module operating mode selection, 
interrupt enable, status flags, and output configuration. These registers are 
shown in Table 8-2 The bits shown in shaded boxes in Table 8-2 are Privilege 
Mode bits, that is, they can only be written to in the Privilege Mode. 



Note: 

Special circuitry prevents 16-bit registers from changing in the middle of 
a 16-bit read or write operation. When reading a 16-bit register, read the 
least-significant byte (LSB) first to lock in the value and then read the 
most-significant byte (MSB). When writing to a 16-bit register, write the 
MSB first and then write the LSB. The register value does not change 
between reading or writing the bytes when done in this order. While 
accessing a 16-bit register, do not read or write from a second 16-bit 
register within this module and expect a correct value for the first register's 
MSB. The 1 6-bit read/write operation actually occurs when accessing the 
LSB. 

Read: LSB then MSB 
Write: MSB then LSB 



8-14 



Timer 2 Control Registers 



Table 8-2. Peripheral File Frame 6: Timer 2 Control Registers 

PERIPHERAL FILE FRAME 6: TIMER 2 MODULE CONTROL REGISTERS 



ADDR PF 

1060h 060 

1061h 061 

1062h 062 

1063h 063 

1064h 064 

1065h 065 

1066h 066 

1067h 067 

1068h 068 

1069h 069 

106Ah 06A 



BIT 7 


BIT 6 


BIT 5 


BIT 4 


BIT 3 


BIT 2 


BIT 1 


BIT 


BIT 15 




T2 COUNTER MSB 




BITS 


BIT 7 




T2 COUNTER LSB 




BITO 


BIT 15 




T2 COMPARE 1 REGISTER MSB 




BIT 8 


BIT 7 




T2 COMPARE 1 REGISTER LSB 




BIT 


BIT 15 




CAPTURE 1/COMPARE 2 REGISTER MSB 




BIT 8 


BIT 7 




CAPTURE 1/COMPARE 2 REGISTER LSB 




BITO 


BIT 15 




CAPTURE REGISTER 2 MSB 




BITS 


BIT 7 




CAPTURE REGISTER 2 LSB 




BIT 


RESERVED 





— 





T2 OVRFL 
INT ENA 


T2 OVRFL 
INT FLAG 


T2 INPUT 
SELECT 1 


T2 INPUT 
SELECT 


T2 

SW RESET 



T2CNTR 



T2C 



T2CC 



T2IC 



MODE: DUAL COMPARE REGISTERS 



106Bh 06B 



106Ch 06C 



T2EDGE1 
INT FLAG 


T2C2 
INT FLAG 


T2C1 
INT FLAG 








T2EDGE1 
INT ENA 


T2C2 
INT ENA 


T2C1 
INT ENA 


T2M0DE 
= 


T2C1 
OUT ENA 


T2C2 
OUT ENA 


T2C1 
RST ENA 


T2EDGE1 
OUT ENA 


T2EDGE1 
POLARITY 


T2EDGE1 
RST ENA 


T2EDGE1 
DET ENA 



MODE: DUAL CAPTURE AND SINGLE COMPARE REGISTERS 



106Bh 06B 



106Ch 06C 



T2EDGE1 
INT FLAG 


T2EGDE2 
INT FLAG 


T2C1 
INT FLAG 








T2EDGE1 
INT ENA 


T2EGDE2 
INT ENA 


T2C1 
INT ENA 


T2M0DE 
= 1 








T2C1 
RST ENA 


T2EGDE2 
POLARITY 


T2EDGE1 
POLARITY 


T2EDGE2 
DET ENA 


T2EDGE1 
DET ENA 



T2CTL1 



T2CTL2 



T2CTL3 



T2CTL2 



T2CTL3 



106Dh 06D 



106Eh 06E 



106Fh 06F 



— 


— 


— 





T2EVT 
DATA IN 


T2EVT 
DATA OUT 


T2EVT 
FUNCTION 


T2EVT 
DATA DIR 


T2IC2/ 

PWM 

DATA IN 


T2IC2/ 

PWM 

DATA OUT 


T2IC2/ 

PWM 

FUNCTION 


T2IC2/ 

PWM 

DATA DIR 


T2IC1/ 

CR 
DATA IN 


T2IC1/ 

CR 

DATA OUT 


T2IC1/ 

CR 

FUNCTION 


T2IC1/ 

CR 

DATA DIR 


T2 

8TEST 


T2 

PRIORffY 





















T2PC1 



T2PC2 



T2PRi 



8-15 



Timer 2 Control Registers 



8.3.1 Timer 2 Control Register 1 



The T2CTL1 register controls the clock input selection, counter overflow 
interrupts, and counter software reset. 

Timer 2 Control Register 1 (T2CTL1) 
[Memory Address - 106Ah] 



Bit#- 
P06A 



7 


6 


5 


4 


3 


2 


1 





— 


— 


... 


T2 OVRFL 
INT 
ENA 


T2 OVRFL 

INT 

FLAG 


T2 INPUT 

SELECT 

1 


T2 INPUT 

SELECT 




T2 

SW 

RESET 



BitO 



RW-0 RC-0 RW-0 RW-0 S-0 

R=Read, S=Set only, W=Write, C=Clear only, -n= Value after RESET 

T2 SW RESET. Timer 2 Software Reset. 

When a one is written to this bit, the counter will reset to OOOOh on the next 

system clock cycle, however, this bit is always read as a zero. 



Bits 1,2 - T2 INPUT SELECT 0-1. Timer 2 Input Select 0,1. 

These two bits select one of four clock sources as an input to the counter. The 
four options are: 

- system clock with no prescale, 

- system clock when external input is high (pulse accumulation), 

- external source synchronized with system clock (event input). 

- no clock. 

The combinations are shown below. 



Bit 2 


Bit1 


Counter Clock Source 




1 
1 



1 

1 


system clock 
pulse accumulation 
event input 
no clock input 



Bit 3 - T2 OVRFL IIMT FLAG. Timer 2 Overflow Interrupt Flag. 

This bit is the Timer 2 Counter Overflow Bit. It is cleared by writing a zero to 
this bit or during RESET. 

= Overflow interrupt inactive. 

1 = Overflow interrupt pending. 

Bit 4 - T2 OVRFL INT ENA. Timer 2 Overflow Interrupt Enable. 

This bit controls the Timer 2 overflow interrupting capability. 

= Disable Interrupt. 

1 = Enable Interrupt from overflow. 

Bits 5,6,7 - Reserved. Read data is indeterminate. 



8-16 



Timer 2 Control Registers 



8.3.2 Timer 2 Control Register 2 



Bit#- 
P06B 



Bit# 



P06B 



The T2CTL2 register contains interrupt flags and controls the capability of the 
module to issue interrupts. 

Timer 2 Control Register 2 (T2CTL2) 
[Memory Address - 106Bh] 

Mode: Dual Compare 

7 6 5 4 3 2 10 



T2EDGE1 
INT 
FLG 


T2C2 
INT 
FLG 


T2C1 

INT 
FLG 


— 


... 


T2EDGE1 
INT 
ENA 


T2C2 
INT 
ENA 


T2C1 
INT 
ENA 


RC-0 


RC-0 


RC-0 




RW-0 


RW-0 


RW-0 








Mode: Dual Capture 






7 


6 


5 


4 


3 2 


1 





T2EDGE1 
INT 
FLG 


T2EDGE2 
INT 
FLG 


T2C1 
INT 
FLG 


— 


... 


T2EDGE1 
INT 
ENA 


T2EDGE2 
INT 
ENA 


T2C1 
INT 
ENA 



RC-0 RC-0 RC-0 RW-0 RW-0 RW-0 

R = Read, W=Write, C=Clear only, -n= Value after RESET 

Bit - T2C1 INT ENA. Timer 2 Compare 1 Interrupt Enable. 

This bit controls the interrupting capability of the Compare 1 register. 

= Disable interrupt. 

1 = Enable interrupt from Compare 1 register. 

Bit 1 - Dual Compare Mode: 

T2C2 INT ENA. Timer 2 Output Compare 2 Interrupt Enable. 

This bit controls the interrupting capability of the Compare 2 register. 

= Disable interrupt. 

1 = Enable interrupt from Compare 2 register. 

Dual Capture Mode: 

T2EDGE2 INT ENA. Timer 2 External Edge 2 Interrupt Enable. 

This bit determines whether or not the active edge input to the T2IC2/PWM 

pin generates an interrupt. 

= Disable interrupt. 

1 = Enable interrupt. 

Bit 2 - T2EDGE1 INT ENA. Timer 2 External Edge 1 Interrupt Enable. 

This bit determines whether or not the active edge input to the T2IC1/CR pin 
generates an interrupt. 

= Disable interrupt. 

1 = Enable interrupt. 

Bit 3,4 - Reserved. Read data is indeterminate. 

Bit 5 - T2C1 INT FLAG. Timer 2 Output Compare 1 Interrupt Flag. 

This bit is set when the output Compare Register first matches the counter 
value, it is cleared by writing a zero to this bit, or during RESET. 

= Interrupt inactive. 

1 = Interrupt pending from Compare 1. 



8-17 



Timer 2 Control Registers 



Bit 6 - Dual Compare Mode: 

T2C2 INT FLAG. Timer 2 Output Compare 2 Interrupt Flag. 

This bit is set when the Capture/Compare Register first matches the counter 

value. It is cleared by writing a zero to this register bit, or during RESET. 

= Interrupt inactive. 

1 = Interrupt pending from Compare 2. 

Dual Capture Mode: 

T2EDGE2 INT FLAG. Timer 2 Edge 2 Interrupt Flag. 

This bit is set when the appropriate edge is detected on T2IC2/PWM and 

indicates that the Capture Register was loaded. It is cleared by writing a zero 

to this register bit, or during RESET. 

= Interrupt inactive. 

1 = Interrupt pending from Edge 2 Detect. 

Bit 7 - T2EDGE1 INT FLAG.Timer 2 External Edge 1 Interrupt Flag. 

This bit is set when the appropriate edge is detected on the T2IC1/CR pin. It 
is cleared by writing a zero to this register bit, or during RESET. 

= Interrupt inactive. 

1 = Interrupt pending from Edge 1 Detect circuitry. 



8-18 



Timer 2 Control Registers 



8.3.3 Timer 2 Control Register 3 



Bit# 



P06C 



The T2CTL3 register controls the Timer 2 module mode of operation, outputs, 
active transition polarity, and counter reset. 

Timer 2 Control Register 3 (T2CTL3) 
[Memory Address - 106Ch] 

Mode: Dual Compare 

7 6 5 4 3 2 10 



Bit#- 



P06C 



T2 

MODE 

=0 


T2C1 
OUT 
ENA 


T2C2 
OUT 
ENA 


T2C1 
RST 
ENA 


T2EDGE1 
OUT 
ENA 


T2EDGE1 
POLARITY 


T2EDGE1 
RST 
ENA 


T2EDGE1 
DET 
ENA 


RW-0 

7 


RW-0 
6 


RW-0 RW-0 RW-0 RW-0 

Mode: Dual Compare 
5 4 3 2 


RW-0 
1 


RW-0 



T2 

MODE 

=1 


— 


— 


T2C1 
RST 

ENA 


T2EDGE2 
POLARITY 


T2EDGE1 
POLARITY 


T2EDGE2 
DET 
ENA 


T2EDGE1 
DET 
ENA 



RW-0 



RW-0 RW-0 RW-0 RW-0 

R=Read, W=Write, -n= Value after RESET 



RW-0 



Bit - T2EDGE1 DET ENA: . Timer 2 Edge 1 Detect Enable. 

This bit enables the edge detection circuit to sense the next active level tran- 
sition on the T2IC1/CR pin. This bit is cleared after the selected transition is 
detected or during RESET. 

= Edge 1 detect disabled. 

1 = Edge 1 detect enabled. 

Bit 1 - Dual Compare Mode: 

T2EDGE1 RST ENA. Timer 2 Edge 1 Detect Reset Enable. 

This bit controls whether or not an external signal can reset the counter. 

= Disable external reset of the counter. 

1 = Enable external reset of the counter. 

Dual Capture Mode: 

T2EDGE2 DET ENA. Timer 2 External Edge 2 Detect Enable. 
This bit enables the edge detection circuit to sense the next active level tran- 
sition on the T2IC2/PWM pin. This bit is cleared after the selected transition 
is detected or during RESET. 

= Edge detect disabled. 

1 = Edge detect enabled. 

Bit 2 - T2EDGE1 POLARITY. Timer 2 Edge 1 Polarity Select. . 

This bit controls which level transition on the T2IC1/CR pin is active. 

= Trigger on high-to-low transition. 

1 = Trigger on low-to-high transition. 



8-19 



Timer 2 Control Registers 



Bit 3 - Dual Compare Mode: 

T2EDGE1 OUT ENA. Timer 2 Edge 1 Detect Output Enable. 

This bit controls whether or not the pulse indicating an external edge detect 

toggles the module's output pin. 

= Disable pulse to toggle output. 

1 = Enable pulse to toggle output. 

Dual Capture Mode: 

T2EDGE2 POLARITY. Timer 2 Edge 2 Polarity Select. 

This bit controls which level transition on the T2IC2/PWM 1 pin, will trigger 

a counter reset, depending upon the counter mode selected. 

= Trigger on high-to-low transition. 

1 = Trigger on low-to-high transition. 

Bit 4 - T2C1 RST ENA. Timer 2 Output Compare 1 Reset Enable. 

This bit controls whether or not the compare equal pulse from the Compare 
Register resets the counter on the next counter increment. 

= Disable reset upon compare equal. 

1 = Enable reset upon compare equal. 

Bit 5 - Dual Compare Mode: 

T2C2 OUT EIMA. Timer 2 Output Compare 2 Enable. 

This bit controls whether or not the output compare equal pulse from the 

Capture/Compare Register toggles the T2IC2/PWM output pin. 

= Disable pulse to toggle output. 

1 = Enable pulse to toggle output. 

Dual Capture Mode: 

Reserved. Read data is indeterminate. 

Bit 6 - Dual Compare Mode: 

T2C1 OUT ENA. Timer 2 Output Compare 1 Enable. 

This bit controls whether or not the compare equal pulse from the Compare 

Register toggles T2IC2/PWM pin. 

= Disable pulse from toggling output. 

1 = Enable pulse to toggle output. 

Dual Capture Mode: 

Reserved. Read data is indeterminate. 

Bit 7 - T2 MODE. Timer 2 Mode Select. 

This bit selects the operating mode for the counter. 

= Dual Compare mode. 

1 = Dual Capture mode. 



8-20 



Timer 2 Control Registers 



8.3.4 Timer 2 Port Control Registers 

The Port Control Registers (T2PC1, T2PC2) control the functions of the I/O 
pins. Each module pin is controlled by a nibble in one of the PCRs. 



8.3.4.1 Timer 2 Port Control Register 1 

The T2PC1 register assigns the I/O function of the T2EVT pin as either a 
general-purpose digital I/O or external event input of the module. 



Bit#- 

P06D 



Timer 2 Port Control Register 1 (T2PC1) 
[Memory Address - 106Dh] 



7 


6 


5 


4 


3 


2 


1 





— 


— 


— 


— 


T2EVT 

DATA 

IN 


T2EVT 
DATA 
OUT 


T2EVT 
FUNCTION 


T2EVT 

DATA 

DIR 



R-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET 



RW-0 



Bit - T2EVT DATA DIR. Timer 2 Event Pin Data Direction. 

This bit determines the data direction on the T2EVT pin if the T2EVT 
FUNCTION bit = 0. 

= T2EVT2 is configured as input. 

1 = T2EVT is configured as output. 

Bit 1 - T2EVT FUNCTION. Timer 2 Event Pin Function Select. 
This bit selects the function of the T2EVT pin. 

= T2EVT is a general-purpose digital I/O port. 

1 = T2EVT is the event input pin. 

Bit 2 - T2EVT DATA OUT. Timer 2 Event Pin Data Out. 

This bit contains the data to be output on the T2EVT pin if the following con- 
ditions are met: 

a. T2EVT DATA DIR = 1 

b. T2EVT FUNCTION = 

Bit 3 - T2EVT DATA IN. Timer 2 Event Pin Data In. 

This bit contains the data to be input from the T2EVT pin. A write to this bit 
has no effect. 

Bits 4,5,6,7 - Reserved. Read data is indeterminate. 



8-21 



Timer 2 Control Registers 



8.3.4.2 Timer 2 Port Control Register 2 

The T2PC2 register assigns the I/O functions of the T2IC1/CR and 
T2IC2/PWM pins as either general-purpose digital I/O pins or the input- 
capture/counter-reset and PWM output pins, respectively. 

Timer 2 Port Control Register 2 (T2PC2) 
[Memory Address - 106Eh] 

Bit# 

P06E 



7 


6 


5 


4 


3 


2 


1 





T2IC2/ 

PWM 

DATA IN 


T2IC2/ 

PWM 

DATA OUT 


T2IC2/ 

PWM 

FUNCTION 


T2IC2/ 

PWM 

DATA DIR 


T2IC1/ 

CR 
DATA IN 


T2IC1/ 

CR 

DATA OUT 


T2IC1/ 

CR 

FUNCTION 


T2IC1/ 

CR 

DATA DIR 



R-0 



RW-0 



RW-0 RW-0 



R-0 



RW-0 RW-0 



RW-0 



R = Read, W=Write, -n= Value after RESET 



BitO 



Biti 



Bit 2 



Bit 3 - 



Bit 4 



Bit 5 



Bits - 



Bit 7 



T2IC1/CR DATA DIR. Timer 2 IC1/CR Data Direction. 

This bit determines the direction of data on the T2IC1 /CR pin if the T2IC1 /CR 

FUNCTION bit = 0. 

= T2IC1/CR is an input. 

1 = T2IC1/CR is an output. 

T2IC1/CR FUIMCTIOIM. Timer 2 IC1/CR Function Select. 
This bit determines the function of the T2IC1 /CR pin. 

= T2IC1/CR is a general-purpose digital I/O port. 

1 = T2IC1/CR is the input capture/counter reset pin. 

T2IC1/CR DATA OUT. Timer 2 IC1/CR Data Out. 

This bit contains the data output on the T2IC1/CR pin if the following condi- 
tions are true: 

a. T2IC1/CR DATA DIR = 1 

b. T2IC1/CR FUNCTION = 

T2IC1/CR DATA IN. Timer 2 IC1/CR Data In. 

This bit contains the data input on the T2IC1/CR pin. A write to this bit has 

no effect. 



IC2/PWM Data Direction. 

of data on the T2IC2/PWM pin if the 



T2IC2/PWM DATA DIR. Timer 2 
This bit determines the direction 
T2IC2/PWM FUNCTION bit = 0. 

= T2IC1/PWMisan input. 

1 = T2IC2/PWM is an output. 

T2IC2/PWM FUNCTION. Timer 2 IC2/PWM Function Select. 
This bit determines the function of the T2IC2/PWM pin. 

= T2IC2/PWI\/l is a general-purpose digital I/O port. 

1 = T2IC2/PWM is the input capture/PWM output pin. 

T2IC2/PWM DATA OUT. Timer 2 IC2/PWM Data Out. 

This bit contains the data output on the T2IC2/PWM pin if the following 

conditions are true: 

a. T2IC2/PWM DATA DIR = 1 

b. T2IC2/PWM FUNCTION = 

T2IC2/PWM DATA IN. Timer 2 IC2/PWM Data In. 

This bit contains the data input on the T2IC2/PWM pin. A write to this bit has 

no effect. 



8-22 



Timer 2 Control Registers 



8.3.5 Timer 2 Interrupt Priority Control Register 

The T2PRI register assigns the priority level of interrupts generated by the 
Timer 2 module. 

Timer 2 Priority Control Register (T2PRI) 
[Memory Address - 106Fh] 

Bit #-7 6 5 4 3 2 1 

P06F 



T2 
STEST 


T2 
PRIORITY 


— 


... 


— 


... 


— 


— , 



RP-0 RP-0 

R = Read, P=Privileged Write, -n= Value after RESET 



Bits 0-5 - Reserved. Read data is indeterminate. 

Bit 6 - T2 PRIORITY. Timer 2 Interrupt Priority Select. 
This bit determines the level of Timer 2 interrupts. 

= Interrupts are level 1 (high priority) requests. 

1 = Interrupts are level 2 (low priority) requests. 

Bit 7 - T2 STEST. 

This bit must be cleared (0) to ensure proper operation. 



8-23 



Timer 2 Control Registers 



8-24 



Introduction 



TMS370 Family Devices 



pPU and fi/fer^^ 



System and Djigital 1/6 C^ 



|int^rrupts:;:inii;^;S^ 



EEPBOIVI Module^ 



ilTpmiiiliVlodulii 



i^imii2l,M{^<lijli:i 



Serial Communications Interface (SCI) Port 



Siffial PeripNiral Interface (SPI) Module Ul* 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Infomnation 



Appendixes 



9. Serial Communications Interface (SCI) Port 



This section discusses the architecture and programming of the Serial Com- 
munications Interface module on TMS370C050 and TMS370C850 devices. 

This section covers the following topics: 

Section Page 

9.1 SCI Overview 9-2 

9.1.1 Physical Description 9-2 

9.1.2 SCI Features 9-4 

9.1.3 SCI Formats and Operation Modes 9-5 

9.1.4 SCI Control Registers 9-6 

9.2 SCI Operation 9-7 

9.2.1 SCI Programmable Data Format 9-7 

9.2.2 SCI Port Interrupts 9-7 

9.2.3 SCI Clock Sources 9-8 

9.2.4 SCI Communications Modes 9-9 

9.2.4.1 Asynchronous Communications Mode 9-9 

9.2.4.2 SCI Isosynchronous Communications Mode 9-10 

9.2.4.3 Receiver Signals in Communications Modes 9-11 

9.2.4.4 Transmitter Signals in Communications Modes 9-12 

9.2.5 SCI Multiprocessor Communications 9-13 

9.2.5.1 Idle Line Multiprocessor Mode 9-14 

9.2.5.2 Address Bit Multiprocessor Mode 9-15 

9.2.6 SCI Initialization Examples 9-16 

9.2.6.1 RS-232-C Example 9-17 

9.2.6.2 RS-232-C Multiprocessor Mode Example 9-18 

9.3 SCI Control Registers 9-19 

9.3.1 Communication Control Register (SCICCR) 9-20 

9.3.2 Control Register (SCICTL) 9-22 

9.3.3 Baud Select Registers (BAUD MSB and BAUD LSB) 9-24 

9.3.4 Transmitter Interrupt Control and Status Register (TXCTL) 9-25 

9.3.5 Receiver Interrupt Control and Status Register (RXCTL) 9-26 

9.3.6 Receiver Data Buffer Register (RXBUF) 9-28 

9.3.7 Transmit Data Buffer Register (TXBUF) 9-28 

9.3.8 Port Control Register 1 (SCIPC1) 9-29 

9.3.9 Port Control Register 2 (SCIPC2) 9-30 

9.3.10 Priority Control Register (SCIPRI) 9-31 



9-1 



SCI Overvie\A/ 



9.1 SCI Overview 



The programmable Serial Communications Interface (SCI) allows digital 
communications between the TMS370 device and other asynchronous peri- 
pherals using the standard NRZ (Non Return to Zero) format. Both the SCI 
receiver and transmitter are double buffered and have their own separate ena- 
ble and interrupt bits. Thus, they may be operated independently or simul- 
taneously in the Full Duplex mode. 

To ensure data integrity, the SCI checks received data for Break detection. 
Parity, Overrun, and Framing errors. The speed of operation, or Baud rate, is 
programmable to over 65,000 different speeds through a 16-bit baud-select 
register. 



9.1.1 Physical Description 



The major elements of the full-duplex SCI is shown in Figure A-9 and in- 
cludes: 

1) a transmitter (TX), 

a) TXBUF - Transmitter Buffer Register, contains data written by the 
CPU, to be transmitted. 

b) TXSHF - Transmitter Shift Register, loaded from TXBUF, shifts 
data onto SCITXD pin one bit at a time. 

2) a receiver (RX), 

a) RXSHF - Receiver Shift Register, shifts data in from SCIRXD pin 
one bit at a time. 

b) RXBUF - Receiver Buffer Register, contains data to be read by the 
CPU, received from remote processor, loaded from RXSHF. 

3) a programmable baud rate generator, and 

4) memory mapped control and status registers. 

The SCI receiver and transmitter can operate independently and simultane- 
ously. A third port line (SCICLK) is available for the optional synchronizing 
clock line in the Isosynchronous mode. 



9-2 



SCI Overview 



50 



FRAME 

FORMAT 

AND MODE 



PARITY 



EVEN/ODD ENA 



50.6 50.5 



SYS 

CLK 



53 



52 



LSB 



MSB 



SCIRXD r^ 



PIN 



55.1 



51.3 



TXWAKE 



TXBUF REG 



'8: 



WUT 



TXSHF REG 



BAUD 
RATE 



16 BITS 



RXWAKE 



RX ERROR 



ERR 



FE 



OE 



PE 



55.7 55.4 55.3 55.2 



51.4 
CLOCK 



RXSHF REG 



/B 



RXENA X 51.0 



RXBUF REG 



57 



59 



SCI TX INT 



54.0 



TXRDY^ 



INT ENA 



54.7 



54.6 



TX EMPTY 



51.1 
-<yo- 



TX ENA 



SCI RX INT 

55.6 55.0 
— iRXRDYhf o^ 



55.5 



BRKDT 



INT ENA 



TXPRI 
c/ 



5F.6 



LEVEL 1 INT 



LEVEL 2 INT 



-O SCITXD PIN 



- g^ SCICLK PIN 



RXPR1 

o- 
o/ 



5F.5 



LEVEL 1 INT 



LEVEL 2 INT 



Figure 9-1. SCI Block Diagram 



9-3 



SCI Overvie\A^ 



9.1.2 SCI Features 

Features of the Serial Communications Interface (SCI) include the following: 

• Two Communications Formats 

- Asynchronous 

- Isosynchronous 

• Programmable Baud Rates 

- Asynchronous: 

A Range at 20 MHz - 3 Bps to 1 56K Bps 
▲ Number of Rates - 64K 

- Isosynchronous: 

A Range at 20 MHz - 39 Bps to 2.5M Bps 
A Number of Baud Rates - 64K 

• Programmable Data Word Length From 1 To 8 Bits 

• Programmable Stop Bits Of Either 1 Or 2 Bits In Length 

• Error Detection Flags: 

- Parity Error 

- Overrun Error 

- Framing Error 

- Break Detect 

• Two Wake- Up Multiprocessor Modes which may be used with either 
Communications Format. 

- Idle Line Wake-Up 
Address Bit Wake- Up 

• Full Duplex Operation 

• Separate Transmitter and Receiver Interrupts For Polled or Interrupt Dri- 
ven Operation 

• Double Buffered Receive and Transmit Functions 

• Separate Enable Bits for the Transmitter and Receiver. 

• NRZ (Non-Return-To-Zero) Format. 



9-4 



SCI Overview 



9.1.3 SCI Formats and Operation Modes 

The SCI may use one of two communication formats. Asynchronous or Iso- 
synchronous. These formats may be programmed to contain: 

O 1 start bit, 

O 1 to 8 data bits, 

• an even/odd parity bit or no parity bit, and 

• 1 or 2 stop bits. 

The SCI provides the following Universal Asynchronous Receiver/Transmitter 
(DART) communications formats for interfacing with many popular peripher- 
als: 

• Asynchronous Mode (discussed in Section 9.2.4.1, page 9-9) requires 
two lines to interface with many standard devices such as terminals and 
printers using RS-232-C formats. 

O Isosynchronous Mode (discussed in Section 9.2.4.2, page 9-10) permits 
high transmission rates and requires a synchronizing clock signal 
between the receiver and transmitter. 

The SCI also has two multiprocessor protocols, the idle Line Multiprocessor 
Mode (see Section 9.2.5.1) and the Address Bit Multiprocessor Mode (see 
Section 9.2.5.2). These protocols allow efficient data transfer between multi- 
ple processors, and may be used with either the Isosynchronous or standard 
Asynchronous formats. 

The SCI transmits and receives serial data, one bit at a time at a programmable 
baud rate. If the TMS370 operates at 20 MHz, the Baud rate for the Asyn- 
chronous mode would range from 3 bits-per-second to 156 kilobits-per- 
second, and for the Isosynchronous mode would range from 39 
bits-per-second to 2.5 megabits-per-second. 



9-5 



SCI Overview 



9.1.4 SCI Control Registers 



The SCI Control registers are located at addresses 1050h to 105Fh. 
function of each location is shown in Table 9-1 . 



The 



Table 9-1. SCI Memory Map 



Peripheral 

File 
Location 


Symbol 


Name 


P050 


SCiCCR 


SCI Communication Control Register 


P051 


SCICTL 


SCI Control Register 


P052 


BAUD MSB 


Baud Rate Select MSB 


P053 


BAUD LSB 


Baud Rate Select LSB 


P054 


TXCTL 


Transmitter Interrupt Control and Status Register 


P055 


RXCTL 


Receiver interrupt Control and Status Register 


P056 




Reserved 


P057 


RXBUF 


Receiver Data Buffer 


P058 




Reserved 


P059 


TXBUF 


Transmit Data Buffer 


P05A 
P05B 
P05C 




Reserved 


P05D 


SCIPC1 


Port Control 1 


P05E 


SCIPC2 


Port Control 2 


P05F 


SCIPRI 


Priority Control 



9-6 



SCI Operation 



9.2 SCI Operation 

The functions of the SCI are software configurable. A set of control words 
sent to the SCI initializes the desired communications format. These control 
words determine the: 

1 ) operating mode and protocol, 

2) baud rate, 

3) character length, 

4) even/odd parity or parity off, 

5) number of stop bits, and 

6) interrupt priorities and enables. 

9.2.1 SCI Programmable Data Format 

SCI data, both receive and transmit, is in NRZ (Non-Return to Zero) format. 
The data format consists of one Start bit, 1 to 8 data bits, an optional 
even/odd parity bit, and either 1 or 2 Stop bits, as illustrated in Figure 9-3 



START LSB 



MSB PARITY STOP 



IDLE LINE MODE 
(NORMAL NON-MULTIPROCESSOR COMMUNICATIONS) 



START LSB 



4 5 6 7 MSB Q°°5f PARITY STOP 



ADDRESS BIT MODE 

Figure 9-3. SCI Data Frame Formats 



9.2.2 SCI Port Interrupts 



The SCI provides independent interrupt requests and vectors for the receiver 
and transmitter. 

The receiver interrupt is asserted when the RXRDY (RXCTL.6) or BRKDT 
(TXCTL.5) flags are set, assuming the SCI RX INT ENA bit (RXCTL.O) is set. 
The transmitter interrupt is asserted when the TXRDY flag (TXCTL.7) is set, 
assuming the SCI TX INT ENA bit (TXCTL.O) is set. 

SCI Interrupts can be programmed onto different priority levels by the SCI RX 
PRIORITY (SCIPRI.5) and SCI TX PRIORITY (SCIPRI.6) control bits. When 
both RX and TX interrupt requests are made on the same level, the receiver 
always has higher priority than the transmitter to reduce the possibility of 
receiver overrun. 

An SCI TX interrupt is asserted whenever TXBUF is transferred to TXSHF. This 
interrupt indicates that the CPU can write to the TXBUF. 

An SCI RX interrupt is asserted whenever the SCI receives a complete frame 
(RXSHF transfers to RXBUF) or when a break detect condition occurs 
(SCIRXD is low for 10 bit periods following a stop bit). 



9-7 



SCI Operation 



9.2.3 SCI Clock Sources 



The SCI port can be driven by an internal or external baud rate generator. The 
CLOCK bit (SCICTL.4) configures the SCI clock source as either an input or 
an output. 

If an external clock source is selected (CLOCK = 0), and the SCICLK 
FUNCTION bit (SCIPC1.1) is set, then the SCICLK pin functions as the high 
impedance Serial Clock input pin. 

If an internal clock source is selected (CLOCK = 1), the SCICLK pin may be 
used as a general purpose I/O pin or as the Serial Clock output pin. If the 
Serial Clock output is selected, a 50 percent duty cycle clock signal is output 
on the SCICLK pin, which becomes a Serial Clock output pin. 

The internally generated serial clock is determined by the TMS370 CLKIN 
frequency and the Baud Rate Select Registers. The SCI uses the 16-bit value 
of the Baud Rate Select Registers to select one of 64K different serial clock 
rates for the communication modes in the following manner: 

Asynchronous Baud Rate = CLKIN / [(BAUD RATE REG + 1) * 128] 

and 

Isosynchronous Baud Rate = CLKIN / [(BAUD RATE REG + 1) * 8] 

and 

SCICLK frequency - CLKIN / [(BAUD RATE REG + 1 ) * 8] 

where, 

BAUD RATE REG - The 16-bit value in the Baud Rate Select Registers. 



Note: 

When an external serial clock signal is used, the maximum SCICLK fre- 
quency is CLKIN/1 6. 



The current logic level on the SCICLK pin can be determined by reading the 
SCICLK DATA IN bit (SCIPC1.3). 

The SCI receives data on rising clock edges and transmits data on falling clock 
edges. 



9-8 



SCI Operation 



9.2.4 SCI Communications Modes 

The SCIRX/SCITX (receiver/transmitter) has two operating modes, Asyn- 
chronous and Isosynchronous. The ASYNC/ISOSYNC bit (SCICCR.4) deter- 
mines the mode of operation. Either of these two modes can be used with 
either of the two forms of multiprocessor protocol. Idle Line and Address Bit. 

9.2.4.1 Asynchronous Communications Mode 

The SCI Asynchronous communication mode uses either single line (one way) 
or double line (two way) communications. In this mode, the frame consists 
of a start bit, one to eight data bits, an optional even/odd parity bit, and one 
or two stop bits. There are 1 6 SCICLK periods per data bit. 

The receiver begins operation on receipt of a valid start bit. A valid start bit 
consists of a negative edge followed by three samples, two of which MUST 
be zero. If two of the three samples are not zero, then the receiver continues 
to search for a start bit. These samples occur on the seventh, eighth, and ninth 
SCICLK periods after the negative edge. This sequence provides false start 
rejection and also locates the center of bits in the frame where the bits are read 
on a majority (two out of three) basis. Figure 9-4 illustrates the asynchronous 
communication format, with a start bit showing how edges are found and 
where a majority vote is taken. 

Since the receiver synchronizes itself to frames, the external transmitting and 
receiving devices do not have to use synchronized serial clocks; it may be 
generated locally. If the CLOCK (SCICTL.4) and SCICLK FUNCTION 
(SCIPC1 .1 ) bits are set, the serial clock function is output continuously on the 
SCICLK pin. 



FALLING \ / \ 

EDGE \ MAJORITY / \ MAJORITY 

DETECTED \ VOTE / \ VOTE / 



UUMMMMMMlMMUUMM^Mlfm 

I ! 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 
I I 



LS BIT OF DATA 



Figure 9-4. Asynchronous Communication Format 



9-9 



SCI Operation 



9.2.4.2 SCI Isosynchronous Communications Mode 

The SCI Isosynchronous communication mode uses either two line (one way) 
or three line (two way) communications. The extra line (Serial Clock) is 
required for data synchronization. In the Isosynchronous mode, each bit of 
data requires only one serial clock pulse for transmission or reception. Thus, 
the data bit period equals the SCICLK period, and data bits are read on a sin- 
gle sample basis. 

Since the receiver does not synchronize itself to data bits, the transmitter and 
receiver must be supplied with a common serial clock. If the internal serial 
clock is used it must be output continuously on the SCICLK pin. The arrival 
of a valid start bit, which consists of a low on the RXD line at the time of a 
rising SCICLK edge, initiates receiver operation. 

Figure 9-5 illustrates the Isosynchronous communication format. A complete 
frame consists of a start bit, one to eight data bits, an optional even/odd parity 
bit, and one or two stop bits. 



SCICLK 



TXD BIT OUT 



y^ BIT OUT )( BIT OUT )(( 



RXD )<>00000000000( BIT IN )000000000000Q< BIT IN 



Figure 9-5. Isosynchronous Communication Format 



9-10 



SCI Operation 



9.2.4.3 Receiver Signals in Communications Modes 

Figure 9-6 illustrates an example of receiver signal timing assuming the fol- 
lowing: 

1) Address bit wake-up mode 

2) 6 bits per character 

Lettered notes following the diagram are keyed to the letter labels in the dia- 
gram. 



J 



B 


















E 










SCIRXD 
PIN 

































STR 12 3 4 5 ADD PAR STP STR 1 2 



A. RX EIMA goes high to enable the receiver. 

B. Data arrives on the SCIRXD pin, start bit detected. 

C. RXRDY goes high to signal that a new character has been received, data is shifted to 

RXBUF, an interrupt is requested. 

D. The program reads the RXBUF register, RXRDY is automatically cleared. 

E. The next byte of data arrives on the SCIRXD pin; start bit detected, cleared. 

F. RX ENA goes low to disable the receiver. Data continues to be assembled in the RXSHF 

register but is not transferred to the RXBUF register. 



Figure 9-6. SCI RX Signals in Communication Modes 



9-11 



SCI Operation 



9.2.4.4 Transmitter Signals in Communications Modes 

Figure 9-6 illustrates an example of transmitter signal timing assuming the 
following: 

1 ) Address bit wake-up mode (address bit would not appear in Idle line 
mode) 

2) 3 bits per character 

Lettered notes following the diagram are keyed to the letter labels in the dia- 
gram. 



_f 



TX 
EMPTY 



u 



SCITXD 
PIN 



STR 1 2 AD PA ST 



STR 1 2 AD PA ST 



A. TX ENA goes high to enable the transmitter to send data. 

B. Write to TXBUF, TX is no longer empty. 

C. SCI transfers data to shift register; TX is ready for new character, requests an interrupt. 

D. Program writes new character to TXBUF after TXRDY goes high (item C). 

E. Finished transmitting first character; transfer new character to shift register. 

F. TX ENA goes low to disable transmitter; SCI finishes transmitting current character. 

G. Finished transmitting character; TX is empty and ready for new character. 

Figure 9-7. SCI TX Signals in Communications Modes 



9-12 



SCI Operation 



9.2.5 SCI Multiprocessor Communications 

The Multiprocessor Communication format allows one processor to efficiently 
send blocks of data to other processors on the same serial link. On one serial 
line there should be only one talker at a time. The first byte of a block of 
information contains an address byte which is read by all listeners. Only cor- 
rectly addressed listeners can be interrupted by the following data bytes. The 
listeners not addressed remain uninterrupted until the next address byte. 

The two different multiprocessor modes, supported by TMS370 devices, differ 
in how the processor recognizes an address byte. The Idle Line mode leaves 
a quiet space before the address byte. The Address Bit mode adds an extra 
bit into every byte to distinguish addresses from data. 

The multiprocessor mode is software selectable via the ADDRESS/IDLE WUP 
bit (SCICCR.3). Both formats use the TXWAKE and SLEEP flags to control 
the SCITX and SCIRX features of these modes. 

On the serial link, all processors set their SLEEP bit to 1 so that they are 
interrupted only when the address byte is detected. When a processor reads 
a block address which corresponds to the CPU's device address as set by 
software, the program must clear the SLEEP bit to enable the SCI to generate 
an interrupt on receipt of each data byte. 

Although the receiver still operates when the SLEEP bit is 1, it does not set 
RXRDY, RXINT, or the error status bits to 1 unless the address byte is detected 
and the address bit in the received frame is a 1 . The SCI does not alter the 
SLEEP bit; software must alter the SLEEP bit. 

In both multiprocessor modes the sequence is: 

1 ) The SCI port wakes up (requests an interrupt) at the start of a block and 
reads the first frame which contains the destination address. 

2) A software routine is entered through the interrupt and checks the 
incoming byte against its device address byte stored in memory. 

3) If the block is addressed to the microcomputer, the CPU clears the 
SLEEP bit and reads the rest of the block; iif not, the software routine 
exits with the SLEEP bit still set and does not receive SCI interrupts until 
the next block start. 

The Idle Line multiprocessor mode does not contain the extra address/data 
bit, and is more efficient than the Address Bit mode in handling blocks con- 
taining more than 10 bytes of data. 

The Address Bit mode is more efficient in handling many small blocks of data 
because it does not have to wait between blocks of data as does the Idle Line 
mode. However, at high transmit speeds, the program may not be quick 
enough to avoid a 10-bit idle in the transmission stream. 



9-13 



SCI Operation 



9.2.5.1 Idle Line Multiprocessor Mode 

In the Idle Line multiprocessor protocol, blocks are separated by having a 
longer idle time between the blocks than between frames in the blocks. An 
idle time of 10 or more bits after a frame indicates the start of a new block. 
The Idle Line multiprocessor communication format is shown in Figure 9-8. 



RXD/TXD 



■BLOCKS OF FRAMES - 



-IDLE PERIODS OF 10 BITS OR MORE- 



RXD/TXD I 
EXPANDED [ 



ST 



ADDR 



SP 



FIRST FRAME WITHIN 

BLOCK IS ADDRESS, 

IT FOLLOWS IDLE 

PERIOD OF 10 BITS 

OR MORE 



ST 



DATA 



SP 



ST 



LAST DATA 



SP 



FRAME WITHIN 
BLOCK 



IDLE PERIOD 

LESS THAN 10 

BITS 



IDLE PERIOD 

GREATER 
THAN 10 BITS 



Figure 9-8. Idle Line Multiprocessor Communication Format 



The SCI wakes up after the block start signal. The processor now recognizes 
the next SCI interrupt. The service routine then receives the address sent by 
a remote transmitter and compares this address to its own. If the CPU is 
addressed, the service routine clears the SLEEP bit, and receives the rest of the 
data block. If the CPU is not addressed, the SLEEP bit is left set. This lets the 
CPU continue to execute its main program without being interrupted by the 
SCI port. 

There are two ways to send a block start signal. 

1 ) The first method is to deliberately leave an idle time of 10 bits or more 
by delaying the time between the transmission of the last frame of data 
in the previous block and the address frame of the new block. 

2) In the second method, the SCI port uses the TXWAKE bit to send an idle 
time of exactly 1 1 bits. Therefore, the serial communications line is not 
idle any longer than necessary. 

Associated with the TXWAKE bit is the wake-up temporary (WUT) flag. WUT 
is an internal flag, double buffered with TXWAKE. When TXSHF is loaded 
from TXBUF, WUT is loaded from TXWAKE, and TXWAKE is reset to 0. This 
arrangement is shown in Figure 9-9. 



9-14 



SCI Operation 




Figure 9-9. Double-Buffered WUT and TXSHF 

To send out a block start signal of exactly one frame time: 

1 ) Write a 1 to the TXWAKE bit. 

2) Write a data word (don't care) to TXBUF. (The first data word written 
is suppressed while the block start signal is sent out, and ignored after 
that.) 

When TXSHF is free again, TXBUF's contents are shifted to TXSHF, the 
TXWAKE value is shifted to WUT, and then TXWAKE is cleared. 

If TXWAKE was set to a 1 , the start, data, and parity bits are replaced 
by an idle period of 1 1 bits transmitted following the last stop bit of the 
previous frame. 

3) Write an address value to the TXBUF. 

Writing the first "don't care" data word to the TXBUF is necessary so the 
TXWAKE bit value can be shifted to WUT. After the "don't-care" data word 
is shifted to the TXSHF, the TXBUF (and TXWAKE if necessary) may be 
written to again, since WUT and TXSHF are both double-buffered. 

The receiver operates regardless of the SLEEP bit. The receiver does not set 
RXRDY, RXINT, or the error status bits until an address frame is detected. 

9.2.5.2 Address Bit IVIu It i processor Mode 

In the Address Bit protocol, the frame has an extra bit called an address bit 
immediately after the last data bit. The first frame in the block has the address 
bit set to 1 , and all other frames have the address bit set to 0. The idle period 
timing is irrelevant. 

The TXWAKE bit sets the address bit. In SCITX, when the TXBUF and 
TXWAKE are loaded into TXSHF and WUT, TXWAKE is reset to and WUT 
is the value of the address bit of the current frame. Thus, to send an address, 
set the TXWAKE bit to a 1, and write the appropriate address value to the 
TXBUF. When this address value is transferred to TXSHF and shifted out, its 
address bit is sent as a 1, which flags the other processors on the serial link 
to read the address. Since TXSHF and WUT are both double-buffered, TXBUF 
and TXWAKE may be written to immediately after TXSHF and WUT are 
loaded. To transmit non-address frames in the block, the TXWAKE bit is left 
atO. 



9-15 



SCI Operation 



RXD/TXD 



■BLOCKS OF FRAMES- 



■IDLE PERIOD OF NO SIGNIFICANCE 



ni F PFRinn np wn RiRNiiFirAWPF 1 1 



RXD/TXD Un 
EXPANDED E: 



ADDR 



SP 



ST 



FIRST FRAME WITHIN 

BLOCK IS ADDRESS 

THE ADDR/DATA BIT IS 1 



DATA 



SP 



ST 



ADDR/DATA BIT "-^ 
IS FOR FRAME 
WITHIN BLOCK 

IDLE TIME IS OF 
NO SIGNIFICANCE 



DATA 



SP 



Figure 9-10. Address Bit Multiprocessor Communication Format 



9.2.6 SCI Initialization Examples 

This section contains four examples that initialize the serial port. In each case 
the data is moved to and from the buffers in the interrupt routines. 

• The first example shows a typical RS-232 application that connects to 
a terminal. 

• The second example illustrates the Address Bit mode in a multiprocessor 
application. 

In all examples, assume the register mnemonics have been equated (EQU) 
with the corresponding Peripheral-File location. 



9-16 



SCI Operation 



9.2.6.1 RS-232-C Example 



This example initializes the transmitter and receiver to accept data at 9600 
baud with a format of 8 data bits, 1 stop bit, and even parity. 



B9600 



,EQU 15 



AND #01Fh,SCICTL 



MOV 


#000h,SCIPRI 


MOV 


#005h,SCIPCl 


MOV 


#022h,SCIPC2 


MOV 


#Hi B9600,BAUDMSB 


MOV 


#Lo B9600,BAUDLSB 


MOV 


#077h,SCICCR 


MOV 


#033h,SCICTL 


MOV 


#001h,TXCTL 


MOV 


#001h,RXCTL- 


EINT 




MOV 


#00,TXBUF 



Value for counter for 9600 baud 
value = (CLKIN/128/baud rate) - 1 = 
(20 MHz/128/9600) - 1 = 15.27 ~ 15 
1.8 percent error 

Make sure that SCI SW RESET bit is 
clear before writing to the SCI 
configuration registers 

Set TX and RX to high priority 

Set SCLK for general purpose output 

Set pins for RXD and TXD functions 

Set baud rate for 9600 (MSB) 

Set baud rate for 9600 (LSB) 

1 stop bit, even parity, 

and 8 data bits/char 

Enable Rx, Tx, clock is internal 

Enable TX interrupt 

Enable RX interrupt 

Let the interrupts begin 

Start transmitter by sending null 
character 



9-17 



SCI Operation 



9.2.6.2 RS-232-C Multiprocessor Mode Example 

This example initializes the transmitter and receiver to accept data at 9600 
baud with a format of 8 data bits, 1 stop bit, and even parity. It uses the 
address bit wake-up mode to implement the multiprocessor protocol. 



B9600 .EQU 15 



MOV #000h,SCIPRI 

MOV #005h,SCIPCl 

MOV #022h,SCIPC2 

MOV #Hi B9600,BAUDMSB 

MOV #Lo B9600,BAUDLSB 

MOV #077h,SCICCR 

MOV #037h,SCICTL 

MOV #001h,TXCTL 

MOV #001h,RXCTL 
EINT 



SENDADD OR #8,SCICTL 

MOV ADDR,TXBUF 
RTS 



SENDATA PUSH A 

MOV OUTDATA , TXBUF 



POP A 
RTI 

GETDATA PUSH A 

BTJZ #2,RXCTL,ISDATA 
MOV RXBUF,A 

CMP #MYADDR,A 

JNE RXEXIT 

AND #0F7h,SCICTL 
JMP RXEXIT 

ISDATA MOV RXBUF,INDATA 



RXEXIT POP A 
RTI 



Value for counter for 9600 baud 

value=(CLKIN/128/baud rate) - 1 = 

(20 MHz/128/9600) - 1 = 15.27 ~ 15 

1.8 percent error 

Set TX and RX to high priority 

Set SCLK for general purpose output 

Set pins for RXD and TXD functions 

Set baud rate for 9600 (MSB) 

Set baud rate for 9600 (LSB) 

1 stop bit, even parity, 

and 8 data bits/char 

Enable Rx, Tx; RX to sleep, 

clock is internal 

Enable TX interrupt 

Enable RX interrupt 

Let the interrupts begin 

MAIN ROUTINES 

Main line routine; set TXWAKE 

wake bit 

Transmit address stored in ADDR 



INTERRUPT ROUTINES 

Address has already been sent by 
the SENDADD 

Output character that is 
stored in DATA 

Other transmitter code 

Restore and exit 

Receive a new character 

Is this address or data byte? 

Get new character and clear 

interrupt flag 

Is this my address or 

another processor's address 

Exit if another's; 'still 

in sleep mode 

If my address get out of sleep mode 

Exit and wait for data 

Put incoming data in register 

Other receiver code 

Restore and exit 



9-18 



SCI Control Registers 



9.3 SCI Control Registers 

The SCI is controlled and accessed through registers in the Peripheral File. 
These registers are listed in Table 9-1 and described in the following sections. 
The bits shown in shaded boxes in Table 9-1 are Privilege Mode bits, that is, 
they can only be written to in the Privilege Mode. 

Table 9-1 . SCI Control Registers 

PERIPHERAL FILE FRAME 5: SERIAL COMMUNICATION INTERFACE (SCI) CONTROL REGISTERS 



ADDR 
1050h 

1051h 

1052h 
1053h 

1054h 

1055h 

1056h 
105711 
1058h 

losgh 

105Ah 
105Bh 
105Ch 

105Dh 
105Eh 
105Fh 



PF 


BIT 7 


BIT 6 


BIT 5 


BIT 4 


BITS 


BIT 2 


BIT 1 


BITO 


050 


STOP 
BITS 


EVEN/ODD 
PARITY 


PARITY 
ENABLE 


ASYNC/ 
ISOSYNC 


ADDRESS/ 
IDLE WUP 


SCI 
CHAR2 


SCI 
CHAR1 


SCI 
CHARO 


051 








SCI 
SW RESET 


CLOCK 


TXWAKE 


SLEEP 


TXENA 


RXENA 


052 


BIT 15 BAUD RATE SELECT REGISTER MSB BIT 8 


053 


BIT 7 BAUD RATE SELECT REGISTER LSB BIT 


054 


TXRDY 


TX EMPIY 

















SCI TX 
INT ENA 


055 


RX 
ERROR 


RXRDY 


BRKDT 


FE 


OE 


PE 


RX 
WAKE 


SCI RX 
INT ENA 


056 


RESERVED 


057 


RECEIVE DATA BUFFER REGISTER 


058 


RESERVED 


059 


TRANSMIT DATA BUFFER REGISTER 


ObA 
05B 
05C 


RESERVED 


05D 














SCICLK 
DATA IN 


SCICLK 
DATA OUT 


SCICLK 
FUNCTION 


SCICLK 
DATA DIR 


05E 


SCI TXD 
DATA IN 


SCI TXD 
DATA OUT 


SCI TXD 
FUNCTION 


SCI TXD 
DATA DIR 


SCI RXD 
DATA IN 


SCI RXD 
DATA OUT 


SCI RXD 
FUNCTION 


SCI RXD 
DATA DIR 


05F 


SCi 

BTEST 


SCITX 

pRioRrrY 


SCIRX 

PRIORITY 


SCi 
ESPEN 















SCICCR 

SCICTL 

BAUD MSB 
BAUD LSB 

TXCTL 
RXCTL 

RXBUF 
TXBUF 

SCiPCI 
SCIPC2 
SCIPRI 



9-19 



SCI Control Registers 



9.3.1 Communication Control Register (SCICCR) 

The SCICC Register defines the character format, protocol, and communi- 
cations mode used by the SCI. 

SCI Communication Control Register (SCICCR) 
[Memory Address - 1050h] 

Bit #-7 6 5 4 3 2 1 

P050 





EVEN/ 






ADDRESS 








STOP 


ODD 


PARITY 


ASYNC/ 


IDLE 


SCI 


SCI 


SCI 


BITS 


PARITY 


ENABLE 


ISOSYNC 


WUP 


CHAR2 


CHAR1 


CHARO 



RW-0 



Bits 0-2 



RW-0 RW-0 RW-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET 



RW-0 RW-0 



SCI CHARO-2. SCI Character Length Control Bits 0-2. 
These bits select the SCI character length, from 1 to 8 bits. Characters of less 
than 8 bits are right-justified in RXBUF and TXBUF, and are padded with 
leading Os in RXBUF. TXBUF need not be padded with leading zeros. 



Table 9-2. Transmitter Character Bit Length 



SCI 
CHAR2 


SCI 
CHAR1 


SCI 
CHARO 


CHARACTER 
LENGTH 











1 








1 


2 





1 





3 





1 


1 


4 


1 








5 


1 





1 


6 


1 


1 





7 


1 


1 


1 


8 



Bit 3 - ADDRESS/IDLE WUP. SCI Multiprocessor Mode Control Bit. 
This bit selects one of the multiprocessor protocols. 

= Idle Line Mode protocol selected. 

1 = Address Bit Mode protocol selected. 

The Idle Line Mode is usually used for normal communications because the 
Address Bit Mode adds an extra bit to the frame. The Idle Line Mode does not 
add this extra bit and is compatible with RS-232-type communications. 
Multiprocessor communication is different from the other communication 
modes because it uses TXWAKE and SLEEP functions. 

Bit 4 - ASYNC/ISOSYIMC. SCI Communications Mode Control Bit. 
This bit determines the SCI communications mode. 

= Selects Isosynchronous mode (described in Section 9.2.4.2). In this mode, 

the bit period is equal to the SCICLK period; bits are read on a single 
sample basis. 

1 = Selects Asynchronous mode (described in Section 9.2.4.1). In this mode 

the bit period is 16 times the SCICLK period; bits are read on a two out 
of three majority basis. 



9-20 



SCI Control Registers 



Bit 5 - PARITY ENABLE. SCI Parity Enable. 

This bit enables or disables the parity function. When parity is enabled during 
the Address Bit multiprocessor mode, the address bit is included in the parity 
calculation. 

= Parity disabled. No parity bit is generated during transmission or expected 

during reception. 

1 = Parity enabled. 

Bit 6 - EVEN/ODD PARITY. SCI Parity Odd/Even. 

If the PARITY ENABLE (SCICCR.5) is set, then this bit selects odd or even 
parity (odd or even number of 1 bits in both transmitted and received charac- 
ters). 

= Sets odd parity. 

1 = Sets even parity. 

Bit 7 - STOP BITS. SCI Number of Stop Bits. 

This bit determines the number of stop bits transmitted. The receiver checks for 
one stop bit only. 



= One stop bit. 

1 = Two stop bits. 



9-21 



SCI Control Registers 



9.3.2 Control Register (SCICTL) 



The SCICTL register controls the RX/TX enable, TXWAKE and SLEEP func- 
tions, internal clock enable, and the SCI software Reset. 

SCI Control Register (SCICTL) 
[Memory - 1051 h] 



Bit#- 



P051 



7 


6 


5 


4 


3 


2 


1 





— 


— 


SCI 

SW 

RESET 


CLOCK 


TXWAKE 


SLEEP 


TXENA 


RXENA 



RW-0 RW-0 



RS-0 RW-0 RW-0 



RW-0 



R = Read, W=Write, S=Set only, -n= Value after RESET 

Bit - RXENA. SCI Receive Enable. 

When this bit is set, received characters are transferred into RXBUF and the 
RXRDY flag is set. When cleared, this bit prevents received characters from 
being transferred into the receiver buffer (RXBUF); and no receiver interrupts 
are generated. However, the receiver shift register continues to assemble char- 
acters. Thus, if RXENA is set during the reception of a character, the complete 
character is transferred into RXBUF. 

= SCI Receiver disabled. 

1 = SCI Receiver enabled. 

Bit 1 - TXENA. SCI Transmit Enable. 

Data transmission through the SCITXD pin occurs only when this bit is set. If 
this bit is reset, the transmission is not halted until all the data previously 
written to TXBUF has been sent. 

= SCI Transmitter disabled. 

1 = SCI Transmitter enable. 

Bit 2 - SLEEP. SCI Sleep. 

This bit controls the receive features of the multiprocessor communication 
modes. This bit must be cleared by the user to bring the SCI out of Sleep mode. 

= Sleep mode disabled. 

1 = Sleep mode enabled. 

Bit 3 - TXWAKE. SCI Transmitter Wake-up. 

The TXWAKE bit controls the transmit features of the multiprocessor commu- 
nication modes. This bit is cleared only by System RESET. The SCI hardware 
clears this bit once it has been transferred to Wake Up Temporary (WUT). 

Bit 4 - CLOCK. SCI Internal Clock Enable. 

This bit determines the source of the SCICLK. Clearing this bit selects an 
external SCICLK, which is input on the high impedance SCICLK line and 
bypasses the baud rate generator. For Isosynchronous transactions, one bit is 
transmitted or received per SCICLK period. For Asynchronous transactions, one 
bit is transmitted or received per 16 SCICLK periods. The maximum frequency 
for the externally sourced SCICLK is CLKIN/16. Setting this bit selects an 
internal SCICLK, derived from the baud rate generator. This signal can be 
output on the SCICLK line. 

= External SCICLK. 

1 = Internal SCICLK. 



9-22 



SCI Control Registers 



Bit 5 - SCI SW RESET. SCI Software Reset (Active Low). 

Writing a to this bit initializes the SCI state machines and operating flags to 
the reset condition. The CLOCK bit retains its state prior to the assertion of SCI 
SW RESET. If SCICLK is configured as an output, then the SCICLK resets (low 
level). All effected logic is held in the reset state until a 1 is written to the SCI 
SW RESET bit. Thus, after a System RESET, the SCI must be re-enabled by 
writing a 1 to this bit. 



Note: 

The SCI SW RESET bit must be cleared before the SCI configuration 
registers can be set up or altered. All configuration registers should be set 
up by the application program prior to setting SCI SW RESET. 



Bits 6,7 -Reserved. Read data is indeterminate. 



9-23 



SCI Control Registers 



9.3.3 Baud Select Registers (BAUD MSB and BAUD LSB) 

The BAUD MSB and BAUD LSB registers store the data required to generate 
the baud rate. The SCI uses the combined 16-bit value, BAUD RATE REG, 
of the baud select registers to set the SCI clock frequency as follows: 

SCICLK frequency = CLKIN / [(BAUD RATE REG + 1 ) * 8] 

where, 

BAUD RATE REG = The 16 bit value in the Baud Rate Select Registers. 

For example, if the CLKIN frequency is 20 MHz, then the maximum internal 
SCICLK frequency would be [20 MHz / 8], or 2.5 MHz. 

For Asynchronous mode communication, data is transmitted and received at 
the rate of one bit for each 16 SCICLK periods. For Isosynchronous mode 
communication, data is transmitted and received at the rate of one bit for each 
SCICLK period. The Asynchronous and Isosynchronous Baud Rates are cal- 
culated as follows: 

Asynchronous Baud Rate = CLKIN / [(BAUD RATE REG + 1)* 128] 

Isosynchronous Baud Rate = CLKIN / [(BAUD RATE REG + 1)* 8] 



Bit#- 



P052 



RW-0 



Baud Rate Select MSB Register (BAUD MSB) 
[ Memory address - 1052h] 



7 


6 


5 


4 


3 


2 


1 





BAUDF 
(msb) 


BAUDE 


BAUDD 


BAUDC 


BAUDB 


BAUDA 


BAUDS 


BAUDS 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



Bit# 



P053 



Baud Rate Select LSB Register (BAUD LSB) 
[Memory address - 1053h] 



7 


6 


5 


4 


3 


2 


1 





BAUD? 


BAUD6 


BAUDS 


BAUD4 


BAUDS 


BAUD2 


BAUD1 


BAUDO 
(Isb) 



RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET 



9-24 



SCI Control Registers 



9.3.4 Transmitter Interrupt Control and Status Register (TXCTL) 

The TXCTL Register contains the Transmitter Interrupt Enable, the Transmitter 
Ready flag, and the Transmitter Empty flag. The status flags are updated each 
time a complete character is transmitted. A summary of the register functions 
and bit assignments is shown below. 



Bit# 



P054 



Transmitter Interrupt Control and Status Register (TXCTL) 
[Memory address - 1054h] 



7 


6 


5 


4 


3 


2 


1 





TXRDY 


TX 

EMPTY 


— 


— 


— 


— 


— 


SCITX 
INT 
ENA 



R-1 



R-1 



RW-0 



R = Read, W=Write, -n= Value after RESET 



Bit - SCI TX INT ENA. SCI Transmitter Ready Interrupt Enable. 

This bit controls the ability of the TXRDY bit to request an interrupt, but does 
not prevent the TXRDY bit from being set. The SCI TX INT ENA bit is set to 
by an SCI SW RESET or a system RESET. 

= SCI TXRDY interrupt disabled. 

1 = SCI TXRDY interrupt enabled. 

Bits 1 -5 - Reserved. Read data is indeterminate. 

Bit 6 - TX EMPTY. SCI Transmitter Empty. 

This bit indicates the status of the transmitter-shift register and the TXBUF 
register. TX EMPTY is set to 1 by a SCI SW RESET or a System RESET. 

= the CPU has written data to the TXBUF register, the data has not been 

completely transmitted. 

1 = TXBUF and TXSHF register empty. 

Bit 7 - TXRDY. SCI Transmitter Ready. 

The TXRDY bit is set by the transmitter to indicate that TXBUF is ready to 
receive another character. The bit is automatically cleared when a character is 
loaded into TXBUF. This flag asserts a transmitter interrupt if the interrupt 
enable bit SCI TX INT ENA (TXCTL.O) is set. TXRDY is a read-only flag. It is 
set to 1 by an SCI SW RESET or a system reset. 

= TXBUF is full. 

1 = TXBUF is ready to receive character. 



9-25 



SCI Control Registers 



9.3.5 Receiver Interrupt Control and Status Register (RXCTL) 

The RXCTL register contains one interrupt enable bit and seven receiver status 
flags (two of which can generate interrupt requests). The status flags are 
updated each time a complete character is transferred to the RXBUF. They are 
cleared each time RXBUF is read. 



Bit#- 



P055 



SCI Receiver interrupt Control and Status Register (RXCTL) 
[Memory address - 1055h] 



7 


6 


5 


4 


3 


2 


1 





RX 
ERROR 


RXRDY 


BRKDT 


FE 


OE 


PE 


RXWAKE 


SCI 
RX 

INT ENA 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



RW-0 



R=Read, W=Write, -n= Value after RESET 

Bit - SCI RX INT EIMA. SCI Receiver Interrupt Enable. 

The SCI RX INT ENA bit controls the ability of the RXRDY and the BRKDT bits 
to request an interrupt, but does not prevent these flags from being set. 

= RXRDY/BRKDT interrupt disabled. 

1 = RXRDY/BRKDT interrupt enabled. 

Bit 1 - RXWAKE. Receiver Wakeup Detect. 

The SCI sets this bit when a receiver wakeup condition is detected. In the 
Address Bit multiprocessor mode, RXWAKE reflects the value of the address 
bit for the character contained in RXBUF. In the Idle line multiprocessor mode 
RXWAKE is set if an idle SCI RXD line is detected. RXWAKE is a read-only flag. 
It is cleared by transfer of the first byte after the address byte to RXBUF, by 
reading the address character in RXBUF, by an SCI RX RESET, or by a system 
Reset. See Section 9.2.5. 

Bit 2 - PE. SCI Parity Error Flag. 

This flag bit is set when a character is received with a mismatch between the 
number of 1s and its parity bit. The parity checker includes the address bit in 
the calculation. If Parity generation and detection is not enabled, the PE flag 
is disabled and read as 0. The PE bit is reset by an SCI SW RESET, a system 
reset, or by reading RXBUF. 

= No Parity error or Parity is disabled. 

1 = Parity error detected. 

Bit 3 - OE. SCI Overrun Error Flag. 

The SCI sets this bit when a character is transferred into RXBUF before the 
previous character has been read out. The previous character is overwritten and 
lost. The OE flag is reset by an SCI SW RESET, a system reset, or reading 
RXBUF. 

= No Overrun error detected. 

1 = Overrun error detected. 

Bit 4 - FE. SCI Framing Error Flag. 

The SCI sets this bit when a stop bit is not found when expected. Only the first 
stop bit is checked. The missing stop bit indicates that synchronization with 
the start bit has been lost and the character is incorrectly framed. It is reset 
by an SCI SW RESET, a system reset, or by reading RXBUF. 

= No Framing error detected. 

1 = Framing error detected. 



9-26 



SCI Control Registers 



Bit 5 - BRKDT. SCI Break Detect Flag. 

The SCI sets this bit when a break condition occurs. A break condition occurs 
when the SCIRXD line remains continuously low for at least 10 bits beginning 
after a missing first stop bit. The occurrence of a break causes a receiver inter- 
rupt to be generated if the SCI RX INT ENA bit is a 1, but it does not cause the 
receiver buffer to be loaded. A BRKDT interrupt can occur even if the receiver 
SLEEP bit is set to 1. BRKDT is cleared by reading RXBUF, by an SCI SW 
RESET, or by a system reset. It is not cleared by receipt of a character after the 
break is detected. 

Bit 6 - RXRDY. SCI Receiver Ready. 

The receiver sets this bit to indicate that RXBUF is ready with a new character, 
and clears the bit when the character is read. A receiver interrupt is generated 
if the SCI RX INT ENA bit is a '1'. RXRDY is reset by an SCI SW RESET or a 
system reset. 

Bit 7 - RX ERROR. SCI Receiver Error Flag. 

The RX ERROR Flag indicates that one of the error flags in the receiver status 
register is set. It is a logical "or" of the parity, overrun, framing error, and break 
detect flags. The bit can be used for fast error condition checking during the 
interrupt service routine since a negative value of the status register indicates 
that an error condition has occurred. This error flag cannot be cleared directly, 
but is cleared if no individual error flags are set. This bit is cleared by an SCI 
SW RESET, a system reset, or reading RXBUF. 



9-27 



SCI Control Registers 



9.3.6 Receiver Data Buffer Register (RXBUF) 

The RXBUF register contains current data from the receiver shift register. 
RXBUF is cleared by system reset. 

Receiver Data Buffer Register (RXBUF) 
[Memory address - 1057h] 

Bit#- 
P057 



7 


6 


5 


4 


3 


2 


1 





RXDT7 


RXDT6 


RXDT5 


RXDT4 


RXDT3 


RXDT2 


RXDT1 


RXDTO 



R-0 R-0 R-0 R-0 R-0 R-0 

R = Read, -n= Value after RESET 



R-0 



R-0 



9.3.7 Transmit Data Buffer Register (TXBUF) 

The TXBUF register is a read/write register used to store data bits to be 
transmitted by SCITX. Data written to TXBUF must be right justified because 
the left-most bits are ignored for characters less than eight bits long. 



Transmit Data Buffer Register (TXBUF) 
[Memory address - 1059h] 



Bit # - 



P059 



7 


6 


5 


4 


3 


2 


1 





TXDT7 


TXDT6 


TXDT5 


TXDT4 


TXDT3 


TXDT2 


TXDT1 


TXDTO 



RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET 



RW-0 



9-28 



SCI Control Registers 



7 


6 


5 


4 


3 


2 


1 





— 


— 


— 


— 


SCICLK 
DATA 

IN 


SCICLK 
DATA 
OUT 


SCICLK 
FUNCTION 


SCICLK 

DATA 

DIR 



9.3.8 Port Control Register 1 (SCIPC1) 

The SCIPC1 register controls the SCICLK pin functions. 

SCI Port Control Register 1 (SCIPC1) 
[Memory address - 105D] 

Bit#- 
P05D 

R-0 RW-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET 

Bit - SCICLK DATA DIR. SCICLK Data Direction. 

This bit determines the data direction on the SCICLK pin if SCICLK has been 
configured as a general purpose I/O pin. 

= SCICLK pin is a general purpose INPUT port. 

1 = SCICLK pin is a general purpose OUTPUT port. 

Bit 1 - SCICLK FUIMCTIGN. 

This bit defines the function of the SCICLK pin. 

= SCICLK pin is a general purpose digital I/O port. 

1 = SCICLK pin is the SCI serial clock pin. 

Bit 2 - SCICLK DATA OUT. 

This bit contains the data to be output on the SCICLK pin if the following 
conditions are met: 

a. SCICLK pin is configured as general purpose I/O. 

b. SCICLK pin data direction is defined as output. 



Bits 

Bits 4-7 - Reserved. Read data is indeterminate 



SCICLK DATA IN. 

The SCICLK DATA IN bit contains the current value on the SCICLK pin. 



9-29 



SCI Control Registers 



9.3.9 Port Control Register 2 (SCIPC2) 

The SCIPC2 register controls the SCIRXD and SCITXD pin functions. 

SCI Port Control Register 2 (SCIPC2) 
[Memory address - 105E] 



Blt#- 


7 


6 


5 


4 


3 


2 


1 





P05E 


SCITXD 

DATA 

IN 


SCITXD 
DATA 
OUT 


SCITXD 
FUNCTION 


SCITXD 

DATA 

DIP 


SCIRXD 

DATA 

IN 


SCIRXD 
DATA 
OUT 


SCIRXD 
FUNCTION 


SCIRXD 

DATA 

DIR 




R-0 


RW-0 


RW-0 RW-0 

R=Read, W=Write, 


R-0 

n= Value i 


RW-0 RW-0 

after RESET 


RW-0 



Bit - SCIRXD DATA DIR. SCIRXD Data Direction 

This bit determines the data direction on the SCIRXD pin if SCIRXD has been 
defined as a general purpose I/O pin. 

= SCIRXD pin is a general purpose INPUT port. 

1 = SCIRXD pin is a general purpose OUTPUT port. 

Bit 1 - SCIRXD FUNCTION. 

This bit defines the function of the SCIRXD pin. 

= SCIRXD pin is a general purpose digital I/O port. 

1 = SCIRXD pin is the SCI Receiver pin. 

Bit 2- SCIRXD DATA OUT. 

This bit contains the data to be output on the SCIRXD pin if the following 
conditions are met: 

a. SCIRXD pin has been defined as a general purpose I/O pin. 

b. SCIRXD pin data direction has been defined as output. 

Bit 3 - SCIRXD DATA IN. 

This bit contains the current value on the SCIRXD pin. 

Bit 4- SCITXD DATA DIR.SCITXD Data Direction. 

This bit determines the data direction on the SCITXD pin if SCITXD has been 
defined as a general purpose I/O pin. 

= SCITXD pin is a general purpose INPUT port. 

1 = SCITXD pin is a general purpose OUTPUT port. 

Bit 5 - SCITXD FUNCTION. 

This bit defines the function of the SCITXD pin. 

= SCITXD pin is a general purpose digital I/O port. 

1 = SCITXD pin is the SCI Transmit pin. 

Bit 6 - SCITXD DATA OUT. 

This bit contains the data to be output on the SCITXD pin if the following 
conditions are met: 

a. SCITXD pin data direction is defined as output. 

b. SCITXD pin is configured as general purpose I/O. 

Bit 7 - SCITXD DATA IN. 

This bit contains the current value on the SCITXD pin. 



9-30 



SCI Control Registers 



9.3.10 Priority Control Register (SCIPRI) 

The SCIPRI register contains the Receiver and Transmitter Interrupt Priority 
Select bits. This register is read-only during normal operation, but can be 
written to in the privileged mode. 

SCI Priority Control Register (SCIPRI) 
[Memory address - 105F] 



Bit# 



P05F 



7 


6 


5 


4 


3 


2 


1 





SCI 
STEST 


SCITX 
PRIORITY 


SCIRX 
PRIORITY 


SCI 
ESPEN 


— 


— 


— 


— 



RP-0 



RP-0 



RP-0 



RP-0 



R=Read, P=Privileged State write only, -n= Value after RESET 

Bits 0-3 - Reserved. Read values are indeterminate. 

Bit 4- SCI ESPEN. SCI Emulator Suspend Enable. 

This bit has no effect except when using the XDS emulator to debug a program. 
Then, this bit determines how the SCI operates when the program is suspended 
by an action such as a hardware or software breakpoint. 

= When the emulator is suspended, the SCI continues to work until the 

current transmit or receive sequence is complete. 

1 = When the emulator is suspended, the SCI state machine is frozen so that 

the state of the SCI can be examined at the point that the emulator was 
suspended. 

Bit 5 - SCI RX PRIORITY. SCI Receiver Interrupt Priority Select. 

This bit assigns the interrupt priority level of the SCI receiver interrupts. 

= Receiver Interrupts are Level 1 (high priority) requests. 

1 = Receiver Interrupts are Level 2 (low priority) requests. 

Bit 6 - SCI TX PRIORITY. SCI Transmitter Interrupt Priority Select. 

This bit assigns the interrupt priority level of the SCI transmitter interrupts. 

- Transmitter Interrupts are Level 1 (high priority) requests. 

1 = Transmitter Interrupts are Level 2 (low priority) requests. 

Bit 7 - SCI STEST; 

This bit must be cleared (0) to ensure proper operation. 



9-31 



SCI Control Registers 



9-32 



Introduction 



TMS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module [mO 

"IE: 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module m* 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information HOE 



Appendixes 



10. Serial Peripheral Interface (SPI) Module 

This section discusses the architecture and programming of the Serial Periph- 
eral Interface module on TMS370 devices. 

This section covers the following topics: 

Section Page 

10.1 Serial Peripheral Interface (SPI) Module Overview 10-2 

10.1.1 Physical Description 10-2 

10.1.2 SPI Control Registers 10-4 

10.2 SPI Operation 10-5 

10.2.1 SPI Data Format 10-6 

10.2.2 SPI Interrupts 10-6 

10.2.3 SPI Clock Sources 10-7 

10.2.4 SPI Operation Modes 10-7 

1 0.2.5 Initialization 1 0-8 

'10.2.6 SPI Example 10-9 

10.3 SPI Control Registers 10-10 

10.3.1 SPI Configuration Control Register 10-11 

10.3.2 SPI Operation Control Register 10-13 

10.3.3 Serial Input Buffer (SPIBUF) 10-14 

10.3.4 Serial Data Register (SPIDAT) 10-14 

10.3.5 Port Control Registers 10-15 

10.3.6 SPI Interrupt Priority Control Register (SPIPRI) 10-17 



10-1 



Serial Peripheral Interface (SPI) Module Overview 



10.1 Serial Peripheral Interface (SPI) Module Overview 

The SPI module is a high-speed synchronous serial I/O port that allows a 
serial bit stream of programmed length (one to eight bits) to be shifted into 
and out of the device at a programmed bit transfer rate. The SPI is normally 
used for communications between the microcontroller and external peripherals 
or another microcontroller. Typical applications include external I/O or 
peripheral expansion using devices such as shift registers, display drivers, A/D 
converters, etc. Multiprocessor communications are also supported by the 
master/slave operation of the SPI. 

10.1.1 Physical Description 

The SPI module, as shown in Figure A-10, consists of: 

• Three I/O pins: 

SPISIMO - SPI Slave In, Master Out. 
SPISOMI - SPI Slave Out, Master In 
SPICLK - SPI CLOCK 

• SPIBUF - SPI Buffer register 

• SPI DAT - SPI Data Shift register 

• State Control logic 

• SPI Control registers located at P030-P03F 



10-2 



Serial Peripheral Interface (SPI) Module Overview 



37 



SPIBUF BUFFER 
REGISTER 8 



39 






SPIDAT 
DATA REGISTER 



STATE CONTROL 



BITS/CHAR 



30. 



SYS 

CLOCK" 



CLOCK RATE 



30. 



OVERRUN 31.7 



SPI INTERRUPT 



FLAG 



31.6 



31.1 
TALK 



-cxo- 



-cr<> 



31.0 



INT ENA 



PRIORITY ^0 



-c/ 



LEVEL 1 INTREQ 



3F.6 o-:- LEVEL 2 INTREQ 



"^ 



-^ 



MASTER/SLAVE MD 
31.2 



POLARITY 



30.6 



Figure 10-1. SPI Block Diagram 



f-g3 SPISIMO PIN 



-g3 SPISOMI PIN 



-22 SPICLK 



10-3 



Serial Peripheral Interface (SPi) Module Overview 



10.1.2 SPI Control Registers 



The SPI Control registers occupy Peripheral File Frame 3 as shown in 
Figure 10-2. 



Table 10-1. SPI Memory Map 



Peripheral 

File 
Location 


Symbol 


Name 


P030 


SPICCR 


SPI Configuration Control Register 


P031 


SPICTL 


SPI Control Register 


P032-P036 




Reserved 


P037 


SPIBUF 


Receive Data Buffer Register 


P038 




Reserved 


P039 


SPI DAT 


Serial Data Register 


P03A-P03C 




Reserved 


P03D 


SPiPCI 


SPI Pin Control 1 


P03E 


SPIPC2 


SPI Pin Control 2 


P03F 


SPIPRI 


SPI Priority Control 



10-4 



SPI Operation 



10.2 SPI Operation 



Figure 10-2 shows a typical connection of the SPI for communications 
between two microcontrollers. One controller, the master, initiates data trans- 
fer by sending the SPICLK signal. Data is enabled out of both shift registers 
on one edge of the clock and latched into both shift registers on the opposite 
clock edge. Thus both controllers send and receive data at the same time. 
Whether or not the data is meaningful or "dummy" data depends on the 
application software. 

There are three possible cases for data transmission: 

• Master sends data and Slave sends "dummy" data 

O Master sends data and Slave sends data 

9 Master sends "dummy" data and Slave sends data 

The Master can initiate data transfer at any time because it controls the 
SPICLK. The manner in which the master knowns when the Slave wishes to 
broadcast data is determined by the software protocol. 



SPI MASTER (MASTER/SLAVE = 1) 



SIMO 



SERIAL INPUT BUFFER 
(SPIBUF) 



I 



SHIFT REGISTER 
(SPIDAT) 



msb 



PROCESSOR 1 



SOMI 



Isb 



SLAVE IN/ 



MASTER 
OUT 



SLAVE OUT 



MASTER 
IN 



SCLK ! gg'g^ ^! SCLK 



SPI SLAVE (MASTER/SLAVE = 0) 



SIMO 



SERIAL INPUT BUFFER 
(SPIBUF) 



SOMI 



I 



SHIFT REGISTER 
(SPIDAT) 



msb 



Isb 



PROCESSOR 2 



Figure 10-2. SPI Master/Slave Connection 



10-5 



SPI Operation 



10.2.1 SPI Data Format 



Three character-length bits (SPICCR.2-0) specify the number of bits in the 
data character (1-8 bits). This information directs the state control logic to 
count the number of bits received or transmitted to determine when a com- 
plete character has been processed. For characters with fewer than 8 bits: 

1 ) Data must be written to SPI DAT left justified. 

2) Data must be read back from SPIBUF right justified. 

3) SPIBUF contains the most recently received character, right justified, 
plus any bits left over from previous transmission (s) which have been 
shifted to the msb position. 

For example: 

If the character length = 1 bit, and 

the value written into SPIDAT = 07Fh, 

then; 

SPIDAT (before transmission) 



(transmitted) 



1111111 


SPIDAT (after transmission) 


11111111^ 


SPIBUF (after transmission) 


11111111 



1 (received) 



•■10.2.2 SPI Interrupts 



The interrupt for the SPI is controlled by bits in two registers. The SPI INT 
ENA bit (SPICTL.O), when set, allows assertion of an interrupt request when 
an interrupt condition occurs. The SPI PRIORITY bit (SPIPRI.6) determines 
whether SPI interrupts are level 1 or level 2 priority requests. 

When a complete character has been shifted into or out of the SPIBUF regis- 
ter, the SPI Interrupt Flag is set and an interrupt is generated if enabled by SPI 
INT ENA (SPICTL.O). The interrupt flag remains set until cleared by one of 
the following four events. 

• CPU reads the SPI receiver buffer (SPIBUF), 

• CPU enters the Halt or Standby mode with an IDLE instruction, 

• Software sets the SPI SW RESET bit, or 

• A System resets occurs. 

An interrupt request must be explicitly cleared by one of the four methods 
listed above to avoid generating another interrupt. An interrupt request can 
be temporarily disabled by clearing the SPI INT ENA bit. However, unless the 
SPI INT FLAG itself is cleared, the interrupt request will be reasserted when 
the enable bit is again set to 1 . 



10-6 



SPI Operation 



The priority level of the SPI interrupt is specified by the SPI PRIORITY bit 
(SPIPRI.6). If SPI PRIORITY = 0, then a level 1 priority interrupt is generated. 
If SPI PRIORITY = 1, then a level 2 priority interrupt is generated. 

The SPI INT FLAG bit indicates, when set, that a character has been placed 
into the SPIBUF register and is ready to be read. If the CPU does not read the 
character by the time the next complete character has been received, the new 
character is written into the SPIBUF and the RECEIVER OVERRUN bit 
(SPICTL.7) is set. This indicates that the last character of data has been 
overwritten with new data before the previous character could be read. 

10.2.3 SPI Clock Sources 

The CLOCK POLARITY bit (SPICCR.6), selects the active edge of the clock, 
either rising or falling. 

In the slave mode, the SPI clock is received from an external source and can 
be no greater than the CLKIN frequency divided by 32. 

In the master mode, the SPI clock is generated by the SPI and is output on the 
SPICLKpin. 

The SPI BIT RATEO-2 bits (SPICCR.5-3) determine the bit transfer rate for 
sending and receiving the data. This transfer rate is defined by: 

SPI BAUD RATE = CLKIN / (8 * 2^) 

where b=bit rate in SPICCR.5-3 (range 0-7). 

10.2.4 SPI Operation Modes 

The MASTER/SLAVE bit (SPICTL.2) selects the operating mode and the 
source of SPICLK. The SPI module may operate as a Master or Slave. 

10.2.4.1 Master 

In the Master mode (MASTER/SLAVE = 1), the SPI provides the serial clock 
on the SPICLK pin for the entire serial communicatipns network. Data is 
output on the SPISIMO pin on the first SPICLK edge and latched from the 
SPISOMI pin on the opposite edge of SPICLK. 

The SPICCR register (SPI BIT RATEO-2) determines the bit transfer rate for 
the network, both transmit and receive. There are eight data transfer rates that 
can be selected by these control bits as shown in Table 9-3 on page 9-20. 

Data written to the SPI DAT register initiates data transmission on the 
SPISIMO pin, msb of data transmitted first. Simultaneously, received data is 
shifted in the SPISOMI pin into the SPIDAT register, and upon completion 
of transmitting the selected number of bits, the data is transferred to the 
SPIBUF (double buffered receiver) for reading by the CPU to permit new 
transactions to take place. Data is shifted into the SPI most significant bit first; 
there, it is stored right-justified in the SPIBUF. 



10-7 



SPI Operation 



To receive a character when operating as a master, data must be written to the 
SPI DAT to initiate the transaction. When the specified number of data bits 
have been shifted through the SPI DAT register, the following events occur: 

1) The SPI INT FLAG bit is set, 

2) SPI DAT contents transfer to SPIBUF, and 

3) If the SPI INT ENA bit is set to one, an interrupt is asserted. 

Writing to the SPIDAT register before transmission is complete corrupts the 
current transmission. 



10.2.4.2 Slave 



In the slave mode (MASTER/SLAVE = 0), data shifts out on the SPISOMI 
pin and in on the SPISIMO pin. The SPICLK pin is used as the input for the 
serial shift clock, which is supplied from the external network master. The 
transfer rate is defined by the input clock on the SPICLK pin, which is supplied 
from the network master. The SPICLK input frequency should be no greater 
than CLKIN frequency divided by 32. 

Data written to the SPIDAT register is transmitted to the network when the 
SPICLK is received from the network master. To receive data, the SPI waits for 
the network master to send SPICLK and then shifts the data on the SPISIMO 
pin into the SPIDAT register. If data is to be transferred by the slave simul- 
taneously, then it must be written to the SPIDAT register prior to the begin- 
ning of SPICLK. 

When the TALK bit (SPICTL.1) is cleared, data transmission is disabled and 
the output line is put into a high impedance state. This allows many slave 
devices to be tied together on the network, but only one slave is allowed to 
talk at a time. 



10.2.5 Initialization 



A system reset forces the SPI peripheral module into the following default 
configuration. 

The unit is configured as a slave module (MASTER/SLAVE = 0). 

The transmit capability is disabled (TALK = 0). 

Data is latched at the input on the falling edge of SPICLK. 

Character length is assumed to be 1 bit. 

The SPI interrupts are disabled. 

Data in the SPI Data Register is OOh. 

o change this SPI configuration it is a good idea to use the SPI SW RESET 
bit. Set the SPI SW RST bit (SPICCR.7); make your desired changes; then 
clear the SPI SW RST bit. This prevents unwanted and unforeseen events 
from occurring during or as a result of mode change. 



10-8 



SPI Operation 



10.2.6 SPI Example 



The following timing diagrams illustrate an example SPI data transfer between 
two TMS370 devices using a character length of five bits. The lettered notes 
following the first diagram are keyed to the letter labels in the diagram. 



5 BITS PER CHARACTER 



MASTER SPI , 
INT FLAG 
SLAVE SPI 
INT FLAG 



SPI SOMI 
FROM SLAVE 



l_!r 



SPI SIMO 
FROM MASTER 

CLOCK 



■4^ 



n 



^v- 



— L_r~i 

7 6 5 4 3 

J — LJ — ' — ' 

7 6 5 4 3 



C D E F 



-^v 



H I 



7 6 5 4 3 

— r 



POLARITY = IlJlJLJI-JL 



i__r^ 
^i_n_n_n_rLrL 



CLOCK 
POLARITY = 1 



i_n_n_rLn_r 



4V- 



■LTLTLrLrLr 



A. Slave writes ODOh to SPIDAT and waits for the master to shift out the data. 

B. Master writes 058h to SPIDAT which starts the transmission procedure. 

C. First byte is finished and sets the interrupt flags. 

D. Slave reads OBh from its SPIBUF register (right justified). 

E. Slave writes 04Ch to SPIDAT and waits for the master to shift out the data. 

F. Master writes 06Ch to SPIDAT which starts the transmission procedure. 

G. Master reads 01 Ah from the SPIBUF register {right justified). 
H. Second byte is finished and set the interrupt flags. 

I. Master received 09h and the Slave received a ODh (right justified). 



SIGNALS CONNECTING TO MASTER PROCESSOR. 



SPI SIMO 
OUTPUT , 

SPI SOMI 

INPUT SAMPLED 

SPICLK OUT 

(CLOCK 

POLARITY = 0) 

SPICLK OUT 

(CLOCK 

POLARITY = 1) 



BIT 4 



BITS 



BIT 2 



— D — Q 




10-9 



SPI Control Registers 



10.3 SPI Control Registers 



ADDR 
1030h 

1031h 

1032h 
TO 

loseh 

1037h 
1038h 
1039h 

103Ah 

TO 
103Ch 

103Dh 

103Eh 

103Fh 



The SPI is controlled and accessed through registers in the Peripheral File. 
These registers are listed in Figure 1 0-3 and described in the following sec- 
tions. The bits shown in shaded boxes in Figure 10-3 are Privilege Mode bits, 
that is, they can only be written to in the Privilege Mode. 





PERIPHERAL FILE FRAME 3: SERIAL PERIPHERAL INTERFACE (SPI) CONTROL REGISTERS 


PF 


BIT 7 


BIT 6 


BITS 


BIT 4 


BIT 3 


BIT 2 


BIT 1 


BIT 


30 


SPI 
SW RESET 


CLOCK 
POLARITY 


SPI BIT 
RATE2 


SPI BIT 
RATE1 


SPI BIT 
RATEO 


SPI 
CHAR2 


SPI 
CHAR1 


SPI 
CHARO 


31 


RECEIVER 
OVERRUN 


SPI 
INT FLAG 











MASTER/ 
SLAVE 


TALK 


SPI 
INT ENA 


32 
TO 
36 


RESERVED 


37 


SPI DATA BUFFER REGISTER 


38 


RESERVED 


39 


SPI SERIAL DATA REGISTER 


3A 

TO 
3C 


RESERVED 


3D 














SPICLK 
DATA IN 


SPICLK 
DATA OUT 


SPICLK 
FUNCTION 


SPICLK 
DATA DIR 


3E 


SPISIMO 
DATA IN 


SPISIMO 
DATA OUT 


SPISIMO 
FUNCTION 


SPISIMO 
DATA DIR 


SPISOMI 
DATA IN 


SPISOMI 
DATA OUT 


SPISOMI 
FUNCTION 


SPISOMI 
DATA DIR 


3F 




iliiPlli 
PRIORITY 


ESPEN 


















SPICCR 
SPICTL 



SPIBUF 
SPIDAT 



SPiPCI 



SPIPC2 



SPIPRI 



Figure 10-3. SPI Control Registers 



10-10 



SPI Control Registers 



10.3.1 SPI Configuration Control Register 

The SPICCR register controls the setup of the SPI for operation. A summary 
of the register functions and bit assignments is shown below. 



SPI Configuration Control Register (SPICCR) 
[Memory Address - 1030h] 



Bit# 



P030 



7 


6 


5 


4 


3 


2 


1 





SPI 

SW 

RESET 


CLOCK 
POLARITY 


SPI 

BIT 

RATE2 


SPI 

BIT 

RATE1 


SPI 

BIT 

RATED 


SPI 
CHAR2 


SPI 
CHAR1 


SPI 
CHARO 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



RW-0 



R = Read, W=Write, -n= Value after RESET 

Bits 0-2 CHARO-2. Character Length Control Bits 0-2. 

These three bits determine the number of bits to be shifted in or out as a single 
character during one shift sequence. The value of these bits is represented in 
the following table. 



Table 10-2. SPI Character Bit Length 



CHAR2 


CHAR1 


CHARO 


CHARACTER 
LENGTH 











1 








1 


2 





1 





3 





1 


1 


4 


1 








5 


1 





1 


6 


1 


1 





7 


1 


1 


1 


8 



10-11 



SPI Control Registers 



Bits 3-5 SPI BIT RATEO-2. SPI Bit Rate Control Bits 0-2. 

These bits determine the bit transfer rate if the SPI is the networl< master. There 
are eight data transfer rates (each a function of the system clock) that can be 
selected. The system clock is divided by an eight bit, free-running prescaler 
from which eight taps are available for use as the shift clock. One data bit is 
shifted per SPICLK cycle. 



Table 10-3. SPI Clock Frequency 



SPIt 

BIT 

RATE2 


SPIt 

BIT 

RATE1 


SPit 

BIT 

RATED 


SPI CLOCK 
FREQUENCY 











CLKIN/8 








1 


CLKIN/16 





1 





CLKIN/32 





1 


1 


CLKIN/64 


1 








CLKIN/128 


1 





1 


CLKI N/256 


1 


1 





CLKIN/512 


1 


1 


1 


CLKIN/1024 



t|f the SPI is a network slave, the module receives a clock on the SPICLK pin 
from the network master; and these bits have no effect on SPICLK. The fre- 
quency of the input clock should be no greater than the CLKIN frequency 
divided by 32. 

Bit 6 CLOCK POLARITY. Shift Clock Polarity. 

The CLOCK POLARITY bit controls the polarity of the SPICLK signal, 

= The inactive level is low; data is output by the rising edge of SPICLK; input 

data is latched by the falling edge of SPICLK. 

1 = The inactive level is high; data is output by the falling edge of SPICLK; 

input data is latched by the rising edge of SPICLK. 

Bit 7 - SPI SW RESET. SPI Software Reset. 

Writing a 1 to this bit initializes the SPI circuitry and operating flags to the reset 
condition. Specifically, the RECEIVER OVERRUN and SPI INT FLAG flags are 
cleared. The SPI configuration remains unchanged. If it is operating as a mas- 
ter, the SPICLK output level returns to its inactive level. 

When a "0" is written to SPI SW RESET the SPI is ready to transmit or receive 
the next character. A character written to the transmitter when SPI SW RESET 
is a "1" will not be shifted out when SPI SW RESET bit is cleared. A new 
character must be written to the Serial Data Register. To change any config- 
uration bits, this bit should be used (see Section 10.2.5, page 10-8). 



10-12 



SPI Control Registers 



10.3.2 SPI Operation Control Register 

The SPI Operation Control Register contains control and status bits as shown 
below. 

SPI Operation Control Register, (SPICTL) 
[Memory Address - 1031 h] 

Bit # - 
P031 



7 


6 


5 


4 


3 


2 


1 





RECEIVER 
OVERRUN 


SPI 

INT 

FLAG 


— 


— 


— 


MASTER/ 
SLAVE 


TALK 


SPI 
INT 
ENA 



R-0 



R-0 RW-0 



RW-0 



RW-0 



BitO- 



Bit 1 



Bit 2 



R = Read, W=Write, -n= Value after RESET 

SPI INT ENA. SPI Interrupt Enable. 

This bit controls the SPI's ability to generate an interrupt. The SPI INT FLAG 

is unaffected by this bit. 

= disable interrupt. 

1 = enable interrupt. 

TALK. Master/Slave Transmit Enable. 

This bit allows data transmission (master or slave) to be disabled by placing 
the serial data output in a high impedance state. TALK is cleared (disabled) 
by a system reset. 

= Transmission disabled; if not programmed as a general purpose I/O pin, the 

SPI serial output is in a high impedance state. 

1 = Transmission enabled. 



During reset 



MASTER/SLAVE. SPI Network Mode Control. 

This bit determines whether the SPI is a network master or slave. 

initialization, the SPI is automatically configured as a slave. 

= SPI configured as a slave. 

1 = SPI configured as a master 

Bits 3-5 - Reserved. Read data is indeterminate. 

Bit 6 - SPI INT FLAG. Serial Peripheral Interrupt Flag. 

The SPI hardware sets this bit to indicate it has completed sending or receiving 
the last bit and is ready to be serviced. A character received is placed in the 
receiver buffer at the time the SPI INT FLAG bit is set. SPI INT FLAG is cleared 
when the receiver buffer is read. It is also cleared by an SPI software reset (SPI 
SW RESET) or by a system reset. 

Bit 7 - RECEIVER OVERRUN. 

This bit is a read only flag which the SPI hardware sets when a receive or 
transmit operation completes before the previous character has been read from 
the receive buffer. It indicates that the last received character has been over- 
written, and therefore has been lost. RECEIVER OVERRUN is cleared when 
the receiver buffer is read. It is also cleared by SPI SW RESET or a system 
reset. 



10-13 



SPI Control Registers 



10.3.3 Serial Input Buffer (SPIBUF) 

The SPIBUF register contains the data received from the network ready for the 
CPU to read. 

Serial Input Buffer, (SPIBUF) 
[Memory Address - 1037h] 

Bit#- 
P037 



7 


6 


5 


4 


3 


2 


1 





RCVD7 
(msb) 


RCVD6 


RCVD5 


RCVD4 


RCVD3 


RCVD2 


RCVD1 


RCVDO 
(Isb) 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R = Read, -n= Value after RESET 

Once the Serial Data Register has received the complete character, the character is then 
transferred to the SPIBUF Register where it can be read. The SPI INT FLAG bit 
(SPICTL.6) is set to indicate that the data is available when the received character is 
transferred. Since data is shifted into the SPI most significant bit first, it is stored right 
justified in the SPIBUF. 

10.3.4 Serial Data Register (SPIDAT) 

The SPIDAT register is the transmit/receive shift register. Data written to the 
SPIDAT is shifted out on subsequent SPICLK cycles. For every bit shifted out 
of the SPI a bit is shifted into the other end of the shift register. 

Writing to the SPIDAT performs two functions. First, it provides data to be 
output on the serial output pin if the TALK bit is set. Second, when the SPI 
is operating as a master, writing to this register initiates a transaction. 

To initiate a receiver sequence, dummy data is written to the register. Since the 
data is not hardware justified for characters that are shorter than eight bits, 
transmit data must be written in left justified form and received data read in 
right justified form. 

Serial Data Register, (SPIDAT) 
[Memory Address - 1039h] 

Bit#- 
P039 

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 

R = Read, W=Write, -n= Value after RESET 



7 


6 


5 


4 


3 


2 


1 





SDAT7 


SDAT6 


SDAT5 


SDAT4 


SDAT3 


SDAT2 


SDAT1 


SDATO 



10-14 



SPI Control Registers 



10.3.5 Port Control Registers 



Two Port Control Registers (SPIPC1 and SPIPC2) allow a programmer to 
control all functions for a SPI port pin in one write cycle. Each module pin is 
controlled by a nibble in one of the SPIPC's. 



10.3.5.1 Port Control Register 1 (SPIPC1) 

This register controls the SPICLK pin. 



Bit#- 
P03D 



BitO 



Bit 1 



Bit 2 



Bits 



Port Control Register 1. (SPIPC1) 
[Memory Address - 103Dh] 



— 


— 


— 


— 


SPICLK 

DATA 

IN 


SPICLK 
DATA 
OUT 


SPICLK 
FUNCTION 


SPICLK 

DATA 

DIR 



R = Read, W=Write, 



R-0 RW-0 RW-0 

-n= Value after RESET 



RW-0 



SPICLK DATA DIR.. SPICLK Data Direction. 

This bit determines the data direction on the SPICLK pin if SPICLK has been 

defined as a general purpose I/O pin. 

= SPICLK pin is a general purpose INPUT port. 

1 = SPICLK pin is a general purpose OUTPUT port. 

SPICLK FUNCTION. SPICLK Pin Function Select. 
This bit defines the function of the SCICLK pin. 

= SPICLK pin is a general purpose digital I/O port. 

1 = SPICLK pin contains the SPI clock. 

SPICLK DATA OUT. SPICLK Port Data Out. 

This bit contains the data to be output on the SPICLK pin if the following 

conditions are met: 

a. SCICLK pin has been defined as a general purpose I/O pin. 

b. SCICLK pin data direction has been defined as output. 

SPICLK DATA IN. SPICLK Pin Port Data In. 

This bit contains the current value on the SCICLK pin regardless of the mode. 

A write to this bit has no effect. 



Bits 4-7 - Reserved. Read data is indeterminate. 



Note: 

The SPICLK pin always functions as the SPICLK input pin in the slave 
mode (i.e., SPICLK.2-0) even if SPICLK FUNCTION = and SPICLK 
DATA DIR = 0. 



10-15 



SPI Control Registers 



10.3.5.2 Port Control Register 2 



The SPIPC2 register controls the SPISOMI and SPISIMO pin functions. 

Port Control Register 2, (SPIPC2) 
[Memory Address - 103Eh) 



Bit#- 



P03E 



SPISIMO 

DATA 

IN 


SPISIMO 
DATA 
OUT 


SPISIMO 
FUNCTION 


SPISIMO 

DATA 

DIR 


SPISOMI 

DATA 

IN 


SPISOMI 
DATA 
OUT 


SPISOMI 
FUNCTION 


SPISOMI 

DATA 

DIR 



R-0 



RW-0 RW-0 



RW-0 



R-0 



RW-0 



RW-0 



RW-0 



BitO 



Bitl 



Bit 2 



Bits 



Bit 4 



Bit5- 



Bit6 



Bit 7 



R = Read, W=Write, -n= Value after RESET 

SPISOMI DATA DIR. SPISOMI Data Direction. 

This bit determines the data direction on the SPISOMI pin if SPISOMI has 

been defined as a general purpose I/O pin. 

= SPISOMI pin is a general purpose INPUT port. 

1 = SPISOMI pin is a general purpose OUTPUT port. 

SPISOMI FUNCTION. SPISOMI Pin Function Select. 
This bit defines the function of the SPISOMI pin. When SPISOMI is an input 
and SPISOMI FUNCTION and SPISOMI DATA DIR are disabled, then SPICLK 
still clocks the internal circuitry. 

= SPISOMI pin is a general purpose digital I/O port. 

1 = SPISOMI pin contains the SPI data. 

SPISOMI DATA OUT. SPISOMI Pin Data Out. 

This bit contains the data to be output on the SPISOMI pin if the following 

conditions are met: 

a. SPISOMI pin has been defined as a general purpose I/O pin. 

b. SPISOMI pin data direction has been defined as output. 

SPISOMI DATA IN. SPISOMI Pin Data In. 

This bit contains the current value on the SCISOMI pin regardless of the mode. 

A write to this bit has no effect. 

SPISIMO DATA DIR. SPISIMO Data Direction. 

This bit determines the data direction on the SPISIMO pin if SPISIMO has 

been defined as a general purpose I/O pin. 



SPISIMO pin is a general purpose INPUT port. 
SPISIMO pin is a general purpose OUTPUT port. 



SPISIMO FUNCTION. SPISIMO Pin Function Select. 
This bit defines the function of the SPISIMO pin. 

= SPISIMO pin is a general purpose digital I/O port. 

1 = SPISIMO pin contains the SPI data. 

SPISIMO DATA OUT. SPISIMO Pin Data Out. 

This bit contains the data to be output on the SPISIMO pin if the following 

conditions are met: 

a. SPISIMO pin has been defined as a general purpose I/O pin. 

b. SPISIMO pin data direction has been defined as output. 

SPISIMO DATA IN. SPISIMO Pin Data In. 

This bit contains the current value on the SCISIMO pin regardless of the mode. 

A write to this bit has no effect. 



10-16 



SPI Control Registers 



10.3.6 SPI Interrupt Priority Control Register (SPIPRI) 

The SPIPRI Register selects the interrupt priority level of the SPI interrupt. 
The register is read only during normal operation, but can be written to in the 
privileged mode. 



Bit#- 



P03F 



SPI Interrupt Priority Control Register. (SPIPRI) 
[Memory Address - 103Fh] 



SPI 
STEST 


SPI 
PRIORITY 


SPI 
ESPEN 


... 


... 


... 


... 


... 



RP-0 



RP-0 



RP-0 



Bits 0-4 
Bit 5 - 



R = Read, W=Write, P= Privileged Write only, 
- Reserved. Read data is indeterminate. 



-n= Value after RESET 



Bite 



Bit 7 



SPI ESPEIM. Emulator Suspend Enable. 

This bit has no effect except when using the XDS emulator to debug a program; 
then, this bit determines SPI operation when the program is suspended by an 
action such as a hardware or software breakpoint. 

= When the emulator is suspended, the SPI continues to work until the cur- 

rent transmit/receive sequence is complete. 

1 = When the emulator is suspended, the the state of the SPI is frozen so that 

it can be examined at the point that the emulator was suspended. 

SPI PRIORITY. Interrupt Priority Select. 

= Interrupts are level 1 (high priority) requests. 

1 = Interrupts are level 2 (low priority) requests. 

SPI STEST. 

This bit must be cleared (0) to ensure proper operation. 



10-17 



SPI Control Registers 



10-18 



Introduction 



TMS370 Family Devices 



CPU and Memoiy Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module mv. 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Information 



Appendixes 



11. Analog-To-Digital Converter Module 

This section discusses the architecture and programming of the Analog-to- 
Digital Converter module on TMS370C050 and TMS370C850 devices. 

This section covers the following topics: 

Section Page 

11.1 Analog-To-Dlgital Converter (A/D) Overview 11-2 

11.1.1 A/D Physical Description 11-2 

11.1.2 A/D Control Registers 11-4 

11.2 A/D Operation 11-5 

11.2.1 A/D Input/Output Pins 11-5 

11.2.2 A/D Sampling Time 11-5 

11.2.3 A/D Conversion 11-5 

11.2.4 A/D Interrupts 11-6 

11.2.3 A/D Programming Considerations 11-7 

11.3 A/D Example Program 11-8 

11.4 A/D Control Registers 11-4 

11.4.1 Analog Control Register (ADCTL) 11-11 

11.4.2 Analog Status and Interrupt Register, (ADSTAT) 11-13 

11.4.3 Analog Conversion Data Register (ADDATA) 11-13 

11.4.4 Analog Port E Data Input Register (ADIN) 11-14 

11.4.5 Analog Port E Input Enable Register (ADENA) 11-14 

11.4.6 Analog Interrupt Priority Register (ADPRI) 11-15 



11-1 



Analog-To-Digital Converter (A/D) Overview 



11.1 Analog-To-Digital Converter (A/D) Overview 

The Analog-to- Digital Converter module (A/D) is an 8 bit successive 
approximation converter with internal sample-and-hold circuitry. The module 
has eight multiplexed analog input channels which allows the processor to 
convert the voltage levels from up to 8 different sources. 

11.1.1 A/D Physical Description 

"he A/D module, shown in Figure 11-1, consists of: 

eight analog input channels (AN0-AN7), any of which can be software 

configured as digital inputs (E0-E7) if not needed as analog channels, 

an A/D Input Selector (INPUT), 

a +Vref Input Selector (+VREF), 

the Analog-to- Digital Converter (A/D), 

the AD DATA register which contains the digital value of a completed 
conversion, and 

A/D module control registers. 

he input channels can be routed through either the channel selector or the 
positive voltage selector. The A/D converter then processes these signals and 
puts the result in the AD DATA register. The A/D interrupt circuit informs the 
rest of the system when a conversion has completed. 



11-2 



Analog-To-Digital Converter (A/D) Overview 



PIN 



DIGITAL INPUT REGISTER 



ANO 



AN1 



AN2 



AN3 



AN4 



AN5 



AN6 



AN7 




EO 



7D.0 



E1 



7D.1 



E2 



7E.2. 



7E.3. 



7D.2 



E3 



7D.3 



r-fm: 



7D.4 



cTT^ 



E5 



7D.5 



H^^ 



7D.6 



.r-r^^^ 



7D.7 



^CC3^ 
Voeo O- 



/7 



70.x 



70.6 



INPUT 



SAMPLE 
START 



70.x 



5 4 3 



+VREF 



70.7 



CONVERT 
START 




72 



ADDATA REG 



71.2 



READY 



A/D INTERRUPT 
71.0 

— I flag' 



71.1 



INT 
ENA 



-o/ 



LEVEL 1 INT 



LEVEL 2 INT 



7F.6 



Figure 11-1. Analog-to-Digital Converter Block Diagram 



11-3 



Analog-To-Digital Converter (A/D) Overview 



11.1.2 A/D Control Registers 



The A/D Control registers occupy Peripheral File Frame 7 as shown in Table 
11-1. 



Table 11-1. A/D Memory Map 



Peripheral 

File 
Location 


Symbol 


Name 


P070 


ADCTL 


Analog Control Register 


P071 


ADSTAT 


Analog Status and Interrupt Register 


P072 


AD DATA 


Analog Conversion Data Register 


P073-P07C 




Reserved 


P07D 


ADIN 


Port E Data Input Register 


P07E 


ADENA 


Port E Input Enable Register 


P07F 


ADPRI 


Port E Interrupt Priority Register 



11-4 



A/D Operation 



11.2 A/D Operation 

The following sections describe the functions and options of the A/D module. 



11.2.1 A/D Input/Output Pins 



The A/D module uses 10 pins to connect to the external world. Eight of the 
10 pins (AN0-AN7) are individually configured as general purpose input pins 
when not used as analog inputs. 

Seven of the eight analog channels (AN1-AN7) are also available as the pos- 
itive input voltage reference. This feature allows a weighted measurement or 
ratio of one channel to another. 

The analog voltage supply pins Vcc3 and Vss3 isolate the A/D module from 
the digital switching noise which may be present on the other power supply 
pins (Vcci' Vcc2' Vssif and Vss2)- This isolation provides a more accurate 
conversion. Power to the Vcc3 and Vss3 P'ns should run on separate con- 
ductors from the other power lines. Power conductors to the Vcc3 and Vss3 
should be as short as possible, and the two lines should be properly 
decoupled. Other standard noise reduction techniques should be applied to 
help provide a more accurate conversion. 

Vref can be chosen to be either Vcc3 or one of the analog input channels 
AN1 to AN7. Vcc3 must provide power to the A/D module even if it does not 
provide the voltage reference. A channel configured as the +Vref for one 
conversion can be changed to an analog input channel for the next conver- 
sion. 

11.2.2 A/D Sampling Time 

The application program controls the length of the sample time which pro- 
vides the flexibility to optimize the conversion process for both high and low 
impedance sources. The program should wait 1 ps for each kilohm of source 
output impedance or a minimum of 1 us for low impedance sources. 

11.2.3 A/D Conversion 

The digital result of the conversion process is given in the following formula. 

Digital result = 255 * Voltage of input / Voltage of reference 

The conversion process takes 164 cycles which results in a conversion time 
of 32.8 microseconds at 20 MHz. A maximum of 27,600 conversions per 
second are possible at 20 MHz including setting up the conversion, sampling, 
converting and saving the results. 

In Ratiometric conversions, the conversion value is a ratio of the Vref source 
to the analog input. As Vref is increased, the input voltage needed to give a 
certain conversion value changes; but all conversion values keep the same 
relationship to Vref- That is, one half of Vref always results in the value 080h 
regardless of the value of Vref (assuming that Vref 'S in the range of 2.5 to 
5.5 volts above Vsss)- 



11-5 



A/D Operation 



Figure 11-2 shows an example of Ratiometric conversion. In this example, the 
digital result of the conversion indicates the position of the potentiometer 
wiper even if the battery loses voltage over time. The A/D conversion always 
gives the ratio of the resistor values on either side of the wiper even if Vref 
drops from 5.0 to 2.5 volts. 



2.5 TO 5 V 



BATTERY 



*Vref 
ANALOG IN 

AVss 



Figure 11-2. Ratiometric Conversion Example 



11.2.4 A/D Interrupts 



The A/D module sets the AD INT FLAG bit (ADSTAT.1) at the end of the 
conversion process. If both the AD INT FLAG and the AD INT ENA bit 
(ADSTAT.O) are set, then the module generates an interrupt request. This 
interrupt request may be asserted on either the high priority level 1 or the lower 
priority level 2 depending on the AD PRIORITY bit (ADPRI.6). 

The program must clear the AD INT FLAG or else the same interrupt will cause 
the CPU to enter the interrupt routine again. If the AD INT ENA bit is cleared 
without clearing the flag, the interrupt is reasserted when the AD INT ENA bit 
is again set. 



11-6 



A/D Operation 



11.2.5 A/D Programming Considerations 

The programmer should follow these steps to obtain data from the A/D con- 
verter. 

1 ) Write to the ADCTL register to: 

• Select the Analog channel (ADCTL.2-0). 

• Select the Vref source (ADCTL.5-3). 

• Set the SAMPLE START bit to 1 (ADCTL.6). 

2) Wait for the sample time to elapse. 

3) Set the CONVERT START bit (ADCTL.7); leave the SAMPLE START 
bit (ADCTL.6) set. 

4) Wait for either the interrupt flag to be set or the A/D interrupt to occur. 

5) Read the conversion data register (ADDATA). 

6) Clear the interrupt flag bit (ADSTAT.1 ). 

To begin sampling, set the SAMPLE START bit. The program should wait 
1 MS for each kilohm of source output impedance or a minimum of 1 jjs for 
low impedance sources. When the sample time completes, set both the 
SAMPLE START and CONVERT START bits. 

Eighteen cycles after the program sets the CONVERT START bit, the A/D 
module clears both the SAMPLE START and CONVERT START bits to signify 
the end of the internal sampling phase. After these bits are cleared, the pro- 
gram can change the input channel without affecting the conversion process. 
The voltage reference source Vref should remain constant throughout the 
conversion. 

To stop a conversion in progress set the SAMPLE START bit to 1 anytime after 
the A/D clears this bit. The entire conversion process requires 164 system 
clock cycles after the program sets the CONVERT START bit. 



11-7 



A/D Example Program 



11.3 A/D Example Program 



This example program samples and converts data from all 8 channels and 
stores the digital results into a table beginning at ATABLE. The routine stops 
interrupting the main program after it finishes all eight channels. If the main 
program wants more recent data it needs only to execute the code at 
RESTART and the A/D routine will again sample and convert all eight chan- 
nels of data. The A/D interrupt enable bit is cleared by the A/D interrupt 
routine as a signal to the main program that all eight channels have been 
processed. The address of the label ATOD must be placed into the interrupt 
vector table located at 7FECh and 7FEDh. 

A/D control register 
A/D status register 
A/D conversion results 
A/D input enable 
keeps current channel number 
8 byte table that stores 
channel data, Isb first 

;all channels to A/D inputs 

; (reset condition) 

; start the interrupts now 

MAIN PROGRAM GOES HERE 



ADCTL 


.EQU 


P070 


ADSTAT 


.EQU 


P071 


ADDATA 


.EQU 


P072 


ADENA 


.EQU 


P07E 




.REG 


ADCHANL 




.REG 


ATABLE , 8 


INIT 


MOV 


#0, ADENA 




CALL 


RESTART 



CALL 



RESTART 



RESTART 



MORE MAIN PROGRAM 

SUBROUTINE SECTION 

CLR ADCHANL 

MOV # 00 Ih, ADSTAT 

MOV 

MOV 

RTS 



#040h, ADCTL 
#OCOh, ADCTL 



; start taking more data 



initialize channel 
enable interrupts, clear 

any flag 
start sampling (approx. 2 ps 

delay) 
start converting now; enter 

main program 



INTERRUPT ROUTINE FOR ANALOG TO DIGITAL CONVERTER 



ATOD 



PUSH 

PUSH 

MOV 

MOV 

MOV 

INC 
BTJZ 

CLR 
MOV 

JMP 



A 
B 

ADCHANL , B 
ADDATA, A 
A, ATABLE (B) 

B 
#8,B,G0CNVRT 

ADCHANL 
#0, ADSTAT 

EXITA2D 



;save registers 

get channel number 

get A/D conversion value 

store in a table according to 

channel number 
point to next channel 
stop when all channels sampled 

(bit3 =1) 
reset the A/D channel 
turn off interrupt and 

clear flag 
all 8 channels taken, enable 

set to now 



11-8 



A/D Example Program 



GOCNVRT 


MOV 
MOV 


B,ADCHANL 
#01h,ADSTAT 




OR 

MOV 

OR 


#040h,B 
B,ADCTL 
#080h,ADCTL 


EXITA2D 


POP 
POP 
RTI 


B 
A 



; Store current A/D channel 

; clear interrupt flag to prevent 

; more interrupts 

;set up sample bit in value 

; start sampling channel data 

; start converting data 

;Restore data 



11-9 



A/D Control Registers 



11.4 A/D Control Registers 

The A/D module control registers occupy peripheral file frame 7, as shown in 
Table 1 1 -2. The bits shown in shaded boxes in Table 1 1 -2 are Privilege Mode 
bits, that is, they can only be written to in the Privilege Mode. 

Table 11-2. Peripheral File Frame 7: A-to-D Converter Control Registers 



PERIPHERAL FILE FRAME 7: A-TO-D CONVERTER CONTROL REGISTERS 



ADDR PF 
1070h 070 

1071h 071 

1072h 072 

1073h 073 

TO TO 

107Ch 07C 

107Dh 07D 
107Eh 07E 

107Fh 07F 



BIT 7 


BIT 6 


BIT 5 


BIT 4 


BIT 3 


BIT 2 


BIT1 


BIT 


CONVERT 
START 


SAMPLE 
START 


REF VOLT 
SELECT 2 


REF VOLT 
SELECT 1 


REF VOLT 
SELECT 


AD INPUT 
SELECT 2 


AD INPUT 
SELECT 1 


AD INPUT 
SELECT 

















AD 
READY 


AD 
INT FLAG 


AD 
INT ENA 


A-TO-D CONVERSION DATA REGISTER 


RESERVED 


PORT E DATA INPUT REGISTER 


PORT E INPUT ENABLE REGISTER 


liiMli 


AD 

PRIORITY 


AD 

ESPEN 

















ADCTL 

ADSTAT 
ADDATA 



ADIN 
ADENA 



ADPRI 



11-10 



A/D Control Registers 



11.4.1 Analog Control Register (ADCTL) 

The ADCTL register controls the input selection, reference voltage selection, 
sample start and conversion start. 



Bit#- 



P070 



Analog Control Register, (ADCTL) 
[Memory Address - 1070h] 



CONVERT 
START 


SAMPLE 
START 


REF 

VOLT 

SELECT2 


REF 

VOLT 

SELECT1 


REF 

VOLT 

SELECTO 


AD 

INPUT 

SELECT2 


AD 

INPUT 

SELECT1 


AD 

INPUT 

SELECTO 



RW-0 



RW-0 RW-0 



RW-0 



RW-0 RW-0 



RW-0 



RW-0 



R = Read, W=Write, -n= Value after RESET 

Bits 0-2 - AD INPUT SELECTO-2. Analog Input Channel Select Bits 0-2. 

These bits select the channel used for conversion. Channels should be 
changed only after the A/D has cleared the SAMPLE START and CONVERT 
START bits. Changing the channel while either SAMPLE START or CONVERT 
START is 1 invalidates the conversion in progress. 



AD 

INPUT 

SELECT2 


AD 

INPUT 

SELECT1 


AD 

INPUT 

SELECTO 


CHANNEL 











AND 








1 


AN1 





1 





AN2 





1 


1 


AN3 


1 








AN4 


1 





1 


AN5 


1 


1 





AN6 


1 


1 


1 


AiVJ7 



Bits 3-5 - REF VOLT SELECTO-2. Reference Voltage (+Vref) Select Bits 0-2. 

These bits select the channel the A/D uses for the positive voltage reference. 
REF VOLT SELECT bits must not change during the entire conversion. 



REF 

VOLT 

SELECT2 


REF 

VOLT 

SELECT1 


REF 

VOLT 

SELECTO 


+Vref source 











VCC3^ 








1 


AN1 





1 





AN2 





1 ^ 


1 


AN3 


1 








AN4 


1 





1 


AN5 


1 


1 





AN6 


1 


1 


1 


AN7 



f Pin ANO can not be selected as positive voltage reference. 



11-11 



A/D Control Registers 



Bit 6 - SAMPLE START. Sample Start. 

Setting this bit stops any ongoing conversion and starts sampling the selected 
input channel to begin a new conversion. This bit is cleared by the A/D module 
18 system-clock cycles after the program sets the CONVERT START bit. 
Entering Halt or Standby mode clears this bit and aborts any sampling in 
progress. 

Bit 7 - CONVERT START. Conversion Start. 

Setting this bit starts the conversion. This bit is cleared by the A/D 18 system 
clock cycles after the program sets the CONVERT START bit. Entering Halt 
or Standby mode clears this bit and aborts any conversion in progress. 



11-12 



A/D Control Registers 



11.4.2 Analog Status and Interrupt Register, (ADSTAT) 

The ADSTAT register indicates the converter and interrupt status. 

Analog Status and Interrupt Register, (ADSTAT) 
[Memory Address - 1071h] 

Bit#- 
P071 



7 


6 


5 


4 


3 


2 


1 

















AD 


AD 


— 


— 


— 


— 


— 


AD 
READY 


INT 
FLAG 


INT 
ENA 



R-1 



RC-0 



RW-0 



BitO 



R = Read, W=Write, C=Clear only, -n= Value after RESET 

AD INT ENA. A/D Interrupt Enable. 

This bit controls the A/D module's ability to generate an interrupt. 



= Disables A/D interrupt. 

1 = Enables A/D interrupt. 

Bit 1 - AD INT FLAG. A/D Interrupt Flag. 

The A/D module sets this bit at the end of an A/D conversion. If this bit is set 
while the AD INT ENA bit is set, an interrupt request is generated. Clearing this 
flag clears pending A/D interrupt requests. This bit is cleared by the system 
RESET or by entering Halt or Standby mode. Software cannot set this bit. 

Bit 2 - AD READY. A/D Converter Ready. 

The A/D module sets this bit whenever a conversion is not in progress and the 
A/D is ready for a new conversion to start. Writing to this bit has no effect on 
its state. 

= Conversion in process. 

1 = Converter ready. 

Bits 3-7 - Reserved. Read data is indeterminate. 



11.4.3 Analog Conversion Data Register (ADDATA) 

The ADDATA register contains the digital result of the last A/D conversion. 

Analog Conversion Data Register (ADDATA) 
[Memory Address - 1072h] 

Bit#- 
P072 



7 


6 


5 


4 


3 


2 


1 





DATA7 


DATA6 


DATA5 


DATA4 


DATA3 


DATA2 


DATA1 


DATAO 



R-0 R-0 R-0 R-0 R-0 R-0 

R = Read, -n= Value after RESET 



R-0 



R-0 



The analog-to-digital conversion data is loaded into this register at the end of 
a conversion and remains until replaced by another conversion. 



11-13 



A/D Control Registers 



11.4.4 Analog Port E Data Input Register (ADIN) 

The ADIN register contains digital input data when one or more of the ANO 
through AN7 pins are used as digital ports. 



Analog Port E Data Input Register (ADIN) 
[Memory Address - 107Dh] 



Bit# 



P07D 



PORTE 
DATA 
AN 7 


PORTE 
DATA 
AN 6 


PORTE 
DATA 
AN 5 


PORTE 
DATA 
AN 4 


PORTE 
DATA 
AN 3 


PORTE 
DATA 
AN 2 


PORTE 
DATA 
AN 1 


PORTE 
DATA 
ANO 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R-0 



R = Read, -n= Value after RESET 



The ADIN register shows the data present at the pins configured for general 
purpose input instead of A/D channels. A bit is configured as a general pur- 
pose input if the corresponding bit of the port enable register is a 1. Pins 
configured as A/D channels are read as Os. Writing to this address has no 
effect. 

11.4.5 Analog Port E Input Enable Register (ADEN A) 

The ADENA register controls the function of the ANO through AN7 pins. 



Analog Port E Input Enable Register (ADENA) 
[Memory Address • 107Eh] 



Bit# 



P07E 



PORTE 
INPUT 
ENA 7 


PORT E 
INPUT 
ENA 6 


PORTE 
INPUT 
ENA 5 


PORT E 
INPUT 
ENA 4 


PORTE 
INPUT 
ENA 3 


PORT E 
INPUT 
ENA 2 


PORTE 
INPUT 
ENA1 


PORTE 
INPUT 
ENAO 



RW-0 



RW-0 RW-0 



RW-0 



RW-0 RW-0 RW-0 RW-0 



R = Read, W=Write, -n= Value after RESET 

The ADENA register individually configures the eight pins AN0-AN7 as either 
analog input channels or as general purpose input pins. 

= The pin becomes an analog input channel for the A/D converter. When 

the bit is 0, the corresponding bit in the ADIN register reads as a '0'. 

1 = Enables the pin as a general purpose input pin and its digital value can be 

read from the corresponding bit in the Port E Data Input Register. 



11-14 



A/D Control Registers 



7 


6 


5 


4 


3 


2 


1 





AD 
STEST 


AD 
PRIORITY 


AD 
ESPEN 




— 


— 


— 


— 



11.4.6 Analog Interrupt Priority Register (ADPRI) 

The ADPRI register selects the interrupt priority level of the A/D interrupt. 

Analog interrupt Priority Register (ADPRI) 
[Memory Address - 107Fli] 

Bit#- 
P07F 

RP-0 RP-0 RP-0 

R = Read, P=Privileged Write, -n= Value after RESET 

Bits 0-4 - Reserved. Read data is indeterminate. 

Bit 5 - AD ESPEIM. Emulator Suspend Enable. 

Normally, this bit has no effect. However, when using the XDS emulator to 
debug a program, this bit determines what happens to the A/D when the pro- 
gram is suspended by an action such as a hardware or software breakpoint. 

= When the emulator is suspended, the A/D continues to work until the 

current conversion is complete. 

1 = When the emulator is suspended, the A/D is frozen so that its state can 

be examined at the point that the emulator was suspended. The conver- 
sion data is indeterminate upon restart. 

Bit 6 - AD PRIORITY. A/D Interrupt Priority Select. 

This bit selects the priority level of the A/D interrupt. 

= A/D interrupt is a higher priority (level 1) request. 

1 = A/D interrupt is a lower priority (level 2) request. 

Bit 7 - AD STEST.This bit must be cleared (0) to ensure proper operation. 



11-15 



A/D Control Registers 



11-16 



Introduction 



TMS370 Family Devices 



CPU and MemorY Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface ISCI) Port 



Serial Peripheral Interface (SPI) Module Bm 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Infomiatlon 




Appendixes 



12. Assembly Language Instruction Set 

An assembly language instruction set is a symbolic language that presents 
binary machine code in a more readable form. The TMS370 family is sup- 
ported by a 73-function instruction set using a wide variety of addressing 
modes. 

This section includes the following topics: 

Section Page 

12.1 Instruction Operation 12-2 

12.2 Addressing Modes 12-3 

12.2.1 General Addressing Modes 12-4 

12.2.2 Extended Addressing Modes 12-10 

12.2.3 Additional Addressing Modes 12-17 

12.3 instruction Set Overview „ 12-18 

12.4 Instruction Set Descriptions 12-29 



12-1 



Assembly Language Instruction Set - Instruction Operation 



12.1 instruction Operation 

The assembly language Instruction set provides a convenient method of pro- 
gramming the CPU. Each TMS370 assembly language Instruction converts 
directly to one machine operation and consists of a function mnemonic fol- 
lowed by zero to three operands. The mnemonic specifies the type of CP op- 
eration while the operands Indicate where the CPU can find or store data 
during an Instruction execution. The type and combination of operands de- 
termine the actual opcode(s) for an instruction. The MOV instruction, for 
example, has 27 different options, each with it's own opcode. 

The typical syntax for TMS370 instructions consists of the function mnemonic 
followed by up to three operands. A typical two-operand Instruction Is shown 
below: 

MNEMONIC SOURCE DESTINATION 

ADD #9, R3 

The example above can be read as: add the value "9" to the contents of reg- 
ister number 3 and place the result back Into register number 3. The destina- 
tion, therefore, also serves as a second source in addition to being the final 
address of the result. This means that registers can be directly manipulated 
without having to use intermediate registers. It should be noted that this in- 
struction form differs from the "mnemonic- destination-source" arrangement 
used by some microprocessors. 

The following example shows how the instruction above might appear in a 
complete program line. 

LABEL INST. OPERANDS COMMENT 
XXXXX ADD R9,R3 ; comment 

There should be at least one space between each entry type. The LABEL and 
COMMENT entries are optional, and depending on which type of instruction 
is used, the OPERANDS column may be blank as well. 

The 73 instructions are supported by 245 opcodes providing flexible control 
of CPU program flow. Some instructions such as CLRC and TEST A share the 
same opcode to aid the user in comprehending all of the functions of an op- 
code. There are instructions that use 16-bit opcodes, depending on the type 
of instruction and/or the addressing mode used. Several bit manipulation in- 
structions are constructed by the assembler out of other instructions in order 
to simplify writing and enhance the readability of the program. 



12-2 



Assembly Language Instruction Set - Addressing Modes 



12.2 Addressing Modes 

Each TMS370 assembly language instruction Includes form zero to three op- 
erands. Each operand has an addressing mode. The addressing mode speci- 
fies how the CPU calculates the address of the data needed by the instruction. 
The power of the TMS370 is enhanced by the large number of addressing 
modes available. The table below shows the 14 addressing modes with a 
sample instruction and it's execution. 

Table 12-1 describes the addressing modes of the instruction set. 
Table 12-1. Addressing Modes 



ADDRESSING MODE 


EXAMPLE 


EXECUTION 


GENERAL: 

Implied 

Register 

Peripheral 

Immediate 

PC Relative 

Stack Pointer Relative 


LDSP 

MOV R5,R4 
MOV P025,A 
ADD#123,R3 
JMP offset 
M0V2(SP),A 


(B) ^ (SP) 
(0005) -^ (0004) 
(1025) -^ A 
123 + (03) -* (03) 
PCN + offset -^ (PC) 
(2 + (SP)) ^ (A) 


EXTENDED: 

Absolute Direct 
Absolute Indexed 
Absolute Indirect 
Absolute Offset Indirect 
Relative Direct 
Relative Indexed 
Relative Indirect 
Relative Offset Indirect 


MOV A,1 234 
MOV1234(B),A 
MOV @R4,A 
MOV12(R4),A 
JMPL 1234 
JMPL 1234(B) 
JMPL@R4 
JMPL12(R4) 


(A) -* (1234) 

(1234 + (B)) ^(A) 

((R3:R4)) -* (A) 

(12 + (R3:R4)) ->• (A) 

PCN + 1234 -^ (PC) 

PCN + 1234 + (B) -♦ (PC) 

PCN + (R3:R4) -^ (PC) 

PCN + 12 + (R3:R4) -+ (PC) 



NOTE: PCN = 16-bit address of next instruction, 
(x) = Contents of memory at address x. 
((x)) = Contents of memory location designated by contents at address x. 



As indicated in the table, there are 14 addressing modes divided into two 
classes: General, which uses an 8-bit addressing range, and Extended, which 
uses a 16-bit addressing range. A number of instructions use more than one 
addressing mode and several, such as the MOV instruction, are very versatile. 



12-3 



Assembly Language Instruction Set - Addressing Modes 



12.2.1 General Addressing Modes 

Instructions using the General Addressing modes have an eight bit range of 
operation, and therefore deal with the register file, peripheral file, or a nearby 
destination. The General Addressing modes are Implied, Register, Peripheral, 
Immediate, Program Counter Relative, and Stack Pointer Relative. Most of 
these modes can use any register as a source and/or destination, preventing 
the bottleneck found on other microprocessors that use only one or two reg- 
isters. 

12.2.1.1 Implied Addressing Mode 

In the Implied addressing mode, the instruction type alone determines where 
the data is to be found. The user does not have to specify the operands since 
they are inherently specified in the instruction. For example, the LDSP (Load 
Stack Pointer) instruction always copies the contents of the B register to the 
stack pointer register. Neither the source nor destination is explicitly stated 
because they are implied in the instruction itself. The instructions using the 
Implied addressing mode are the CLRC, LDSP, RTS, RTI, SETC, STSP,EINT, 
EINTH, and EINTL instructions. Figure 1 2-1 shows an example of the Implied 
addressing mode. 

LDSP 
CCB) -► SP] 



PROGRAM 




STACK 
POINTER 



Figure 12-1. Implied Operand Addressing Mode 



12-4 



Assembly Language Instruction Set - Addressing Modes 



12.2.1.2 Register Addressing Mode 

The Register file of the Ti\/IS370 consists of the the first 256 bytes of memory. 
In the Register addressing mode, instructions use a one byte value to specify 
an address (location) in the Register file. Any location in the Register file can 
be accessed in one memory cycle by instructions using this mode. (Extended 
addressing modes take two cycles to access the Register file). In Register file 
addressing, the operand is stated by Rn, where n is the 8-bit address number. 
The address number may be a decimal (0-255) or hexadecimal (0-OFF) 
number. Hexadecimal numbers require a leading zero, but no suffix. Registers 
RO and R1 of the register file are also known as registers A and B and are 
referenced as such by most instructions to reduce the size of the program. 
For example, the instruction MOV A,B uses one byte of code, while the 
instruction MOV R3,R4 uses three bytes of code. Any register can be 
specified by a symbol that has been equated to that register. This is illustrated 
in the following example: 



MOV R16,R011 ;move contents of OOlOh to OOllh 

CAT .EQU R16 ; Equate register 16 to symbol CAT 

DOG .EQU R17 ; Equate register 17 to symbol DOG 

MOV CAT, DOG ;move contents of OOlOh to 1020h 

Note that the entry ".EQU" is an assembler directive, not an assembly language 
instruction. For more information on assembler directives, refer to the TMS370 
Family Assembly Language Tools User's Guide. Figure 12-2 shows an ex- 
ample of the Register Addressing Mode. 

INC R23 



PROGRAM 



DATA 




NOTE: NUMBERS IN PARENTHESIS REPRESENT ORDER OF EXECUTION 
Figure 12-2. Register Addressing Mode 



12-5 



Assembly Language Instruction Set - Addressing Modes 



12.2.1.3 Peripheral Addressing Mode 

The Peripheral file of the TMS370 is allocated 256 bytes of memory. The 
Peripheral addressing mode is used for program control of the peripheral 
on-chip modules such as timers, interrupts, and I/O ports. A small amount 
of external memory can also be addressed as Peripheral file space from the 
TMS370Cx50. Each Peripheral file register is accessed by an 8-bit operand 
designated as Pn, with n being either a decimal (0-255) or hexidecimal (00- 
FF) number. Hexidecimal numbers require a leading zero but no suffix. The 
CPU assumes the most significant byte of a peripheral address to be 01 Oh. 
As described in Register file addressing, the Pn designation may be substi- 
tuted with a symbol using the equate (.EQU) assembler directive as shown in 
the example below. 



MOV R16,P020 ;move contents of OOlOh to 1020h 

CAT .EQU R16 ; Equate register 16 to symbol CAT 

DOG .EQU P32 ; Equate peripheral file 32 to symbol DOG 

MOV CAT, DOG ;move contents of OOlOh to 1020h 

The use of designated symbols is optional, of course, but is particularly suited 
for the register and peripheral addressing modes. Figure 1 2-3 shows an ex- 
ample of Peripheral-File addressing. 









MOV Po25. A 
[(P3)— *-A] 








PROGRAM 




PERIPHERAL 
REGISTER 




REGISTER 


ADDRESS 




ADDRESS 
.„„^^^ 1024h 




ADDRESS 
^^(A) 


^m 


7120h 


MOV Pp. A 


7121h 




7122h 


ADD 


^"'~'^1025h 
102eh 




-""""^ (B) 1 

2 
3 




7123h 













Figure 12-3. Peripheral Addressing Mode 



12-6 



Assembly Language Instruction Set - Addressing Modes 



12.2.1.4 Immediate Addressing Mode 

The Immediate Addressing mode uses a constant value as the operand imme- 
diately following the function mnemonic. This mode allows non-changing 
data to be incorporated into the instruction. The constant may be in the form 
of a decimal, hexadeciami, or symbolic label, but it is always preceded by the 
number sign (#). Hexadecimal numbers require both a leading numeric digit 
and the "h" suffix. Some examples of Immediate addressing are as follows: 



MOV #OFh,A 
MOV #(3*54) ,R022 
CNT .EQU 12 
ADD #CNT,R34 



;Store the value 15 in register A 
;Store the value 162 at location 022h 
;Equate 12 to sym,bol CNT 
;Add the value 12 to register 34, place 
;result in register 34. 



Figure 12-4 illustrates an instruction using the immediate addressing mode. 



ADDRESS 


PROGRAM 


(2) 


^ ADD #11, R45 


ADDRESS 
R43 

^-.^..^^^ R44 

— -^ R45 

R46 


DATA 


7123 


ADD n, Rfi 


12 


7124 
7125 


34 









NOTE: NUMBERS IN PARENTHESIS REPRESENT ORDER OF EXECUTION 

Figure 12-4. Immediate Addressing Mode 



12-7 



Assembly Language Instruction Set - Addressing Modes 



12.2.1.5 Program Counter Relative Addressing Mode 

The Program Counter Relative addressing mode adds an 8-bit signed offset 
to the address of the next instruction to produce the address of the successive 
instruction. The new address is placed in the program counter register. The 
range of the 8-bit offset is within 128 bytes before or 127 bytes after the in- 
struction following the jump. When labels are used, the signed offset is auto- 
matically calculated by the assembler. The PCN is the location (address) of the 
next instruction. Figure 12-5 illustrates object code generated by a Jump in- 
struction using the Program Counter Relative addressing mode. 



QPCN 



JMP LABEL 
OFFSET — * 



(PC)] 





PROGRAM 






ADDRESS 








' 7121h 


JMP 






5 


(OFFSET) 




7122h 






7123h 


ADD 


, , 




(PCN) 




7124h 


R3 






7125h 


R4 




7126h 


INC 




7127h 


R4 




7128h 


CLR 


(LABEL) 




7129h 


RB 














OFFSET = LABEL - PCN 
(PRECALCULATED BY ASSEMBLER) 



Figure 12-5. Program Counter Relative Addressing Mode 



12-8 



Assembly Language Instruction Set - Addressing Modes 



12.2.1.6 Stack Pointer Relative Addressing Mode 

The Stack Pointer Relative addressing mode adds an 8-bit signed constant to 
the existing 8-bit contents of the Stack Pointer Register. The result is trun- 
cated to an 8-bit address of the data. The second operand in the Stack Pointer 
Relative mode is always register A. This addressing mode is useful in access- 
ing arguments that are passed to a subroutine on the stack. The programmer 
must insure that the resulting address location is within the implemented reg- 
ister file, because overflows or underflows will execute without warning. Only 
the CMP and MOV instructions use this mode. An example of Stack Relative 
addressing is as follows: MOl/ -2(SP), A . In this case, the value of -2 plus the 
stack pointer equals the address of the data to be moved to register A. Figure 
12-6 illustrates this instruction operation. 

MOV -2 (SP), A 
[((SP) + n)— ^(aO 





PROGRAM 


STACK 
POINTER 




ADDRESS 




^HHpHi 




7123h 
7124h 


MOV n(SP), A 


63 
^ 1 "^ 


ADDRESS 
SQh 






7125h 


ADD 


^^^ 60h 


7126h 


XXX 


^^*-61h 






62h 








63h 



DATA 



REGISTER 

FILE 



ADDRESS 
,(A) 

(B) 1 

2 

3 



Figure 12-6. Stack Pointer Relative Addressing Mode 



12-9 



Assembly Language Instruction Set - Addressing Modes 



12.2.2 Extended Addressing Modes 

The Extended Addressing modes provide sophisticated addressing capabilities 
of arrays, tables, and routine addresses. These modes allow the program to 
access data from anywhere in the memory. Extended Addressing modes 
consist of four main types: Direct, Indirect, Indexed, and Offset Indirect. Each 
of these four types can be subdivided into Absolute and Relative modes for 
a total of eight Extended addressing modes. 

Extended Absolute addressing modes always use register A or the PC as one 
of the operands in generating a 16-bit address. The Extended Absolute ad- 
dressing modes are used only by the Branch (BR), CALL, Compare (CMP), 
and Move (MOV) instructions. The BR and CALL instructions use these 
modes exclusively. 

The Extended Relative addressing modes are similar to the Extended Absolute 
addressing modes but include the additional step of combining the operand 
with the program counter (PCN) value before placing the 16-bit address into 
the program counter. These modes are similar to the Program Counter Rela- 
tive mode. A 16-bit signed offset is used to calculate the successive instruc- 
tion address. The successive instruction address is calculated at execution 
time using the signed 16-bit offset according to the instruction's addressing 
mode. 

The Extended Relative Addressing modes are useful in relocatable code since 
operation is based on the differences in address position instead of the ad- 
dresses themselves. This makes the Extended Relative addressing modes well 
suited for high level languages that often use position independent code. 
Extended Relative addressing is used by the CALLR and JMPL instructions. 

12.2.2.1 Direct Addressing Modes 

Direct Addressing mode instructions use an address as the operand. The 16- 
bit address is written either as a constant value or a label, and immediately 
follows the opcode in the source code. The Absolute Direct addressing mode 
acts upon the address itself for operation as shown in Figure 12-7 below. 



12-10 



Assembly Language Instruction Set - Addressing Modes 





PROGRAM 


ADDRESS 
2232h 


_MOV 2233h, A_, 
(label) — ^(A)_ 

DATA 


ADDRESS 
(A) 

^^ (B) 1 

2 
3 


REGISTER 
FILE 




ADDRESS 


12 




7123h 


MOV label. A 
ADD 


^^ 2233h |gg^^^ 




7124h 


^ 2234h 
^ 2235h 


56 






7125h 


78 






7126h 

















Figure 12-7. Absolute Direct Addressing Mode 



The Relative Direct addressing mode (Figure 12-8) adds the address of the 
next instruction to the 16-bit operand to produce the address of the succes- 
sive instruction. If a label is used in the instruction, the assembler automat- 
ically calculates the offset to use as the operand. 



JMPL 5432h 
\_P<ZH + 5432 -*- 



(PC)] 



ADDRESS 
4130h 

4131h 

4132h 

4133h 



PROGRAM 



JMPL 




INC 



PCN 



PROGRAM 
COUNTER 



^I^^^H 



5432h 
•- + 4133h 
g565h 



Figure 12-8. Relative Direct Addressing Mode 



12-11 



Assembly Language Instruction Set - Addressing Modes 



12.2.2.2 Indexed Addressing Modes 

The Absolute Indexed Addressing mode generates a 1 6-bit address by adding 
the unsigned contents of the B Register to a 16-bit unsigned constant. The 
assembly language statement for the Indexed Addressing modes contain the 
direct memory address written as a 16-bit value or a label, followed by a B in 
parentheses: MOV 1234(B), or MOV LABEL(B). The MOV and CMP in- 
structions can use Absolute Indexed addressing to easily step through a small 
table or pick out a particular array value. The instructions CALL and BR can 
use this mode to execute code based on a decision table and the value in re- 
gister B. Figure 12-9 illustrates how the object code produced by an in- 
struction using this mode generates a 16-bit effective address. 

^ MOV 2233h (B). A _, 
[[{label + (B)) -^ (aO ■ 



PROGRAM 




(3) 



ADDRESS 
(A) 

^(B) 1 

2 


FILE 


^(4) 




ADDRESS 


DATA 


2235h 




2236h 


^^^^^^^^1 


2238h 











NOTE: NUMBERS IN PARENTHESIS REPRESENT ORDER OF EXECUTION 



Figure 12-9. Absolute Indexed Addressing Mode 



The Relative Indexed addressing mode includes the operation described above 
with the additional following step. The address of the next instruction is added 
to the sum of register B and the signed 16-bit constant offset, before pro- 
ducing the address of the successive instruction as shown in Figure 12-10. 



12-12 



Assembly Language Instruction Set - Addressing Modes 



JMPL 1236h (B) 
C1236 + (B) + PCN — ^ (PCO 



REGISTER 
FILE 



PROGRAM 
COUNTER 





PROGRAM 


ADDRESS 




7123h 


JMPL n (B) 


7124h 


■Qjd 


7125h 


^a 


7126h 


INC 







(1) 



PCN 



ADDRESS 

(A) 

(B) 1 



1236 (2) 

+ 7126 -* ).l 
6390h 



25 



lAL 



NOTE: NUMBERS IN PARENTHESIS REPRESENT ORDER OF EXECUTION 

Figure 12-10. Relative Indexed Addressing Mode 



12-13 



Assembly Language Instruction Set - Addressing Modes 



12.2.2.3 Indirect Addressing Modes 

Instructions using the Indirect addressing modes use the contents of a register 
pair as the 16-bit address of the data. The indirect Register File address is 
written as a register number (Rn) preceded by the commercial "at" (@) sym- 
bol. The LSB of the address is contained in Rn, and the MSB of the address 
is contained in the previous register (Rn-1 ). The TMS370 can use any register 
pair as an indirect register. Figure 12-11 shows how the Absolute Indirect 
addressing mode uses the register pair itself in the caculation. 

M0V(aR99, A _, 
QRn-l: Rn) —*- (aO 



RESS 


PROGRAM 


ADDRESS 
R097 

>. R098 

^i^099 

R09A 


REGISTER 
FILE 


ADDRESS 
2231 

-1 2232 

-i-^2233 

2234 


DATA 


ADDRESS 
(A) 1 

/(B) 2 

' 3 

4 


REGISTER 
FILE 


7123 


MOV@Rn, A 
ADD 


JH 




7124 


HH 


7125 




7126 

















Figure 12-11. Absolute indirect Addressing Mode 



The Relative Indirect addressing mode (Figure 12-12) adds the address of the 
next instruction to the register pair contents before obtaining the destination 
address. 



JMPL(aR099 
[;{Rd - 1: Rcj) + PCN -^ (POU 





PROGRAM 


ADDRESS 




7123h 


JMPL@Rjj 


7124h 


HEHl 


7125h 


ADD 







REGISTER 
FILE 



(1L 



ADDRESS 
R098 

R0g9 



W^ 



PCN 



(2) 



1024 

+ 7125 

8149 



(3) 
(4) 



PROGRAM 
COUNTER 



7>2ir 8149 



Figure 12-12. Relative Indirect Addressing Mode 



12-14 



Assembly Language Instruction Set - Addressing Modes 



12.2.2.4 Offset Indirect Addressing Modes 

The Offset Indirect addressing modes are similar to the Indirect addressing 
modes previously described. The Absolute Offset Indirect Addressing mode 
generates a 16-bit address by adding an 8-bit signed offset to an address 
taken from a register pair. Offset Indirect addressing is useful in stepping 
through tables or finding a particular value in a table by using two values to 
generate the address. Figure 12-13 illustrates how the object code produced 
by an instruction using the Offset Indirect Addressing mode generates 16-bit 
effective address. 

MOV 2 (R099). A 
C(n + (Rn - 1: Rn)) -*► (A)] 



PROGRAM 



ADDRESS 
(A) 




REGISTER 
FILE 



U,^ 


,(5) 








DATA 


62 
78 









NOTE: NUMBERS IN PARENTHESIS REPRESENT ORDER OF EXECUTION 



Figure 12-13. Absolute Offset Indirect Addressing Mode 



The Relative Offset Indirect addressing mode adds the address of the next in- 
struction with the sum of the 8-bit signed offset and the register pair before 
obtaining the destination address. 



12-15 



Assembly Language Instruction Set - Addressing Modes 



JMPL 56h {R010) 
Q PCN + 56h + (Rn-1 : Rn) - 



(PC)] 



ADDRESS 


PROGRAM 


(1) 


ADD 


7123h 
7124h 
7125h 


JMPL n (Rn) 
INC 




(2) 




7126h 


PCN 








^i;r 




+ 7126 
81A0h 



NOTE: NUMBERS IN PARENTHESIS REPRESENT ORDER OF EXECUTION 



Figure 12-14. Relative Offset Indirect Addressing Mode 



12-16 



Assembly Language Instruction Set - Addressing Modes 



12.2.3 Additional Addressing Modes 

There are some cases where the operation of an instruction does not fit into 
any of the previously described addressing modes. The individual instruction 
description can be referenced for a list of that instruction's operations. 



12-17 



Assembly Language instruction Set - Overvie\A/ 



12.3 Instruction Set Overview 

The following tables provide a listing of the instruction set symbols, a listing 
of the instruction set itself including pertinent characteristics, and an 
opcode/instruction map. 



Table 12-2. TMS370 Symbol Definitions 



SYMBOL 


DEFINITION 


SYMBOL 


DEFINITION 


A 


Register A or RO in Register File 


B 


Register B or R1 in Register File 


Rn 


Register n of Register File 


Pn 


Register n of Peripheral File (0 ^ n 
<. 255) 


s 


Source operand 


d/D 


Destination operand (8-bit/1 6-bit) 


Rs 


Source register in Register File 


Ps 


Source register in Peripheral File 
(0 ^ s < 255) 


Rd 


Destination register in Register File 


Pd 


Destination register in Peripheral File 
(0 ^ d :S 255) 


Rps 


Source register pair 


Rpd 


Destination register pair 


iop8 


8-bit Immediate operand 


iop16 


16-bit Immediate operand 


offS 


8-bit Signed Offset 


off 16 


16-bit Signed Offset 


Rp 


Register pair 


label 


16-bit label 


ST 


Status Register 


SP 


Stack Pointer 


PC 


Program Counter 


PCN 


16-bit address of next instruction 


# 


Immediate operand 


@ 


Indirect addressing operand 


MSB 


Most significant byte 


LSB 


Least significant byte 


MSb 


Most significant bit 


LSb 


Least significant bit 


end 


Condition 


() 


Contents of 


-♦ 


Is assigned to 


*- 


Becomes equal to 


[] 


Indicates an optional entry. 
The brackets themselves are not 
entered. 


< > 


Indicates an entry that must be typed 
in. For example, <label> indicates that 
a label must be entered. The brackets 
themselves are not entered. 


C 


Carry flag 


N 


Sign flag 


V 


Overflow/borrow flag 


Z 


Zero flag 


XADDR 


16-bit address 


name 


symbol defined for a bit 


Rname 


symbol defined register bit 


Pname 


symbol defined peripheral bit 



Table 12-3 lists all instruction formats, opcodes, byte lengths, cycles/instruc- 
tion, operand types, status bits affected, and an operational description. 



12-18 



Assembly Language Instruction Set - Overvie\AA 



Table 12-3. TMS370 Family Instruction Overview 



MNEMONIC 


OPCODE 


BYTES 


CYCLES 


STATUS 


OPERATION DESCRIPTION 










tc 


C N Z V 




ADC 


B,A 


69 


1 


8 


X X X X 


(s) + (d) + (C) -^ (d) 




Rs,A 


19 


2 


7 




Add the source, destination, and carry bit 




Rs,B 


39 


2 


7 




together. Store at the destination address. 




Rs,Rd 


49 


3 


9 








#iop8,A 


29 


2 


6 








#iop8,B 


59 


2 


6 








#iop8,Rd 


79 


3 


8 






ADD 


B,A 


68 


1 


8 


X X X X 


(s) + (d) - (d) 




Rs,A 


18 


2 


7 




Add the source and destination operands at 




Rs,B 


38 


2 


7 




the destination address. 




Rs,Rd 


48 


3 


9 








#iop8,A 


28 


2 


6 








#iop8,B 


58 


2 


6 








#iop8,Rd 


78 


3 


8 






AND 


A,Pd 


83 


2 


9 


X X 


(s) AND (d) -♦ (d) 




B,A 


63 


1 


8 




AND the source and destination operands 




B,Pd 


93 


2 


9 




together and store at the destination 




Rs,A 


13 


2 


7 




address. 




Rs,B 


33 


2 


7 








Rs,Rd 


43 


3 


9 








#iop8,A 


23 


2 


6 








#iop8,B 


53 


2 


6 








#iop8,Rd 


73 


3 


8 








#iop8,Pd 


A3 


3 


10 






BR 


label 


8C 


3 


9 


. . . . 


XADDR -♦ (PC) 




@Rp 


9C 


2 


8 




Branch to the destination address. 




label(B) 


AC 


3 


11 








off8(Rp) 


F4EC 


4 


16 






(1) 










X X 


If (s) AND (d) ^ 0, 


BTJO 


A,Pd,off8 


86 


3 


10 




then PCN + offset -» (PC) 




B,A,off8 


66 


2 


10 




If the AND of the source and destination 




B,Pd,off8 


96 


3 


10 




operands ^ (corresponding 1 bits) 




Rs,A,off8 


16 


3 


9 




The PC will add the offset, and the 




Rs,B,off8 


36 


3 


9 




jump will be taken. 




Rs,Rd,off8 


46 


4 


11 








#iop8,A,off8 


26 


3 


8 








#iop8,B,off8 


56 


3 


8 








#iop8,Rd,off8 


76 


4 


10 








#iop8,Pd,off8 


A6 


4 


11 






(1) 










X X 


If (s) AND (notd) ,4 


BTJZ 


A,Pd,off8 


87 


3 


10 




then (PCN) + offset -» (PC) 




B,A,off8 


67 


2 


10 




destination operands ^ (jump if 




B,Pd,off8 


97 


3 


10 




corresponding 1 and bits). The PC 




Rs,A,off8 


17 


3 


9 




will add the offset and the jump 




Rs,B,off8 


37 


3 


9 




will be taken. 




Rs,Rd,off8 


47 


4 


11 








#iop8,A,off8 


27 


3 


8 








#iop8,B,off8 


57 


3 


8 








#iop8,Rd,off8 


77 


4 


10 








#iop8,Pd,off8 


A7 


4 


11 







Note: 1 .Add two to cycle count if jump is taken. 

Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on results. 

Status Bit not affected. 



12-19 



Assembly Language Instruction Set - Overview 



Table 12-3. TMS370 Family Instruction Overview (Continued) 



MNEMONIC 


3PCODE 


BYTES 


CYCLES 


STATUS 


OPERATION DESCRIPTION 










tc 


C N Z V 




CALL 


label 


8E 


3 


13 


. . - . 


Push PC MSB, PC LSB, 




@Rp 


9E 


2 


12 




XADDR -♦ (SP) 




label(B) 


AE 


3 


15 








off8(Rp) 


F4 EE 


4 


20 






CALLR 


label 


8F 


3 


15 


. . . - 


Call Relative 




@Rp 


9F 


2 


14 




Push PC MSB, PC LSB, 




label(B) 


AF 


3 


17 




PCN + (XADDR) -> (PC) 




off8(Rp) 


F4 EF 


4 


22 






CLR 


A 


B5 


1 


8 


10 


-> (d) 




B 


C5 


1 


8 




Clear the destination operand. 




Rd 


D5 


2 


6 






CLRC 




BO 


1 


9 


X X 


O-^(C) 

Clears the carry bit. 


CMP 


label,A 


8D 


3 


11 


X X X X 


Compare; (d) - (s) computed. 




@Rp,A 


9D 


2 


10 




Set flags on the result of the source 




label(B),A 


AD 


3 


13 




operand subtracted from the destination 




off8(Rp),A 


F4 ED 


4 


18 




operand. Operands are not affected by 




off8(SP),A 


F3 


2 


8 




operation. 




B,A 


6D 


1 


8 








Rs,A 


ID 


2 


7 








Rs,B 


3D 


2 


7 








Rs,Rd 


4D 


3 


9 








#iop8,A 


2D 


2 


6 








#iop8,B 


5D 


2 


6 








#iop,Rd 


7D 


3 


8 






CMPBIT 


Rname 


75 


3 


8 


X X 


Complement Bit; invert the bit 




Pname 


A5 


3 


10 






COMPL 


A 


BB 


1 


8 


X X X 


Two's complement; 




B 


CB 


1 


8 




OOh - (s) -» (d) 




Rd 


DB 


2 


10 






DAC 


B,A 


6E 


1 


10 


X X X X 


(s) + (d) + (C) -* (d) (BCD) 




Rs,A 


IE 


2 


9 




The source, destination, and the carry bit 




Rs,B 


3E 


2 


9 




are added, and the BCD sum is stored at tht 




Rs,Rd 


4E 


3 


11 




destination address. 




#iop8,A 


2E 


2 


8 








#iop8,B 


5E 


2 


8 








#iop8,Rd 


7E 


3 


10 






DEC 


A 


B2 


1 


8 


X X X X 


(d) - 1 -* (d) 




B 


C2 


1 


8 




Decrement destination operand by 1. 




Rd 


D2 


2 


6 






DINT 




FOOO 


2 


6 





-♦ (ST) (global interrupt enable bits) 
-> IE1,0 -► IE2. 



Note: Add two to cycle count if jump is taken. 

Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on results. 

Status Bit not affected. 



12-20 



Assembly Language Instruction Set - Overvie\A/ 



Table 12-3. TMS370 Family Instruction Overview (Continued) 



MNEMONIC 


DPCODE 


BYTES 


CYCLES 

to 


STATUS 
C N Z V 


OPERATION DESCRIPTION 


DIV Rs,A 


F4F8 


3 


47-63 
14 


X X 
1111 


A:B/Rs-A(=quo),B{= REM) 
Integer divide, 16 
by 8 bit. 
Detected overflow 


(1) 

DJNZ A,off8 
B,off8 
Rd.offS 


BA 
CA 
DA 


2 
2 
3 


10 

10 

8 




(d) - 1 -^ (d); 

If (d) ^ 0, then PCN + offset -^ (PC) 

Decrement and jump if not 0. 


DSB B,A 
Rs,A 
Rs,B 
Rs,Rd 
#iop8,A 
#iop8,B 
#iop8,Rd 


6F 
IF 
3F 
4F 
2F 
5F 
7F 


1 
2 
2 
3 
2 
2 
3 


10 
9 
9 

11 
8 
8 

10 


X X X X 


(d)-(s)-1 + (C) -* (d) (BCD) 
The source operand is subtracted from the 
destination; this sum is then reduced by 1 
and the carry bit is then added to it. The 
result is stored as a BCD number. 


El NT 


FOOC 


2 


6 





OCh -^ (ST) (global interrupt enable bit) 
1 -* IE1, 1 -> IE2. 


El NTH 


F0 04 


2 


6 





04h -» (ST) (high priority global 
interrupt enable bit). 
1 -► IE1,0-» IE2 


EINTL 


F0 08 


2 


6 





08h -♦ (ST) (low priority global 
interrupt enable bit) 
-♦ IE1, 1 -» IE2 


IDLE 


F6 


1 


6 


- " ■ ■ 


(PC) -^ (PC) until interrupt 

(PC) + 1 -» (PC) after return from interrupt 

Stops pC execution until an interrupt 


INC A 
B 
Rd 


B3 
C3 
D3 


1 
1 
2 


8 
8 
6 


X X X X 


(d) + 1 - (d) 

Increase the destination operand by 1 . 


INCW #off8,Rp 


70 


3 


11 


X X X X 


(Rp) + offset -♦ (Rp) 

Add 8-bit signed offset to register pair. 


INV A 
B 
Rd 


B4 
C4 
D4 


1 
1 
2 


8 
8 
6 


X X 


NOT(d) -* (d) 

1's complement the destination operand. 


(1) 

JBITO Rd.offS 
Pd,off8 


77 
A7 


4 
4 


10 
11 


X X 


Jump If Bit = 


(1) 

JBIT1 Rd,off8 
Pd,off8 


76 
A6 


4 
4 


10 
11 


X X 


Jump If Bit = 1 


J MP off 8 


00 


2 


7 


.... 


PCN + off8 -» (PC) 

Jump unconditionally using an 8-bit offset. 



Note: 1 . Add two to cycle count if jump is taken. 

Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on results. 

Status Bit not affected. 



12-21 



Assembly Language Instruction Set - OvervleAAA 



Table 12-3. TMS370 Family Instruction Overview (Continued) 



MNEMONIC 


3PC0DE 


BYTES 


CYCLES 


STATUS 


OPERATION DESCRIPTION 










tc 


C N Z V 




JMPL 


label 


89 


3 


9 




PCN + D -► (PC) 




@Rp 


99 


2 


8 




Jump unconditionally using 




label(B) 


A9 


3 


11 




a 16-bit offset 




off8(Rp) 


F4 E9 


4 


16 






(1) 














Jcnd 










. . . 


- Conditional jump 




JC 


03 


2 


5 




Carry 




JEQ 


02 


2 


5 




Jump Equal 




JG 


OE 


2 


5 




Greater Than, signed 




JGE 


OD 


2 


5 




Greater Than or Equal, signed 




JHS 


OB 


2 


5 




Higher or Same, unsigned 




JL 


09 


2 


5 




Less Than, signed 




JLE 


OA 


2 


5 




Less Than or Equal, signed 




JLO 


OF 


2 


5 




Lower Value, unsigned 




JN 


01 


2 


5 




Negative, signed 




JNC 


07 


2 


5 




No Carry 




JNE 


06 


2 


5 




Jump Not Equal 




JNV 


OC 


2 


5 




No Overflow, signed 




JNZ 


06 


2 


5 




Not Zero 




JP 


04 


2 


5 




Positive, signed 




JPZ 


05 


2 


5 




Positive or Zero, signed 




JV 


08 


2 


5 




Overflow, signed 




JZ 


02 


2 


5 




Zero 


LDSP 




FD 


1 


7 


- _ - - 


(B) - (SP) 

Load stack pointer with contents 

of register B. 


LOST 


#iop8 


FO 


2 


6 


X X X X 


(d) -* (ST) 
Load ST Register 



Note: 1 .Add two to cycle count if jump is taken. 

Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on results. 

Status Bit not affected. 



12-22 



Assembly Language Instruction Set - Overvie\AA 



Table 12-3. TMS370 Family Instruction Overview (Continued) 



r 


MNEMONIC 


DPCODE 


BYTES 


CYCLES 

to 


STATUS 
C N 2 V 


OPERATION DESCRIPTION 


MOV 


A,B 


CO 


1 


9 


X X 


(s) -* (d) 




A,Rd 


DO 


2 


7 




Replace the destination operand with the 




A,Pd 


21 


2 


8 




source operand. 




AJabel 


8B 


3 


10 








A,@Rp 


9B 


2 


9 








A,label(B) 


AB 


3 


12 








A,off8(Rp) 


F4 EB 


4 


16 








A,off8(SP) 


F2 


2 


7 








Rs,A 


12 


2 


7 








Rs,B 


32 


2 


7 








label.A 


8A 


3 


10 








@Rp,A 


9A 


2 


9 








label(B),A 


AA 


3 


12 








off8(Rp),A 


F4 EA 


4 


17 








off8(SP),A 


F1 


2 


7 








B,A 


62 


1 


8 








B,Rd 


D1 


2 


7 








B,Pd 


51 


2 


8 








Rs.Rd 


42 


3 


9 








Rs,Pd 


71 


3 


10 








Ps,A 


80 


2 


8 








Ps,B 


91 


2 


8 








Ps.Rd 


A2 


3 


10 








#iop8,A 


22 


2 


6 








#iop8,B 


52 


2 


6 








#iop8,Rd 


72 


3 


8 








#iop8,Pd 


F7 


3 


10 






MOVWRps,Rpd 


98 


3 


12 


X X 


(s) -^ (Rpd) 




#iop16,Rpd 


88 


4 


13 




Copy the source register word to the 




#iop16(B),Rp( 


A8 


4 


15 




destination register pair. 




off8(Rs),Rpd 


F4E8 


5 


20 






MPY 


B,A 


6C 


1 


47 


X X 


(s) X (d) - (A:B) 




Rs,A 


1C 


2 


46 




Multiply the source and destination oper- 




Rs,B 


3C 


2 


46 




ands, store the result in Registers A 




Rs,Rd 


4C 


3 


48 




(MSB) and B (LSB). 




#iop8,A 


2C 


2 


45 








#iop8,B 


5C 


2 


45 








#iop8,Rn 


7C 


3 


47 






NOP 


FF 


1 


7 


.... 


No operation 


OR 


A,Pd 


84 


2 


9 


X X 


(s) OR (d) -^ (d) 




B,A 


64 


1 


8 








B,Pd 


94 


2 


9 








Rs,A 


14 


2 


7 




Logically OR the source and destination 




Rs,B 


34 


2 


7 




operands, and store the results at the desti- 




Rs,Rd 


44 


3 


9 




nation address. 




#iop8,A 


24 


2 


6 








#iop8,B 


54 


2 


6 








#iop8,Rd 


74 


3 


8 








#iop8,Pd 


A4 


3 


10 







Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on result. 
- Status Bit not affected. 



12-23 



Assembly Language Instruction Set - Overvie\A/ 



Table 12-3. TMS370 Family Instruction Overview (Continued) 



MNEMONIC 


DPCODt 


BYTES 


CYCLES 

to 


STATUS 
C N Z V 


OPERATION DESCRIPTION 


POP A 
B 

Rd 
ST 


B9 
C9 
D9 
FC 


2 


9 
9 

7 
8 


X X 
X X X X 


((SP)) -» (d) . 
(SP) -1 - (SP) 


PUSH A 
B 

Rd 
ST 


B8 
C8 
D8 
FB 


2 


9 
9 

7 
8 


X X 


(SP) + 1 -» (SP) 

(s) -* ((SP)) 
Copy the operand onto the stack. 
Copy the Status Register onto the Stack 


RL A 
B 
Rd 


BE 
CE 
DE 


2 


8 
8 
6 


X X X 


Bit(n) -^ Bit(n + 1) 
Bit(7) -* Bit(O) and Carry 


RLC A 
B 
Rd 


BF 
CF 
DF 


2 


8 
8 
6 


X X X 


Bit(n) -» Bit(n + 1) 
Carry -> Bit(O) 
Bit(7) -•• Carry 


RR A 
B 
Rd 


BC 
CC 
DC 


2 


8 
8 
6 


X X X 


Bit(n + 1) -> Bit(n) 

Bit(O) -» Bit(7) and Carry 


RRC A 
B 
Rd 


BD 
CD 
DD 


2 


8 
8 
6 


X X X 


Bit(n + 1) -► Bit(n) 
Carry -* Bit(7) 
Bit(O) -* Carry 


RTI 


FA 




12 


X X X X 


Pop PCL, PCH, POP ST 
Return From Interrupt 


RTS 


F9 




9 


.... 


Pop PCL, PCH 


SBB B,A 
Rs,A 
Rs,B 
Rs,Rd 
#iop8,A 
#iop8,B 
#iop8,Rd 


6B 
IB 
3B 
4B 
2B 
5B 
7B 


2 
2 
3 
2 
2 
3 


8 

7 
7 
9 
6 
6 
8 


X X X X 


(d) - (s) - 1 + (C) -» (d) 

Subtract with borrow. 

Destination minus source minus 1 plus 

carry; stored at the destination address. 


SBITO Rd 
Pd 


73 
A3 


3 
3 


8 
10 


X X 


Set Bit to 


SBIT1 Rd 
Pd 


74 
A4 


3 
3 


8 
10 


X X 


Set Bit to 1 


SETC 


F8 


1 


7 


10 10 


Axh -♦ (ST) Set the carry bit. 
IE1 and IE2 unchanged. 



Note: 1 .Add two to cycle count if jump is taken. 

Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on results. 
- Status Bit not affected. 



12-24 



Assembly Language Instruction Set - Overvie\A^ 



Table 12-3. TMS370 Family Instruction Overview (Concluded) 



MNEMONIC 


DPCODE 


BYTES 


CYCLES 


STATUS 


OPERATION DESCRIPTION 










to 


C N Z V 




STSP 




FE 


1 


8 


- - - - 


(SP) -* (B) 

Copy the SP into Register B. 


SUB 


B,A 


6A 


1 


8 


X X X X 


(d) - (s) ^ (d) 




Rs,A 


lA 


2 


7 




Store the destination operand minus the 




Rs,B 


3A 


2 


7 




source operand into the destination. 




Rs,Rd 


4A 


3 


9 








#iop8,A 


2A 


2 


6 








#iop8,B 


5A 


2 


6 








#iop8,Rd 


7A 


3 


8 






SWAP 


A 


B7 


1 


11 


X X 


s(7-4,3-0) - d(3-0,7-4) 




B 


C7 


1 


11 




Swap the operand's hi and lo nibbles. 




Rd 


D7 


2 


9 






TRAP 


n 


EF-EO 


1 


14 


_ _ _ _ 


Vector n -♦ (PC), n = -» 1 5 
Trap to Subroutine; Push PCN 
Trap = EF 


TST 


A 


BO 


1 


9 


X X 


Test; Set flags from register. 




B 


C6 


1 


10 






XCHB 


A 


B6 


1 


10 


X X 


(B) ^-» (Rn) 




B 


C6 


1 


10 




Swap the contents of Register B with (Rn). 




Rd 


D6 


2 


8 






XOR 


A,Pd 


85 


2 


9 


X X 


(s) XOR (d) -» (d) 




B,A 


65 


1 


8 




Logically exclusive OR the source and 




B,Pd 


95 


2 


9 




destination operands, store at the 




Rs,A 


15 


2 


7 




destination address. 




Rs,B 


35 


2 


7 








Rs,Rd 


45 


3 


9 








#iop8,A 


25 


2 


6 








#iop8,B 


55 


2 


6 








#iop8,Rd 


75 


3 


8 








#iop8,Pd 


A5 


3 


10 







Note: 1 .Add two to cycle count if jump is taken. 

Legend : 

Status Bit always cleared. 

1 Status Bit always set. 

X Status Bit cleared or set on results. 
- Status Bit not affected. 



12-25 



Assembly Language Instruction Set - Overvie\AA 



"Table 12-4 provides an opcode-to-instruction cross reference of all 73 in- 
structions and 245 opcodes of the TMS370 instruction set. To check the in- 
struction of a known opcode, locate the left (high) digit across the top or 
bottom of thetable, then find the right (low) digit along the side of the table. 
The intersection contains the instruction mnemonic, operands, and byte/cycle 
particular to that opcode. Some opcodes, such as BO, are shared by two in- 
structions, in which case both mnemonics are shown along with the 
byte/cycles count. 



12-26 



Assembly Language Instruction Set - Overview 



Table 12-4. TMS370 Family Opcode/Instruction Map 



JMP 
ra 
2/7 














INCW 
#n.Rd 
3/11 


MOV 
Ps.A 
2/8 






CLRC 

TSTA 

1/9 


MOV 
A,B 
1/9 


MOV 
A.Rd 
2/7 


TRAP 
15 

1/14 


LOST 
n 

2/6 


JN 
ra 
2/5 




MOV 
A,Pd 
2/8 






MOV 
B.Pd 
2/8 




MOV 
Rs.Pd 
3/10 




MOV 
Ps.B 
2/7 








MOV 
B.Rd 
2/7 


TRAP 

14 
1/14 


MOV 

n(SP),A 

2/7 


JZ 
ra 

2/5 


MOV 
Rs,A 
2/7 


MOV 
#n.A 
2/6 


MOV 
Rs,B 
2/7 


MOV 
Rs.Rd 
3/9 


MOV 
#n,B 
2/6 


MOV 
B.A 
1/8 


MOV 

#n.Rd 

3/8 






MOV 
Ps.Rd 
3/10 


DEC 
A 
1/8 


DEC 

B 

1/8 


DEC 
Rn 
2/6 


TRAP 

13 
1/14 


MOV 

A.n(SP) 

2/7 


JC 

ra 
2/5 


AND 
Rs.A 
2/7 


AND 
#n,A 
2/6 


AND 
Rs.B 
2/7 


AND 

Rs.Rd 

3/9 


AND 
#n,B 
2/6 


AND 
B.A 

1/8 


AND 

#n.Rd 

3/8 


AND 
A.Pd 
2/9 


AND 
B.Pd 
2/9 


AND 
#n.Pd 
3/10 


INC 
A 
1/8 


INC 

B 
1/8 


INC 
Rn 
2/6 


TRAP 

12 
1/14 


CMP 

n(SP).A 

2/8 


JP 
ra 
2/5 


OR 
Rs.A 
2/7 


OR 

#n.A 
2/6 


OR 
Rs.B 
2/7 


OR 
Rs.Rd 
3/9 


OR 

#n,B 
2/6 


OR 
B.A 
1/8 


OR 

#n,Rd 
3/8 


OR 
A,Pd 
2/9 


OR 
B.Pd 
2/9 


OR 
#n,Pd 
3/10 


INV 
A 
1/8 


INV 

B 

1/8 


INV 
Rn 
2/6 


TRAP 

11 
1/14 


extend 

inst.2 

opcodes 


JPZ 
ra 
2/5 


XOR 
Rs.A 
2/7 


XOR 

#n,A 
2/6 


XOR 
Rs.B 
2/7 


XOR 

Rs.Rd 
3/9 


XOR 

#n.B 
2/6 


XOR 
B.A 
1/8 


XOR 

#n.Rd 
3/8 


XOR 
A.Pd 
2/9 


XOR 
B.Pd 
2/9 


XOR 

#n,Pd 
3/10 


CLR 
A 
1/8 


CLR 
B 

1/8 


CLR 
Rn 
2/6 


TRAP 
10 

1/14 




JNZ 
ra 
2/5 


BTJO 
Rs.A 
3/9 


BTJO 

#n,A 
3/8 


BTJO 
B.Rd 
3/9 


BTJO 
Rs.Rd 

4/11 


BTJO 

#n.B 
3/8 


BTJO 
B.A 
2/10 


BTJO 

#n,Rd 
4/10 


BTJO 
A,Pd 
3/11 


BTJO 
B.Pd 
3/10 


BTJO 

#n.Pd 
4/11 


XCHB 

A 
1/10 


XCHB 

TESTB 

1/10 


XCHB 
Rn 
2/8 


TRAP 

9 
1/14 


IDLE 
1/6 


JNC 
ra 
2/5 


BTJZ 
Rs.A 
3/9 


BTJZ 

#n,A 
3/8 


BTJZ 
Rs.B 
3/9 


BTJZ 
Rs.Rd 
4/11 


BTJZ 
#n.B 
3/8 


BTJZ 
B.A 
2/10 


BTJZ 

#n.Rd 
4/10 


BTJZ 
A.Pd 
3/10 


BTJZ 
B.Pd 
3/10 


BTJZ 
#n,Pd 
4/11 


SWAP 

A 
1/11 


SWAP 

B 
1/11 


SWAP 
Rn 
2/9 


TRAP 
8 

1714 


MOV 
#n,Pd 
3/10 


JV 
ra 
2/5 


ADD 
Rs.A 
2/7 


ADD 

#n,A 
2/6 


ADD 
Rs.B 
2/7 


ADD 
Rs.Rd 
3/9 


ADD 

#n,B 
2/6 


ADD 
B,A 

1/8 


ADD 

#n,Rd 
3/8 


MOVW 

#16.Rd 

4/13 


MOVW 
Rs.Rd 
3/12 


MOVW 

#16{B),Rd 

4/15 


PUSH 
A 

1/9 


PUSH 

B 

1/9 


PUSH 
Rs 
2/7 


TRAP 

7 
1/14 


SETC 
1/7 


JL 
ra 
2/5 


ADC 
Rs.A 
2/7 


ADC 

#n,A 
2/6 


ADC 
Rs.B 
2/7 


ADC 

Rs.Rd 

3/9 


ADC 

#n.B 
2/6 


ADC 
B.A 
1/8 


ADC 

#n.Rd 
3/8 


JMPL 
lab 
3/9 


JMPL 
@Rd 
2/8 


JMPL 
lab(B) 
3/10 


POP 
A 
1/9 


POP 
B 
1/9 


POP 
Rd 
2/7 


TRAP 
6 

1/14 


RTS 
1/9 


JLE 
ra 
2/5 


SUB 
Rs.A 
2/7 


SUB 

#n,A 
2/6 


SUB 
Rs.B 
2/7 


SUB 
Rs.Rd 
3/9 


SUB 

#n,B 
2/6 


SUB 
B.A 
1/8 


SUB 

#n,Rd 
3/8 


MOV 
lab.A 
3/10 


MOV 

@Rs.A 

2/9 


MOV 

lab(B),A 

3/12 


DJNZ 
A.ra 
2/10 


DJNZ 
B.ra 
2/10 


DJNZ 
Rn.ra 
3/8 


TRAP 

5 
1/14 


RTI 
1/12 


JHS 
ra 
2/5 


SBB 
Rs.A 
2/7 


SBB 
#n,A 
2/6 


SBB 
Rs.B 
2/7 


SBB 

Rs.Rd 

3/9 


SBB 

#n,B 
2/6 


SBB 
B.A 
1/8 


SBB 

#n.Rd 
3/8 


MOV 
A.lab 
3/10 


MOV 

A.@Rd 

2/9 


MOV 

A.lab(B) 

3/12 


COMPL 
A 
1/8 


COMPL 

B 

1/8 


COMPL 

Rn 

2/10 


TRAP 

12 
1/14 


PUSH 
ST 
1/8 


JNV 
ra 
2/5 


MPY 
Rs.A 
2/46 


MPY 
#n,A 
2/45 


MPY 
Rs.B 
2/46 


MPY 
Rs.Rd 
3/48 


MPY 
#n.B 
2/45 


MPY 
B.A 
1/47 


MPY 
#n.Rs 
3/47 


BR 
lab 
3/9 


BR 

@Rd 
2/8 


BR 
lab(B) 
3/11 


RR 
A 

1/8 


RR 

B 

1/8 


RR 
Rn 
2/6 


TRAP 

3 
1/14 


POP 
ST 

1/8 


JGE 

ra 
2/5 


CMP 
Rs.A 
2/7 


CMP 

#n,A 
2/6 


CMP 
Rs.B 
2/7 


CMP 
Rs.Rd 
3/9 


CMP 
#n,B 
2/6 


CMP 
B,A 
1/8 


CMP 

#n.Rd 

3/8 


CMP 
lab.A 
3/11 


CMP 
@Rs.A 
2/10 


CMP 

lab(B),A 

3/13 


RRC 
A 
1/8 


RRC 
B 

1/8 


RRC 
Rn 
2/6 


TRAP 
2 

1/14 


LDSP 
1/7 


JG 
ra 
2/5 


DAC 
Rs.A 
2/9 


DAC 

#n,A 
2/8 


DAC 
Rs.B 
2/9 


DAC 
Rs.Rd 
3/11 


DAC 

#n,B 
2/8 


DAC 
B,A 
1/10 


DAC 

#n.Rd 
3/10 


CALL 
lab 
3/13 


CALL 
@Rd 
2/12 


CALL 
lab(B) 
3/15 


RL 
A 
1/8 


RL 

B 

1/8 


RL 
Rn 
2/6 


TRAP 

1 
1/14 


STSP 

1/8 


JLO 
ra 
2/5 


DSB 
Rs.A 
2/9 


DSB 

#n,A 
2/8 


DSB 
Rs.B 
2/9 


DSB 
Rs.Rd 
3/11 


DSB 
#n.B 
2/8 


DSB 
B.A 

1/10 


DSB 
#n,Rd 
3/10 


CALLR 
lab 
3/15 


CALLR 
@Rd 
2/14 


CALLR 
lab(B) 
3/17 


RLC 
A 

1/8 


RLC 

B 
1/8 


RLC 
Rn 
2/6 


TRAP 


1/14 


NOP 
1/7 



Note: 

All conditional jumps (opcodes 01 -OF), BTJO, and BTJZ instructions use 
two additional cycles if the branch is taken. The BTJO and BTJZ in- 
structions have a relative address as the last operand. 



12-27 



Assembly Language Instruction Set - Overview 



Second byte of two-byte instructions (F4xx): 





E 


F 


8 


MOVW 
n(Rn) 
4/15 


DIV 

Rn,A 

3/14-63 


9 


JIVIPL 
n(Rn) 
4/16 




A 


MOV 

r)(Rn),A 

4/17 




B 


MOV 

A,n(Rn) 

4/16 




C 


BR 
n(Rn) 
4/16 




D 


CMP 
n(Rn) 
4/18 




E 


CALL 
n(Rn) 
4/20 




F 


CALLEF 
n(Rn) 
4/22 





ra - relative address 
Rn - Register 

Rs - Register containing source byte 
Rd - Register containing destination byte 
Ps - Peripheral register containing source byte 
Pd - Peripheral register containing destination byte 
Pn - Peripheral register 
n - Immediate 8-bit number 
#16 - Immediate 16-bit number 
lab - 16-bit label 



12-28 



Assembly Language Instruction Set - Descriptions 



12.4 Instruction Set Descriptions 

The TMS370 instruction set contains 73 instructions covered by 245 unique 
opcodes. Each operation has an associated opcode. Some instructions, in- 
cluding those using the Offset Indirect addressing mode, have 1 6-bit (or dual) 
opcodes. In two cases, an opcode is shared by two instructions. This is to 
aid the programmer in understanding the operation associated with the op- 
code, as well as enhance the readablity of the source code. The following 
pages contain the individual instruction descriptions. The instructions are in 
alphabetical order according to the function mnemonic. 



12-29 



ADC 



Add with Carry 



ADC 



Syntax 


[<label>] ADC 


<s>,< 


Rd> 






Execution 


(s) + (Rd) + (C) 


-(Rd) 








Options 


inst operands 
ADC B,A 
ADC Rs,A 
ADC Rs,B 
ADC Rs,Rd 
ADC #iop8,A 
ADC #iop8,B 
ADC #iop8,Rd 


bytes cycles 

1 8 

2 7 

2 7 

3 9 
2 6 

2 6 

3 8 


opcode 
69 
19 
39 
49 
29 
59 
79 


operation 

(B) + (A) + (C)-(A) 
(Rs) + (A) + (C)-(A) 
(Rs) + (B) + (C)->(B) 
(Rs) + (Rd) + (C) -* (Rd) 
iop8 + (A) + (C) -* (A) 
iop8+(B) + (C) -» (B) 
iop8 + (Rd) + (C) -> (Rd) 


Status Bits 
Affected 


C Set to 1 on carry-out of (s) + (Rd) + (C) 

Z Set on result 

N Set on result 

V (C XOR N) AND (source [bit 7] XNOR destination [bit 7]) 


Description 


ADC adds the contents of the 


source. 


the contents of the destination reg- 



Adding a to the destination register is equivalent to a conditional incre- 
ment (increment on carry). 

ADC can implement multi-precision addition of signed or unsigned inte- 
gers. For example, the 1 6-bit integer in register pair (R2,R3) may be added 
to the 16-bit integer in (A,B) as follows: 



ADD 
ADC 



R3,B 
R2,A 



Examples 



LABELl ADC R66,R117 



ADC 



B,A 



ADC #03Ch,R29 



Low order bytes added 
High order bytes added 

Adds the contents of 
register 66, register 
117, and the carry bit, 
and stores the sum in 
register 117 

Adds the contents of 
Register B, Register A, 
and the carry bit, and 
stores the sum in 
Register A 

Adds #3Ch, contents of 
register 29, and the 
carry bit, and stores 
the sum in register 29 



12-30 



ADD 



Add 



ADD 



Syntax [<label>] ADD <s>,<Rd> 

Execution (s) + (Rd) -♦ (Rd) 

Options in St operands bytes cycles opcode operation 

ADD B,A 1 8 68 (B) + (A) -* (A) 

ADD Rs,A 2 7 18 (Rs) + (A) -* (A) 

ADD Rs,B 2 7 38 (Rs) + (B) -♦ (B) 

ADD Rs,Rd 3 9 48 (Rs) + (Rd) ^ (Rd) 

ADD #iop8,A 2 6 28 iop8+(A) -^ (A) 

ADD #iop8,B 2 6 58 iop8+(B) - (B) 

ADD #iop8,Rd 3 8 78 iop8 + (Rd) -» (Rd) 



Status Bits 
Affected 



Description 
Examples 



C Set to 1 on carry-out of (s) + (Rd) 

Z Set on result 

N Set on result 

V (C XOR N) AND (Source [bit 7] XNOR Destination [bit 7]) 

ADD adds two bytes and stores the result in the destination register. It can 
be used for signed 2's complement or unsigned addition. 



LABEL 



ADD A,B 



ADD R7,A 



;Adds the contents of 
;Registers A and B, stores 
;the results in B 

;Adds the contents of R7 
;and A, and stores the 
; results in A 



ADD #T0TAL,R13 ;Adds the value of 

; TOTAL to R13 and stores 
;the result in R13 



12-31 



AND 



Logical AND 



AND 



Syntax 


[<label>] AND 


<s>. 


<Rd> 






Execution 


(s) AND (Rd) - (Rd) 








Options 


inst operands 


bvtes cycles 


opcode 


operation 




AND A,Pd 


2 


9 


83 


(A) AND (Pd) -» (Pd) 




AND B,A 


1 


8 


63 


(B) AND (A) -* (A) 




AND B,Pd 


2 


9 


93 


(B) AND (Pd) -* (Pd) 




AND Rs,A 


2 


7 


13 


(Rs) AND (A) -* (A) 




AND Rs,B 


2 


7 


33 


(Rs) AND (B) -* (B) 




AND Rs,Rd 


3 


9 


43 


(Rs) AND (Rd) -^ (Rd) 




AND #iop8,A 


2 


6 


23 


iopBAND (A) -> (A) 




AND #iop8,B 


2 


6 


53 


iopBAND (B) -^ (B) 




AND #iop8,Rd 


3 


8 


73 


iopBAND (Rd) - (Rd) 




AND #iop8,Pd 


3 


10 


A3 


iop8 AND (Pd) -> (Pd) 


Status Bits 












Affected 


C -0 












N Set on result 










Z Set on result 










V -0 










Description 


AND logically ANDs the two 8-bit operands. Each bit in the first operand 



is ANDed with the corresponding bit in the second operand. This is useful 
for clearing bits. If you need to clear a bit in the destination operand, then 
put a in the corresponding source bit. A 1 in a source bit will not change 
the corresponding destination bit. 



Examples LABEL AND #01h,Rl2 ; Clear all bits in R12 except 

;Bit 0, which will remain 
/unchanged 

AND R7,A ;AND the contents of R7 to A 
;and store the contents in A 

AND B,P025 ;AND contents of B to P025, 
; store the contents in P025 



12-32 



BR 



Branch 



BR 



Syntax 


[<label>] BR 


<XADDR> 




Execution 


XADDR -^ (PC) 






Options 


inst operands 
BR label 
BR label(B) 
BR off8(Rp) 
BR @Rp 


bytes cycles opcode 
3 9 8C 

3 11 AC 

4 16 F4 EC 
2 8 9C 


operation 
label -> (PC) 
label + (B) -> (PC) 
(Rn-1:Rn)+off8 -* (PC) 
(Rn-1:Rn) ^ (PC) 



Status Bits 
Affected 

Description 



Examples 



Note: label = unsigned 16-bit value 
(B) = unsigned 8-bit value 
off8 =^ signed 8-bit value 



None 



BR 



BR branches to any location in memory, including the on-chip RAM. 
supports the four extended absolute addressing modes: 

• Direct 

• Indirect 

• Indexed 

• Offset Indirect 

The powerful concept of computed GOTOs is supported by the BR @Rn 
instruction. An indexed branch instruction of the form BR TABLE (B) is 
an extremely efficient way to execute one of several actions on the basis of 
a control input. This is similar to the Pascal CASE statement. The program 
can branch to up to 1 28 different jump statements. This technique may also 
be used to transfer control on character inputs, error codes, etc. 



LABEL BR LABEL4 



BR 


5432h 


(PC) 


BR 


LABELS (B) 


(PC) 


BR 


1234h(B) 


(PC) 


BR 


(aR12 


(PC) 


BR 


56(R10) 


(PC) 



(PC) 



LABEL4 

5432h 

LABELS + (B) 

1234h + (B) 

(R11:R12) R12=LSB 

56 + (R9:R10) R10=LSB 



12-33 



BTJO 



Examples 



Bit Test and Jump If One 



BTJO 



Syntax 


[<label>] BTJO <s>,<d 


>,<off8> 




Execution 


If (s) AND (d) 9i 0, th 


en PCN +off8 


-* (PC), else PCN -* (PC) 


Options 


inst operands 
BTJO A,Pd,label 
BTJO B,A,label 
BTJO B,Pd,label 
BTJO Rs,A,label 
BTJO Rs,B,label 
BTJO Rs,Rd,label 
BTJO #iop8,A,label 
BTJO #iop8,B,label 
BTJO #iop8,Rd,label 
BTJO #iop8,Pd,label 


bvtes 
3 
2 
3 
3 
3 
4 
3 
3 
4 
4 


cycles opcode 
10/12 86 
10/12 66 
10/12 96 
9/11 16 
9/11 36 
11/13 46 
8/10 26 
8/10 56 
10/12 76 
11/13 A6 


Jump If 

(A) AND (Pd) 96 

(B) AND (A) jt 
(B) AND (Pd) # 
(Rd) AND (A) # 
(Rd) AND (B) 9t 
(Rd) AND (Rs)^ 

(A) AND off8 9* 

(B) AND off8 9t 
(Rd) AND offS 9^ 
(Pd) AND off8 ^ 


Status Bits 
Affected 


C ^0 

N Set on (s) AND (d) 
Z Set on (s) AND (d) 

V *-o 








Description 


BTJO jumps if at least one 


corresponding 


bit position in the source and 



destination are both 1 . The source operand can be used as a bit mask to test 
for one or more 1 bits in the specified register. The operands are not 
changed by this instruction. If one or more corresponding 1 bits are found, 
the program branches to the offset (refer to the table below). 



(s) 


(d) 


Jump? 


00000001 


xxxxxxxO 


No 


00000001 


xxxxxxxl 


Yes 


0000001 1 


xxxxxxOO 


No 


11110000 


1 OOOxxxx 


Yes 


11110000 


1 001 xxxx 


Yes 



LABEL 



BTJO #014,R4,ISSET ; Jump to ISSET if R4 

; (bit 2) or R4 (bit 
;4) is a 1 



BTJO #01, A, LOOP 



;Jump to LOOP if bit 
;of Register A is a 1 



BTJO R37,R113, START ; Jump to START if any 

; 1 bit of R113 corre- 
;sponds to a 1 bit 
;in R37 



12-34 



BTJZ 



Bit Test and Jump If Zero 



BTJZ 



Syntax 


[<label>] BTJZ <s>,<d 


>,<off8 


> 




Execution 


If (s) AND NOT (d) i^ 


0, th 


en PCN+ off8 ^ 


' (PC), else PCN -^ (PC) 


Options 


inst operands 


bvtes 


cycles 


DDCode 


Jump If 




BTJZ A,Pd,label 


3 


10/12 


87 


(Pd) AND NOT(A) i^ 




BTJZ BAIabel 


2 


10/12 


67 


(A) AND NOT(B) i^ 




BTJZ B,Pd,label 


3 


10/12 


97 


(B) AND NOT(Pd) ?* 




BTJZ RdAlabel 


3 


9/11 


17 


(A) AND NOT(Rd) i^ 




BTJZ Rd,B,label 


3 


9/11 


37 


(B) AND NOT(Rd) 5^ 




BTJZ Rs,Rd,label 


4 


11/13 


47 


(Rd) AND NOT(Rs) # 




BTJZ #iop8,A,label 


3 


8/10 


27 


(A) AND NOToff8 i^ 




BTJZ #iop8,B,label 


3 


8/10 


57 


(B) AND NOT off8 ^ 




BTJZ #iop8,Rd,label 


4 


10/12 


77 


(Rd) AND NOToffS # 




BTJZ #iop8,Pd,label 


4 


11/13 


A7 


(Pd) AND NOToffB ^ 


Status Bits 












Affected 


C ^0 












N Set on (s) AND NOT (Rd) 








Z Set on (s) AND NOT (Rd) 
V ^0 






Description 


BTJZ jumps if at least 


one corresponding bit position which has a 1 in the 



source and a in the destination (refer to the table below). The source 
operand can be used as a bit mask to test for zero bits in the specified reg- 
ister. The operands are unchanged by this instruction. The jump is calcu- 
lated starting from the opcode of the instruction just after the BTJZ. 



(s) 


(d) 


Jump? 


00000001 


xxxxxxxO 


Yes 


00000001 


xxxxxxxl 


No 


11000000 


1 1 xxxxxx 


No 


11110000 


01 1 1 xxxx 


Yes 


11110000 


01 1 0xxxx 


Yes 



Examples 



LABEL BTJZ A, R2 3, ZERO 



If any 1 bits in A 
correspond to bits 
in R23, then jump to 
ZERO 



BTJZ #OFFh,A,NEXT ;If A contains any 
;bits, jump to NEXT 



BTJZ R7,R15,OUT 



;If any bits in R15 
; correspond to 1 bits 
;in R7, jump to OUT 



12-35 



CALL 



Call 



Status Bits 
Affected 

Description 
Examples 



CALL 



Syntax 


[<label>] CALL <XADDR> 


Execution 


(SP) + 1 -► (SP) 




PCN MSB -+ ((SP)) 




(SP) + 1 -♦ (SP) 




PCN LSB -» ((SP)) 




XADDR -» (PC) 




(The Stack contains the address of the instruction immediately following the CALL.) 


Options 


inst operands bvtes cvcles opcode operation 




CALL label 3 13 8E label -► (PC) 




CALL label(B) 3 15 AE label + (B) -♦ (PC) 




CALL off8(Rd) 4 20 F4 BE (Rd-1:Rd)+off8 -♦ (PC) 




CALL @Rd 2 12 9E (Rd-1:Rd) -♦ (PC) 



Note : offset = signed 16-bit value 
(B) = unsigned 8-bit value 
offS = signed 8-bit value 



None 



CALL invokes a subroutine and pushes the PC contents on the stack. The operand 
indicates the starting address of the subroutine. The extended addressing modes of the 
CALL instruction allow powerful transfer of control functions. 



LABEL CALL LABEL4 ;Push PC 

CALL 5432h ;Push PC 

CALL LABELS (B) ;Push PC 

CALL 1234h(B) ;Push PC 



CALL @R12 



;Push PC 
7R12=LSB 



(PC) ^ LABEL4 

(PC) - 5432h 

(PC) *- LABELS + (B) 

(PC) ^ 1234h + (B) 

(PC) ^ (R11:R12) 



CALL 56 (RIO) ;Push PC; (PC) *" 56 + 
;(R9:R10) R10=LSB 



12-36 



CALLR 



Call Relative 



CALLR 



Syntax 
Execution 



[<label>] CALLR <XADDR> 



(SP) + 1 
PCN MSB 
(SP) + 1 
PCN LSB 



(SP) 
((SP)) 
(SP) 
((SP)) 



XADDR + PC^^ (PC) 



Options inst operands 

CALLR label 
CALLRIabel(B) 
CALLRoff8(Rp) 
CALLR@Rd 

Note 



bytes cycles opcode 
3 15 8F 

3 17 AF 

4 22 F4 EF 
2 14 9F 



operation 

off16 + PCN ->■ (PC) 

off16 + (B) + PCN -* (PC) 

(Rd-1:Rd) + offS + PCN - (PC) 

(Rd-1:Rd) + PCN -* (PC) 



:off16= signed 16-bit value 
(B) = unsigned 8-bit value 
offS = signed 8-bit value 



Status Bits 
Affected 

Description 



Examples 



None 

CALLR is similar to CALL, but uses a value relative to the current program 
counter (PCN). The extended relative addressing modes of the CALLR in- 
struction allow powerful transfer of control functions. This is useful for re- 
locatable code produced by linkers, compilers or other high language 
structures. The assembler automatically calculates the correct offset value 
for the two modes using labels in the operands. 



Direct Addressing 
LABEL CALLR LABEL4 



CALLR 5432h 



Indexed Addressing 

CALLR LABELS (B) 



;push PC ; (PC) ^ PCN + 
;Offl6, off 16=LABEL4-PCN 



;push PC 
;5432h 



(PC) 



PCN -I- 



CALLR 1234h(B) 



Indirect Addressing 
CALLR @R12 



;push PC ; (PC) *- PCN -I- 
;Offl6 -I-(B) 
;offl6=LABEL5 - PCN 

;push PC ; (PC) ♦- PCN -I- 
;1234h + (B) 



push PC ; (PC) ^ PCN -f- 
(R11:R12) 
R12=LSB 



Offset Indirect Addressing 
CALLR 56 (RIO) 



push PC ; (PC) ♦- PCN 
-I- 56 + (R9:R10) 
R10=LSB 



12-37 



CLR 



Clear 



CLR 



Syntax 
Execution 

Options 



Status Bits 
Affected 



Description 
Examples 



[<label>] CLR <Rn> 

- (Rn) 

inst operands bytes cycles opcode operation 



CLR 
CLR 
CLR 



C 

N 

Z 
V 



A 
B 
Rn 



B5 
C5 
D5 



(A) 
(B) 
(Rn) 



CLR clears or initializes to any register including Registers A and B. 

LABEL CLR B /Clear Register B 
CLR A ; Clear Register A 
CLR R105 ; Clear register 105 



12-38 



CLRC 



Clear the Carry Bit 



CLRC 



Syntax 


[<label>] CLRC 


Execution 


Set status bits 




Options 


inst Goerands 
CLRC none 


bvtes cycles opcode 
1 9 BO 


Status Bits 
Affected 


C -^0 

N Set on value of Register A 
Z Set on value of Register A 
V -0 


Description 


CLRC clears the 


carry flag. This may 



rotate instruction. The logical and move instructions typically clear the carry 
bit. The CLRC opcode is equivalent to the TST A opcode. 



Example 



LABEL CLRC 



; Clear the carry bit 



12-39 



CMP 



Compare 



CMP 



Syntax 


[<label>] CMP 


<s>, 


,<d> 






Execution 


(d) - (s) computed but not stored 




Options 


inst operands 1 


bvtes cycles opcode 


operation 




General: 












CMP B,A 


1 


8 


6D 


(A)-(B) 




CMP Rs,A 


2 


7 


ID 


(A)-(Rs) 




CMP Rs,B 


2 


7 


3D 


(B)-(Rs) 




CMP Rs,Rd 


3 


9 


4D 


(Rd)-(Rs) 




CMP #i6p8,A 


2 


6 


2D 


(A)-iop8 




CMP #iop8,B 


2 


6 


5D 


(B)-iop8 




CMP #iop8,Rd 


3 


8 


7D 


(Rd)-iop8 




Extended: 












CMP label,A 


3 


11 


8D 


(A)-(label) 




CMP label(B),A 


3 


13 


AD 


(A)-(label + (B)) 




CMP off8(Rp),A 


4 


18 


F4 ED 


(A)-((Rn-1:Rn)+off8) 




CMP @Rp,A 


2 


10 


9D 


(A)-((Rn-1:Rn)) 




CMP off8(SP),A 


2 


8 


F3 


(A)-((SP)+off8) 



Note: Operations are computed 
but not stored. Status bits 
are set on results. 



Status Bits 
Affected 



Description 



1 if (d) > (s) 

N Sign of result 

Z 1 if (d) = (s) 

V (C XOR N) AND (Source [bit 7] XOR Destination [bit 7]) 

CMP compares the destination operand to the source operand and sets the 
status bits. The CMP instruction is usually used in conjunction with a Jump 
instruction. Table 12-5 shows which Jump instructions can be used on 
status conditions set by CMP execution. There are only seven possible 
outcomes of the status register after a compare instruction. The jump in- 
structions JC and JHS are equivalent after a compare. 



12-40 



CMP 



Compare 



CMP 



Table 12-5. Compare Instruction Examples - Status Bit Values 



Operand 

Opcodes 

(S) (D) 


Status 

Bits 

CNZV 


JGE 


JG 


JL 


JLE 


JLO 


JHS 


JC 


JNC 


JN 


JP 


lEQ 
JZ 


JPZ 


JIME/ 
JNZ 


JV 


JNV 


FFOO 
81 00 


0000 


1 


1 








1 








1 





1 





1 







1 


80 00 
80 7F 


0101 


1 


1 








1 








1 


1 













1 





00 7F 
20 30 
90 AO 


1000 


1 


1 











1 


1 








1 





1 







1 


7F00 
30 20 
A0 90 


0100 








1 


1 


1 








1 


1 
















1 


7F80 


1001 








1 


1 





1 


1 








1 





1 




1 





00 FF 
00 81 
00 80 


1100 








1 


1 





1 


1 





1 
















1 


7F7F 


1010 


1 








1 





1 


1 











1 


1 








1 



Notes: 1. Signed Jumps:JGE, JG, JL, JLE. 
Unsigned JumpsJLO, JHS. 
Test BitsJC, JNC, JN, JP, JEQ/JZ, JPZ, JNE/JNZ, JV, JNZ 

2. 1 =jump was taken; O=does not jump 



Examples LABEL CMP R13,R89 

CMP R39,B 
CMP #003, A 



;Set status bits on 
;result of R89 minus R13 

;Set status bits on result 
;of (B) minus R39 

;Set status bits on result 
;of (A) minus #03h 



CMP TABLE(B),A ;Set statusd bits on result 
;of (A) minus (TABLE + (B)) 



12-41 



CMPBIT 



Complement Bit 



CMPBIT 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] CMPBIT <name> 
NOT <name> -*■ <name> 



inst operands 

CMPBIT Rname 
CMPBIT Pname 



bytes cycles opcode 
3 8 75 

3 10 A5 



C 

N 

Z 
V 







Set on result of (Mask XOR (s)) 
Set on result of (Mask XOR (s)) 
*-0 



operation 
NOT (bit) 
NOT (bit) 



(bit) Reg. bits 
(bit) Per. bits 



CMPBIT is an assembler constructed instruction that conviently comple- 
ments the value of the named bit without having to specify a register or 
mask. This enhances the readability of the software program. The CMPBIT 
instruction assembles to the instructions XOR #iop8,Rd or XOR #iop8,Pd. 
The name for the bit is defined by the .DBIT assembler directive. 



Examples INTIENA .DBIT 7,P017 ; Interrupt 1 bit is now 

; named INTIENA 

TEST .DBIT 4,R33 ;Bit 4 of register 33 is now 

; named TEST 



LABEL CMPBIT TEST 



; Invert the value of the TEST 
;bit. 



CMPBIT INTIENA ; Change the interrupt 1 
; enabled condition. 



12-42 



COMPL 



T\/>jo"s Complement 



COMPL 



Syntax [<label>] COMPL <Rn> 

Execution - Rn -♦ Rn 



Options in St operands 

COMPL A 

COMPL B 

COMPL Rn 



Status Bits 
Affected 



Description 



Set on result 
Set on result 
Set on result 

*-o 



bytes cycles opcode 
1 8 BB 

1 8 CB 

2 6 DB 



operation 
N0T(A)+1 -^ (A) 
N0T(B)+1 -* (B) 
N0T(Rn) + 1 - (Rn) 



COMPL provides a logical or 2's complement of the operand. This is the 
equivalent of an inversion of all the bits followed by an increment. The 
instruction is useful in doing arithmetic with signed numbers. 



Examples LABEL COMPL A ;Complement register A 

COMPL B ; Complement register B 
COMPL R82 ; Complement register 82 



12-43 



DAC 



Decimal Add \A^ith Carry 



DAC 



Syntax 


[<label>] DAC <s>,<Rd> 






Execution 


(s) + 


(Rd) + (C) -* (Rd), Produces a 


decimal result 


Options 


in St 


operands bytes cycles 


opcode 


operation 




DAC 


B,A 1 10 


6E 


(B) + (A) + (C) -(A) 




DAC 


Rs,A 2 9 


IE 


(Rs) + (A) + (C)-(A) 




DAC 


Rs,B 2 9 


3E 


(Rs) + (B) + (C)-(B) 




DAC 


Rs,Rd 3 11 


4E 


(Rs) + (Rd) + (C) ^ (Rd) 




DAC 


#iop8,A 2 8 


2E 


iop8 + (A) + (C) -^ (A) 




DAC 


#iop8,B 2 8 


5E 


iop8+(B) + (C) -> (B) 




DAC 


#iop8,Rd 3 10 


7E 


iop8+(Rd) + (C) - (Rd) 


Status Bits 










Affected 


C 

N 

Z 
V 


1 if value of (s) + (Rd) 
Set on result 
Set on result 
Undefined 


+ C > 


99 


Description 


DAC adds bytes in binary-coded decimal (BCD) form. Each byte is as- 



sumed to contain two BCD digits. DAC is not defined for non-BCD oper- 
ands. DAC with an immediate operand of zero value is equivalent to a 
conditional increment of the destination operand (increment destination on 
carry). The DAC instruction automatically performs a decimal adjust on the 
binary sum of (s) + (d) + C. The carry bit is added to facilitate adding 
multi-byte BCD strings, and so the carry bit must be cleared before exe- 
cution of the first DAC instruction. 



Examples 



LABEL DAC #024h,A 



If register A contains 097h 
and C = 0,then the final result 
put into A is 02 Ih ancJ the carry 
bit is set 



DAC R55,R7 



DAC B , A 



Acid the BCD value of R55, 
and the carry bit to the 
BCD value of R7 

Add the carry bit to the 
BCD value in Register B 
to Register A 



12-44 



DEC 



Decrement 



DEC 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 
Examples 



[<label>] DEC <Rn> 
(Rn) - 1 ^ (Rn) 

in St operands bytes cycles opcode operation 

DEC A 1 8 B2 {A)-1 -* (A) 

DEC B 1 8 C2 (B)-1 - (B) 

DEC Rn 2 6 D2 (Rn)-1 -* (Rn) 

C If (Rn) decrements from OOh to FFh; 1 otherwise 

N Set on result 

Z Set on result 

V 1 if (Rn) decrements from 80h to 7Fh; otherwise 

DEC subtracts 1 from any register. It is useful in counting and addressing 
byte arrays. 

LABEL DEC R102 ; Decrement R102 by 1 

DEC A 



DEC B 



; Subtract 1 from the contents of 

/register A 

; Subtract 1 from the contents of 

; register B 



12-45 



DINT 



Disable Interrupts 



DINT 



Syntax 

Execution 

Options 



Status Bits 
Affected 



[<label>] 
- (ST) 



DINT 



Description 



Example 



inst operands bytes cycles opcode 
DINT none 2 6 FO 00 



C ^0. 
N ^0 

Z *-o 

V ^0 
IE1 *-0 
IE2 -0 

DINT simultaneously disables all interrupts. Since the interrupt enable flags 
are stored in the Status Register, the POP ST or RETI instructions may re- 
enable interrupts even though a DINT instruction has been executed. Dur- 
ing the interrupt service, the interrupt enable bit is automatically cleared 
after the old Status Register value has been pushed onto the stack. The 
DINT instruction is equal to the LDST #00 instruction. 

LABEL DINT ;Disable high and low level interrupts. 



12-46 



DIV 



Divide 



DIV 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] DIV (Rs), A 
A:B/(Rs) -♦ A(=quo), B(=rem) 

inst operands bytes cycles opcode operation 
DIV Rn,A 3 47-63 F4 F8 (A:B)/(Rs) Quotient -> A 

Remainder -♦ B 
Note: If overflow occurs, 

14 cycles are used, and 
C,N,Z,V = 1 



C *-o 

N Set on results (Register A) 
Z Set on results (Register A) 
V -0 

DIV divides the 1 6-bit value in the A:B register pair by the 8-bit value in the 
specified register. The resulting 8-bit quotient is stored in A. Overflow 
conditions are checked prior to execution and if an overflow is detected, the 
operands are left unchanged and the status bits C,N,Z, and V are set to 1 
and the instruction is aborted. Execution time varies from 47-63 cycles 
depending on the operands, with an overflow condition taking only 14 cy- 
cles. 



Example label div rio,a 

JC OVERFLOW ; Carry is 1 on overflow conditions 



;R10 is divided into the 
;A:B register pair (A = MSB) 



12-47 



DJNZ Decrement Register and Jump If Not Zero DJNZ 



Syntax 
Execution 

Type 
Options 



Status Bits 
Affected 

Description 



Examples 



[<label>] DJNZ <Rn>,<off8> 

(Rn) - 1 ^ (Rn) 

If (Rn) ?i 0, then PCN + (offS) 



(PC), else PCN -> (PC) 



Single Operand 



inst operands bytes cycles opcode operation 

DJNZ A,LABEL 2 10/12 BA (A)-1 -* (A), jump if (A) ,4 

DJNZ B,LABEL 2 10/12 CA (B)-1 -> (B) jump if (B) ?i 

DJNZ Rn,LABEL 3 8/10 DA (Rn)-1 -(Rn) jump if (Rn) ?i 



None 

DJNZ is used for looping control. It combines the DEC and the JNZ in- 
structions, providing a faster and more compact instruction. DJNZ does 
not change the status bits. 

LABEL DJNZ R15, THERE ; Decrement R15 . If R15 ^ 0, 

;jump to THERE 



DJNZ A, AGAIN 
DJNZ B , BACK 



; Decrement A; if A # , 
;jump to AGAIN 

/Decrement B; if B ?* , 
;jump to BACK 



12-48 



DSB 



Decimal Subtract \AAith Borrow 



DSB 



Syntax 


[<label>] DSB 


<s> 


<Rd> 






Execution 


(Rd) 


- (s) - 1 + 


(C)-> 


(Rd) (decimal 


result) 


Options 


in St 

DSB 

DSB 

DSB 

DSB 

DSB 

DSB 

DSB 


operands 
B,A 
Rs,A 
Rs,B 
Rs,Rd 
#iop8,A 
#iop8,B 
#iop8,Rd 


bytes 
1 
2 
2 
3 
2 
2 
3 


cycles opcode 

10 6F 
9 IF 
9 3F 

11 4F 
8 2F 
8 5F 

10 7F 


operation 

(A)-(B)-1+(C) ->(A) 
(A)-(Rs)-1+(C)->(A) 
(B)-(Rs)-1+(C) ->(B) 
(Rd)-(Rs)-1+(C) -* (Rd) 
(A)-iop8-1+(C) - (A) 
(B)-iop8-1+(C) -* (B) 
(Rd)-iop8-1+(C) - (Rd) 


Status Bits 














Affected 


C 


1 if no borrow required. 


if borrow required 




N 


Set on result 










Z 


Set on result 










V 


Undefined 










Description 


DSB performs mi 


jitiprec 


:ision BCD subtraction. A DSB instruction with an 



Examples 



immediate operand of zero value is equivalent to a conditional decrement 
of the destination operand, depending on the carry bit. The carry bit func- 
tions as a no borrow bit, so if no borrow in is required, the carry bit should 
be set to 1. This can be accomplished by executing the SETC instruction. 
The DSB instruction is undefined for non-BCD operands. 



LABEL DSB R15,R76 



DSB A,B 



DSB #0,R5 



R76 minus R15 minus 1 plus 
the carry bit is stored 
in R76 

Register B minus Register 
A minus 1 plus the carry 
bit is stored in 
Register B 

R5 - 1 -► R5, if C = 
;R5 -► R5 if C = 1 



12-49 



EINT 



Enable Interrupts 



EINT 



Syntax 

Execution 

Options 



Status Bits 
Affected 



[<label>] EINT 
OCh ->' (ST) 

inst operands 
EINT none 



bytes cycles opcode 
2 6 FO OC 



Description 



Example 



C *-o 

N ^0 

Z *-o 
V *-o 

IE1 - 1 
IE2 ^ 1 

EINT simultaneously enables all global interrupts. Since the interrupt ena- 
ble flags are stored in the Status Register, the POP ST or RETI instructions 
may disable interrupts even though an EINT instruction has been executed. 
During the interrupt service, the interrupt enable bit is automatically cleared 
after the old Status Register value has been pushed onto the stack. Thus, 
the EINT instruction must be included inside the interrupt service routine 
to permit nested or multilevel interrupts. This instruction is equivalent to the 
LOST #OOCh instruction. 

LABEL EINT ;A11 interrupts are enabled. 



12-50 



EINTH 



Enable High Level Interrupts 



EINTH 



Syntax 


[<label>] EINTH 




Execution 


04h -* (ST) 






Options 


inst operands 


bvtes cvcles 


opcode 




EINTH none 


2 6 


F0 04 


Status Bits 








Affected 


C ^0 

N "^0 

z *-o 
V *-o 

IE1 *-1 
IE2 *-0 






Description 


EINTH is similar 


to the EINT ir 


istructio 



terrupts and disables low level interrupts. This is equal to the LOST 04h 
instruction. 



Example 



LABEL EINTH ;A11 level 1 interrupts are enabled, 



12-51 



EINTL 



Enable Lo\rj Level Interrupts 



EINTL 



Syntax 


[<label>] EINTL 




Execution 


08h - (ST) 






Options 


inst oDerands 


bvtes cvcles 


ODCode 




EINTL none 


2 6 


F0 08 


Status Bits 








Affected 


C ^0 
N -0 
Z -0 
V -0 
IE1 ^0 
IE2 ^ 1 






Description 


EINTL is similar 


to the EINT ir 


istructio 



Example 



terrupts while disabling high level interrupts. This is equal to the LDST 
#08h instruction. 

LABEL EINTL ;A11 level 2 interrupts are enabled. 



12-52 



IDLE 



idle Until Interrupt 



IDLE 



Syntax 
Options 



Status Bits 
Affected 

Description 



[<label>] IDLE 

(PC) + 1 -► (PC) after return from interrupt 

inst operands bytes cycles opcode 
IDLE none 1 6 (min.) F6 



None 

The IDLE Instruction causes the device to enter one of three modes. Two 
of these modes, HALT and STANDBY, use only a fraction of the normal 
operating power. In STANDBY, the on-chip oscillator remains active. In 
HALT, the oscillator is off and the chip consumes the least amount of 
power. Appropriate interrupts must be enabled before entering IDLE. For 
more information on the low power modes refer to section 4.4. 



Example 



LABEL IDLE 



; Enter Idle mode and 
:wait for interrupt 



12-53 



INC 



Increment 



INC 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 
Examples 



[<label>] INC <Rn> 
(Rn) + 1 -> (Rn) 

in St operands bytes cycles opcode operation 

INC A 18 B3 (A)+1 -^ (A) 

INC B 18 C3 (B)+1 -^ (B) 

INC Rd 2 6 D3 (Rn) + 1 -^ (Rn) 



C 1 if (Rd) incremented from FFh to OOh; otherwise 

N Set on result 

Z Set on result 

V 1 if (Rn) incremented from 7Fh to 80h; if otherwise 

INC increments the value of any register. It is useful for incrementing 
counters. 



LABEL INC A 
INC B 
INC R43 



/•Increment Register A by 1 
; Increment Register B by 1 
; Increment Register 43 by 1 



12-54 



IMCW 



Increment Word 



INCW 



Syntax 


[<label>] INCW #off8,<Rp> 


Execution 


(Rp) + #off8 - (Rp) 


Options 


inst ODerands bvtes cvcles opcode operation 
INCW #off8,Rp 3 11 70 off8 + (Rn-1:Rn) -► (Rn-1 :Rn) 

off8= signed 8 bit value 


Status Bits 
Affected 


C Set to 1 on carry out of off8 + (Rp) 

N Set on result 

Z Set on result 

V ( C XOR N ) AND (MSBIT offS XNOR MSBIT (Rd)) 


Description 


INCW increments the value of any register pair by the amount specified. 



Examples 



The register pair can be incremented by as much as 127 or decremented by 
as much as 128. This instruction is useful for incrementing counters into 
large tables. The off8 is sign extended in order to perform 16-bit two's 
complement addition. 



LABEL INCW #1,R10 
INCW #-l,R10 



; Increment RIO by 1 
;Decrement register RlO by 1 



INCW #100,R255 ; Increment register pair 
;R254:R255 



12-55 



INV 



Invert 



INV 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



Examples 



[<label>] INV <Rn> 
NOT(Rn) -* (Rn) 

in St operands bytes cycles opcode operation 

INV A 18 B4 NOT(A) -♦ (A) 

INV B 18 C4 NOT(B) -^ (B) 

INV Rn 2 6 D4 NOT(Rn) -^ (Rn) 



C 

N 

Z 
V 



Set on result 
Set on result 
-0 



INV performs a one's complement of the operand. A one's complement 
inverts the value of every bit in the register. A two's complement of the 
operand can be made by following the INV instruction with an increment 
(INC), or simply using the COMPL instruction. 

LABEL INV A ; Invert Register A (Os become Is, 
;ls become Os) 

INV B ; Invert Register B 

INV R82 ; Invert register 82 



12-56 



JBITO 



Jump If Bit = 



JBITO 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] JBITO <name>, <off8> 

If bit (name) = then PCN + offS -* (PC) else PCN -♦ PC 

in St operands bytes cycles opcode 
JBITO Rname 4 10 77 
JBITO Pname 4 11 A7 

Note: Add 2 cycles if jump is taken 



C *-o 

N Set on (s) AND NOT (Rd) 
Z Set on (s) AND NOT (Rd) 

V ^0 

The JBITO is an assembler constructed instruction that conviently jumps 
to the label if the value of the named bit is zero. This enhances the read- 
ability of the software program since the source does not have to specify 
both the register containing the bit and a mask. The instruction is assem- 
bled to BTJZ #iop8,Rd,label or BTJZ #iop8,Pd,label. The name for the bit 
is defined by the DBIT assembler directive. 



Example 



MCDATA .DBIT 2,P010 

BIT4 .DBIT 4,R3 

JBITO BIT4, THERE 



MC data in bit 2 of 
SCCRO (POlO) is now 
named MCDATA 

;Bit 4 of register 3 is 
;now named BIT4 

;Jump to THERE if bit 4 in 
;register 3 is zero. 



JBITO MCDATA, HERE ;Jump to HERE if the MC pin 
; is zero 



12-57 



JBIT1 



Jump If Bit = 1 



JBITl 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] JBITl <off8> 

bit (name) = 1 then PCN + off8 



(PC) else PCN -* (PC) 



inst operands bytes cycles opcode operation 
JBITl Rname 3 10 76 register bits 

JBITl Pname 3 12 A6 peripheral bits 

Note: Add two cycles if Jump is taken. 



C 

N 

Z 
V 



^0 

Set on (s) AND 

Set on (s) AND 

<-0 



(Rd) 
(Rd) 



The JBITl is an assembler constructed instruction that conviently jumps 
to the label if the value of the named bit is one. This instruction enhances 
the readability of the software program since the source does not have to 
specify both the register containing the bit and a mask. This instruction 
assembles to BTJO #iop8,Rd, label or BTJO #iop8,Pd, label. The name for 
the bit is defined by the .DBIT assembler directive. 



Example BUSYP .DBIT 7,P01C 

BITO .DBIT 0,R100 
LABEL BITl BITO, THERE 



;Busy bit in PEECTL 

; (program EEPROM) is now 

; named BUSYP 

;Bit of register 100 is 
;now named BITO 

;Jump to THERE if bit in 
;register 100 is a one. 



JBITl BUSYP, HERE ; Jump to HERE if the program 
; EEPROM is busy. 



12-58 



JMP 



Jump Unconditional 



JMP 



Syntax 

Execution 

Options 



Status Bits 
Affected 

Description 



[<label>] JMP <off8> 
PCN + offS - (PC) 

inst operands bytes cycles opcode operation 
JMP offS 2 7 00 PCN + off8 

None 



(PC) 



JMP jumps unconditionally to the address specified in the operand. The 
second byte of the JMP instruction contains the 8-bit relative address of 
the operand. The operand address must therefore be within -128 to -1-127 
bytes of the location of the instruction following the JMP instruction. The 
assembler will indicate an error if the target address is beyond -1 28 to -i-l 27 
bytes from the next instruction. For a longer jump the BR (branch) or the 
JMPL instructions can be used. 



Example 



LABEL JMP THERE 



/•Load the PC with the address 
;of THERE 



12-59 



JMPL 



Jump Long 



JMPL 



Syntax 

Execution 

Options 



[<label>] JMPL <XADDR> 
PCN + D -* (PC) 

Inst operands bytes cycles opcode operation 

JMPL label 3 9 89 off16 + PCN -♦ (PC) 

JMPL label(B) 3 11 A9 off16 + (B) + PCN -► (PC) 

JMPL off8(Rp) 4 16 F4 E9 (Rn-1 :Rn)+off8+PCN - (PC) 

JMPL @Rd 2 8 99 (Rn-1:Rn) + PCN -* (PC) 

Note: offset = signed 1 6 bit value 
off8 = signed 8 bit value 
(B) = unsigned 8 bit value 



Status Bits 
Affected 



None 



Description JMPL is similar to JMP instruction but generates a 16-bit (instead of 8-bit) 
signed offset to the program counter. 



Example LABEL JMPL LABEL4 

JMPL 5432h 
JMPL LABELS (B) 

JMPL 1234h(B) 
, JMPL @R12 

JMPL 56 (RIO) 

JMPL -2 (RIO) 



(PC) ^ PCN + offset 
offset=LABEL4-PCN 



(PC) 



PCN + 5432h 



(PC) ♦- PCN + offB + (B) 
offset=LABEL5 - PCN 



(PC) 



PCN + 1234h + (B) 



(PC) ♦- PCN + (R11:R12) 
R12=LSB 

(PC) - PCN + 56 + (R9:R10) 
R10=LSB 

(PC) - PCN -2 + (R9:R10) 
RIO = LSB 



12-60 



J<cnd> 



Jump on Condition 



J<cnd> 



Syntax [<label>] J<cnd> <off8> 

Execution If tested condition is true, (PC) + offS -+ (PC), else PCN -* (PC) 



Status Bits 
Affected 

Description 



None 

The J<cnd> instructions are commonly used after a CMP instruction to 
branch according to the relative values of the operands tested. After MOV 
operations, a JZ or JNZ may be used to test if the value moved was equal 
to zero. JN and JPZ may be used in this case to test the sign bit of the 
value moved. The program may check the overflow bit V after using an 
arithmetic instruction with the JV or JNV instructions. 

Conditional Jump Instructions 



INSTRUCTION 


MNEMONIC 


OPCODE 


C 


N 


z 


V 


OPERATION 


Jump if Carry 


JC 


03 


1 


X 


X 


X 




Jump if No Carry 


JNC 


07 





X 


X 


X 




Jump if Equal 


JEQ 


02 


X 


X 


1 


X 




Jump if Not Equal 


JNE 


06 


X 


X 





X 




Jump if Non-zero 


JNZ 


06 


X 


X 





X 




Jump if Zero 


JZ 


02 


X 


X 


1 


X 




Jump if Lower 


JLO 


OF 





X 





X 


(C = 1) OR (Z = 1) 


Jump if Higher or same 


JHS 


OB 


- 


X 


- 


X 


--Signed Operation-- 


Jump if Greater 


JG 


OE 


X 


- 


- 


- 


ZOR (NXORV) =0 


Jump if Greater or equal 


JGE 


OD 


X 


- 


X 


- 


NXORV = 


Jump if Less 


JL 


09 


X 


- 


X 


- 


N XOR V = 1 


Jump if Less or Equal 


JLE 


OA 


X 


- 


- 


- 


ZOR (NXORV) = 1 


Jump if Negative 


JN 


01 


X 


1 


X 


X 




Jump if Positive 


JP 


04 


X 








X 




Jump if Positive or Zero 


JPZ 


05 


X 





X 


X 




Jump if No Overflow 


JNV 


OC 


X 


X 


X 







Jump if Overflow 


JV 


08 


X 


X 


X 


1 





Signed Number Jumps 



Unsigned Number Jumps 



CONDITION 


TRUE 


FALSE 


d < s 


JL 


JGE 


d ^ s 


JLE 


JG 


d = s 


JEQ 


JNE 


d > s 


JGE 


JL 


d > s 


JG 


JLE 


Negative 


JN 


JPZ 


Positive 


JP 


1 


Pos or 


JPZ 


JN 



CONDITION 


TRUE 


/FALSE 


d <s 


JLO 


JHS 


d ^ s 


2 


3 


d = s 


JEQ 


JNE 


d >s 


JHS 


JLO 


d > s 


3 


2 



Notes 1 .JZ LABEL, JN LABEL 

2.JEQ LABEL, JLO LABEL 
3.JEQ LABEL, JHS LABEL 



12-61 



J<cnd> 



Jump on Condition 



J<cnd> 



Examples 



LABEL 



JNC TABLE 
JP 



JZ 



Status Bit Jumps 



BITS 


TRUE 


FALSE 


C 


JC 


JNC 


N 


JN 


JPZ 


Z 


JZ 


JNZ 


V 


JV 


JNV 



;If the carry bit is clear, 
;jump to TABLE 



HERE ;If the negative and zero flags 
;are clear, jump to HERE 

NEXT ;If the zero flag is set, jump 
;to NEXT 



12-62 



LDSP 



Load Stack Pointer 



LDSP 



Syntax 

Execution 

Options 

Status Bits 
Affected 

Description 
Example 



[<label>] LDSP 
(B) -> (SP) 

inst operands bytes cycles opcode 
LDSP none 1 7 FD 

None 

LDSP copies the contents of Register B to the Stack Pointer register. Use 
LDSP to initialize the Stack Pointer. 

MOV #080h,B ;Register B = SP value. 

LABEL LDSP ;Copy Register B to the stack 
;pointer . 



12-63 



LDST 



Load Status Register 



LDST 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] LDST#iop8 
(iop8) - (ST) 

in St operands bytes cycles opcode operation 
LDST none 2 6 FO iop8 - (ST) 



C Set on value loaded 

N Set on value loaded 

Z Set on value loaded 

V Set on value loaded 

IE1 Set on value loaded 

IE2 Set on value loaded 

The LDST copies the immediate value operand to the Status register. Any 
combination of bits may be loaded into the status register using this com- 
mand. Some instructions such as EINT, EINTL, EINTH or DINT are assem- 
bled into this instruction. 



Exannple LABEL LDST #08Ch ;Copy immediate value to 

;the Status Register and 
;set IE2 bit 



12-64 



MOV 



Move 



MOV 



Syntax 


[<label>] MOV 


<s> 


,<d> 








Execution 


(s)- 


(d) 












Options 


inst 


operands bytes cvcles 


opcode 


operation 






REGISTER: 














MOV 


A,B 


1 


9 


CO 


(A) -* (B) 






MOV 


A,Rd 


2 


7 


DO 


(A) - (Rd) 






MOV 


B,A 


1 


8 


62 


(B) - (A) 






MOV 


B,Rd 


2 


7 


D1 


(B) - (Rd) 






MOV 


Rs,A 


2 


7 


12 


(Rs) - (A) 






MOV 


Rs,B 


2 


7 


32 


(Rs) - (B) 






MOV 


Rs,Rd 


3 


9 


42 


(Rs) -* (Rd) 






MOV 


#iop8,A 


2 


6 


22 


iop8 -♦ (A) 






MOV 


#iop8,B 


2 


6 


52 


iop8 -+ (B) 






MOV 


#iop8,Rd 


3 


8 


72 


iop8 -♦ (Rd) 






PERIPHERAL: 














MOV 


A,Pd 


2 


8 


21 


(A) - (Pd) 






MOV 


B,Pd 


2 


8 


51 


(B) - (Pd) 






MOV 


Rs,Pd 


3 


10 


71 


(Rs) - (Pd) 






MOV 


Ps,A 


2 


8 


80 


(Ps) - (A) 






MOV 


Ps,B 


2 


8 


91 


(Ps) -> (B) 






MOV 


Ps,Rd 


3 


10 


A2 


(Ps) - (Rd) 






MOV 


#iop8,Pd 


3 


10 


F7 


iop8 - (Pd) 






EXTENDED: 














MOV 


A,@Rn 


2 


9 


9B 


(A) -((Rn-1:Rn)) 






MOV 


AJabel 


3 


10 


8B 


(A) -^ (label) 






MOV 


A,label(B) 


3 


12 


AB 


(A) -> (!abel + (B)) 






MOV 


A,off8(SP) 


2 


7 


F2 


(A) - (off8+(SP)) 






MOV 


A,off8(Rd) 


4 


16 


F4 EB 


(A) ^ (off8+(Rd-1:Rd)) 






MOV 


@Rs,A 


2 


9 


9A 


((Rs-1:Rs)) -(A) 






MOV 


label,A 


3 


10 


8A 


(label) ^ (A) 






MOV 


label(B),A 


3 


12 


AA 


(label + (B)) -* (A) 






MOV 


off8(SP),A 


2 


7 


F1 


(off8 + (SP)) ^ (A) 






MOV 


off8(Rn),A 


4 


17 


F4 EA 


(off8 +(Rn-1:Rn)) -> (A) 




Status Bits 
















Affected 


C 


^0 














N 


Set on value loaded 










Z 


Set on value loaded 










V 


^0 












Description 


MOV transfers values w 


Ithin the memory space. Immediate values 


may be 



Examples 



loaded directly into the registers. In extended addressing modes the pro- 
cessor must use register A. A MOV instruction that uses Register A or B 
as an operand requires fewer bytes. The MOV Pn,Rn and MOV Rn,Pn in- 
structions have the operands reversed when assembled into machine code. 



LABEL MOV A , B 



;Move the contents of Register 
;A to Register B 



MOV R32,R105 ;Move the contents of register 
;32 to register 105 



MOV 



#010h,R3 ;Move #010h to register 3 



12-65 



MOVW 



Move Word 



MOVW 



Syntax 


[<label>] MOVW <s>,<Rd> 






Execution 


(s) -> (Rd) 






Options 


inst operands bvtes cycles 
MOVW#iop16,Rpd 4 13 
MOVWRps,Rpd 3 12 
MOVW#off8(Rs),Rpd 5 20 
MOVW#iop16(B),Rpd4 15 


opcode 
88 
98 

F4E8 
A8 


operation 

iop16 - (Rd-1:Rd) 

(Rs-1:Rs) -* (Rd-1:Rd) 

(Rs-1:Rs)+off8 -* (Rd-1:Rd) 

(B) + iop16 -* (Rd-1:Rd) 

;blank.1 



Status Bits 
Affected 



Description 



Examples 



C -0 

N Set on MSB moved 

Z Set on MSB moved 

V -0 

MOVW moves a two-byte value to the register pair indicated by the desti- 
nation register number. (Note that Rpd should be greater than 0.) The 
destination points to the LSB of the destination register pair. The source 
may be a 16-bit constant, another register pair, or an indexed address. For 
the Indexed address, the source must be of the form "#ADDR(B)" where 
ADDR is a 16-bit constant or address. This 16-bit value is added (via 
16-bit addition) to the contents of the B register, and the result placed in 
the destination register pair. This stores an indexed address into a register 
pair, for use later in indirect addressing mode. This is not to be confused 
with the extended addressing instruction LABEL(B). 



LABEL MOVW #1234h,R3 
MOVW R5,R3 



MOVW #TAB(B) ,R3 



;1234h -> (R2:R3) 

;(R4:R5) -> (R2:R3) 
7R5,R3 = LSB 



;TAB -1- (B) 
;R3=LSB 



(R2:R3) 



MOVW #127(R200) ,R34 ;127 + (R199:R200) 

;(R33:R34) 

MOVW #-128(R200) ,R34 ;(R199:R200) - 128 

7 (R33:R34) 



12-66 



MPY 



Multiply 



MPY 



Syntax 
Execution 

Options 



Status Bits 
Affected 



Description 



Examples 



[<label>] MPY <s>,<Rn> 

(s) X (Rn) -* (A:B) Result always stored in A,B A = MSB 

Inst operands bytes cycles opcode operation 



MPY 
MPY 
MPY 
MPY 
MPY 
MPY 
MPY 



C 

N 

Z 
V 



B,A 

Rs,A 

Rs,B 

Rs,Rd 

#iop8,A 

#iop8,B 

#iop8,Rd 







1 47 6C (A) X (B) - (A:B) 

2 46 1C (A) X (Rs) - (A:B) 

2 46 3C (B) X (Rs) -> (A:B) 

3 48 4C (Rd) X (Rs) - (A:B) 
2 45 2C (A) X iop8 -* (A:B) 

2 45 5C (B) X iop8 -* (A:B) 

3 47 7C (Rd) X iop8 -* (A:B) 



Set on MSB of results (Register A) 
Set on MSB of results (Register A) 
-0 



MPY performs an 8-bit multiply for a general source and destination op- 
erand. The 16-bit result is placed in the A, B register pair with the most 
significant byte in A. Multiplying by a power of two is a convenient means 
of performing double-byte shifts. If a double byte shift is three places or 
less, then it may be faster to use RLC or RRC instead of multiply. If a single 
byte needs shifting then it is almost always faster to use RLC or RRC. 



LABEL MPY R3,A 



;Multiply (R3) with (A), store 
/•result in A, B register pair 



MPY #032h,B /Multiply 32h with (B) , store 
; in register pair A, B 

MPY R12,R7 /-Multiply (R12) with (R7) and 
/•store in A, B register pair 



12-67 



NOP 



No Operation 



NOP 



Syntax 

Execution 

Options 



Status Bits 
Affected 

Description 



Example 



[<label>] NOP 
(PC) + 1 -» (PC) 

inst operands bytes cycles opcode 
NOP none 1 7 FF 

None 

NOP is useful as a pad instruction during program development, to "patch 
out" unwanted or erroneous instructions or to leave room for code changes 
during development. It is also useful in software timing loops. 

LABEL NOP 



12-68 



OR 



Logical OR 



OR 



Syntax 


[<label>] OR <s 


>,<Rd> 








Execution 


(s) OR (Rd) - (Rd) 








Options 


inst operands 
OR A,Pd 
OR B,Pd 
OR B,A 
OR Rs,A 
OR Rs,B 
OR Rs,Rd 
OR #iop8,A 
OR #iop8,B 
OR #iop8,Rd 
OR #iop8,Pd 


bytes cycles 
2 9 
2 9 

1 8 

2 7 

2 7 

3 9 
2 6 

2 6 

3 8 
3 10 


opcode 
84 
94 
64 
14 
34 
44 
24 
54 
74 
A4 


operation 

(A) OR (Pd) -* (Pd) 

(B) OR (Pd) -* (Pd) 
(B) OR (A) - (A) 
(Rs) OR (A) ^ (A) 
(Rs) OR (B) -* (B) 
(Rs) OR (Rd) -* (Rd) 
iop8 OR (A) ->• (A) 
iop8 OR (B) -* (B) 
iop8 OR (Rd) - (Rd) 
iop8 OR (Pd) ^ (Pd) 


Status Bits 
Affected 


c *-o 

N Set on result 
Z Set on result 
V ^0 








Description 


OR logically ORs the two operands. The OR operation is used to set bits 
in a register. If a register needs a 1 in the destination then a 1 is placed in 
the corresponding bit location in the source operand. 


Examples 


LABEL OR 


A,R12 


7 


OR the 


A Register with R12, 



; store in R12 

OR #OOFh,A ;Set lower nibble of A to Is, 
; leave upper nibble unchanged 



OR R8,B 



;0R (R8) with (B) , store in B 



12-69 



POP 



POP from Stack 



POP 



Syntax [<label>] POP <d> 

Execution ((SP)) -► (d) 

(SP) - 1 - (SP) 

(Move value then decrement SP) 

Options inst operands bytes cycles opcode operation 

POP A 1 9 B9 ((SP)) - (A); (SP) - 1 -* (SP) 

POP B 1 9 C9 ((SP)) -» (B); (SP) - 1 -^ (SP) 

POP Rn 2 7 D9 ((SP)) -^ (Rn); (SP) - 1 -* (SP) 

POP ST 1 8 PC ((SP)) -^ (ST); (SP) - 1 -> (SP) 



Status Bits 






Affected 


C 


-0 




N 


Set on value POPed 




Z 


Set on value POPed 




V 


^0 



Note: POP ST affects all status bits. 



Description 



Examples 



POP pulls a value from the top of the stack. The stack can be used to save 
or pass values between routines. The Status Register may be replaced with 
the contents on the stack by the statement POP ST. This one-byte in- 
struction is usually executed in conjunction with a previously performed 
PUSH ST instruction. 

LABEL POP R32 ;Load R32 with value on top of stack 

POP ST ;Load Status Register with 
/value on top of stack 



12-70 



PUSH 



Push On Stack 



PUSH 



Syntax 
Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] PUSH <s> 

(SP) + 1 -» (SP) 

(s) - ((SP)) 

(Increment SP then move value) 

inst operands bytes cycles opcode operation 

PUSH A 1 9 B8 (SP) + 1 

PUSH B 1 9 C8 (SP) + 1 

PUSH Rn 2 7 D8 (SP) + 1 

PUSH ST 1 8 FB (SP) + 1 



(SP); (A) - ((SP)) 
(SP); (B) -> ((SP)) 
(SP); (Rn) -> ((SP)) 
(SP); (ST) -> ((SP)) 



C *-o 

N Set on value PUSHed 

Z Set on value PUSHed 

V ^0 

Note: Status bits are unchanged for PUSH ST 

PUSH places a value on the top of the stack. The stack is used to save or 
pass values between routines. 

The Status Register may be pushed on the stack with the statement PUSH 
ST This one-byte instruction is usually executed in conjunction with a 
subsequently performed POP ST instruction. 



Examples LABEL PUSH A ;Move (A) to top of stack 

PUSH ST ;Move status to top of stack 



12-71 



RL 



Rotate Left 



RL 



Syntax 
Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] RL <Rn> 



Bit(n) 
Bit(7) 



Bit(n + 1) 
Bit(O) and carry 



inst operands bytes cycles opcode 

RL A 1 8 BE 

RL B 1 8 CE 

RL Rn 2 6 DE 



C Set to bit 7 of the original operand 

N Set on result 

Z Set on result 

V *-o 



RL circularly shifts the destination contents one bit to the left. The MSb is 
shifted into the LSb; the carry bit is also set to the original MSb value. 







MSb 














LSb 




c 






7 


6 


5 


4 


3 


2 


1 





4 1 

























Examples 



For example, if Register B contains the value 93h, then RL changes the 
contents of B to 27h and sets the carry bit. 



LABEL 



RL R102 
RL A 
RL B 



12-72 



RLC 



Rotate Left Through Carry 



RLC 



Syntax 


[<label>] RLC <Rn> 


Execution 


Bit(n) 
Carry 
Bit(7) 


-^ Bit(n + 1) 
-* Bit(O) 
-» Carry 


Options 


inst 
RLC 
RLC 
RLC 


operands bytes cycles opcode 
A 1 8 BF 
B 1 8 CF 
Rn 2 6 DF 


Status Bits 
Affected 


C 

N 

Z 
V 


Set to bit 7 of the original operand 
Set on result 
Set on result 
^0 


Description 


RLC circularly shifts the destination conte 



the carry. The original carry bit contents shift into the LSb, and the original 
MSb shifts into the carry bit. 





c 




MSb 














LSb 




r-4— 


7 


6 


5 


4 


3 


2 


1 





4 1 



















Examples 



For example, if Register B contains the value 93h and the carry bit is a zero, 
then the RLC instruction changes the operand value to 26h and the carry 
to one. 

Rotating left effectively multiplies the value by 2. Using multiple rotates, 
any power of 2 (2, 4, 8, 16,...) can be achieved. This type of multiply can 
be faster than the MPY (multiply) instruction. This instruction is also useful 
in rotates where a value is contained in more than one byte such as an ad- 
dress or in multiplying a large multibyte number by 2. Care must be taken 
to assure that the carry is at the proper value. The SETC or CLRC in- 
structions may be used to setup the correct value. 

LABEL RLC R72 
RLC A 
RLC B 



12-73 



RR 



Rotate Right 



RR 



Syntax 
Execution 

Options 



[<label>] RR <Rn> 



Bit(n + 1) 
Bit(O) -H 



-► Bit(n) 
Bit (7) and carry 



inst operands bytes cycles opcode 

RR A 1 8 BC 

RR B 1 8 CC 

RR Rn 2 6 DC 



Status Bits 
Affected 



Description 



C Set to bit of the original value 

N Set on result 

Z Set on result 

V ^0 

RR circularly shifts the destination contents one bit to the right. The LSb 
is shifted into the MSb, and the carry bit is also set to the original LSb va- 
lue. 







MSb 














LSb 




c 






7 


6 


5 


4 


3 


2 


1 





— ►-i 

























Example 



For example, if Register B contains the value 93h, then the "RR B" in- 
struction changes the contents of B to C9h and sets the carry status bit. 

LABEL RR A 



12-74 



RRC 



Rotate Right Through Carry 



RRC 



Syntax 


[<label>] RRC <Rn> 


Execution 


Bit(n- 
Carry 
Bit(O) 


f1) -* Bit(n) 
-* Bit(7) 
-♦ Carry 


Options 


inst 
RRC 
RRC 
RRC 


ODerands bytes cycles opcode 
A 1 8 BD 
B 1 8 CD 
Rn 2 6 DD 


Status Bits 
Affected 


C 

N 

Z 
V 


Set to bit of the original value 
Set on result 
Set on result 
^0 


Description 


RRC ( 


:ircularly shifts the destination c( 



the carry. The carry bit contents shift into the MSb, and the LSb is shifted 
into the carry bit. 







MSb 














LSb 




1 — ►- 


c 


7 


6 


5 


4 


3 


2 


1 





— ►- 























Example 



For example, if Register B contains the value 93h and the carry bit is zero, 
then RRC changes the operand value to 49h and sets the carry bit. 

When the carry is this instruction effectively divides the value by two. A 
value of 80h becomes 40h. By repetitive use of this instruction, the value 
can be divided by any power of two. Care must be taken to assure the 
correct value in the carry bit. 

LABEL RRC R32 



12-75 



RTI 



Return from Interrupt 



RTI 



Syntax 
Execution 



Options 



Status Bits 
Affected 

Description 



[<label>] RTI 

((SP)) 
(SP) - 1 
((SP)) 
(SP) - 1 
((SP)) 
(SP) - 1 



(PC LSB) 

(SP) 

(PC MSB) 

(SP) 

(ST) 

(SP) 



Example 



Inst operands bytes cycles opcode 
RTI none 1 12 FA 



Status Register is loaded from the stack 

RTI is typically the last instruction executed in an interrupt service routine. 
RTI restores the Status Register to its state immediately before the interrupt 
occurred and branches back to the program at the instruction boundary 
where the interrupt occurred. In an interrupt routine, there must be an equal 
number of POP's and PUSH'S so that the Stack is pointing to the correct 
return address and not some other data. 

LABEL RTI ;Return to main program from interrupt routine 



12-76 



RTS 



Return from Subroutine 



RTS 



Syntax 
Execution 



Options 



Status Bits 
Affected 

Description 



Example 



[<label>] RTS 



((SP)) 
(SP) - 1 
((SP)) 
(SP) - 1 



(PCLSB) 
(SP) 

(PC MSB) 
(SP) 



inst operands bytes cycles opcode 
RTS none 1 9 F9 



None 

RTS is typically the last instruction executed in a subroutine. RTS branches 
to the location immediately following the subroutine call instruction. In the 
called subroutine there must be an equal number of POPs and PUSHes so 
that the stack is pointing to the return address and not some other data. 

LABEL RTS ; Return to main program from subroutine 



12-77 



SBB 



Subtract >A/ith Borrow 



SBB 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



[<label>] SBB <s>,<Rcl> 
(Rd) - (s) - 1 + (C) - (Rd) 

in St operands bytes cycles opcode operation 

SBB B,A 1 8 6B (A) - (B) - 1 + (C) ->■ (A) 

SBB Rs,A 2 7 IB (A) - (Rs) - 1 + (C) -^ (A) 

SBB Rs,B 2 7 3B (B) - (Rs) - 1 + (C) - (B) 

SBB Rs,Rd 3 9 4B (Rd) - (Rs) - 1 + (C) -» (Rd) 

SBB #iop8,A 2 6 2B (A) - iopS - 1 + (C) -♦ (A) 

SBB #iop8,B 2 6 5B (B) - iop8 - 1 + (C) ^ (B) 

SBB #iop8,Rd 3 8 7B (Rd) - iop8 - 1 + (C) -► (Rd) 



C Set to 1 if no borrow; otherwise 

N Set on result 

Z Set on result 

V ((C XOR N) AND (Source[Bit 7] XOR Destination [Bit 7])) 

SBB performs multibyte 2's complement subtraction. An SBB instruction 
with an immediate operand of zero value is equivalent to a conditional de- 
crement of the destination operand, dependent on the carry value. If (s)-0 
and (C)=0 then (Rd) is decremented. A borrow occurs if the result is ne- 
gative. In this case, the carry bit is set to 0. The carry bit can be thought 
of as the "no-borrow" bit. 



Examples 



LABEL 



SBB 



SUB 
SBB 



#023h,B ;Subtract 23h from (B) , sub- 
; tract 1, add the carry bit 
;and store in Register B 



R3,R21 
R2,R20 



R20:R21 and R2:R3 contain 16 
bit numbers. SUB subtracts 
the LSB and the SBB will 
use the carry as a borrow 
during the subtract of 
the MSB. 



12-78 



SBITO 



Set Bit to 



SBITO 



Syntax 


[<label>] SBITO <name> 




Execution 


-* <name> 




Options 


inst 

SBITO 

SBITO 


operands bvtes cycles opcode operation 
Rname 3 8 73 -* <bit> 
Pname 3 10 A3 -> <bit> 


Register bits 
Peripheral bits 


Status Bits 
Affected 


C 

N 

Z 
V 


*-o 

Set on result 
Set on result 

*-o 




Description 


SBITO 


is an assembler constructed instruction that 


conveniently clears the 



value of the named bit without having to specify a register or mask. This 
enhances the readability of the software program. This instruction assem- 
bles to the instructions AND #iop8,Rd or AND #iop8,Pd. The name for the 
bit is defined by the .DBIT assembler directive. 



Examples 



INTIENA .DBIT 7,P01C 



The interrupt 1 enable 
bit is now 
named INTIENA 



TEST 



LABEL 



;Bit 4 of register 33 
; is now named TEST 



.DBIT 4,R33 

SBITO TEST 

SBITO INTIENA ; Disables Interrupt 1 



; Clears the value of the 
;TEST bit 



12-79 



SB[T1 



Set Bit to 1 



SBIT1 



Syntax 


[<label>] SBIT1 


1 <name> 


Execution 


1 -*■ <name> 






Options 


inst operands 
SBIT1 Rname 
SBIT1 Pname 


bvtes cycles opcode 
3 8 74 
3 10 A4 


Status Bits 
Affected 


C ^0 

N Set on rest 
Z Set on rest 
V -0 


lit 
lit 




Description 


SBIT1 is an assembler constructed in 



operation 

1 -» <bit> Register bits 

1 -> <bit> Peripheral bits 



value of the named bit without having to specify a register or mask. This 
enhances the readability of the software program. This instruction assem- 
bles to the instructions OR #iop8,Rd" or OR #iop8,Pd. The name for the 
bit is defined by the .DBIT assembler directive. 



Examples 



INTIENA .DBIT 7,P01C 



;The interrupt 1 enable bit 
;is now named INTIENA 



TEST .DBIT 4,R33 ;Bit 4 of register 33 is now 

; named TEST 

LABEL SBITl TEST ;Sets the value of the TEST 

;bit to 1 

SBITl INTIENA ;Enables Interrupt 1 



12-80 



SETC 



Set Carry 



SETC 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 
Example 



[<label>] SETC 

1 -(C) 

inst operands bytes cycles opcode 



SETC none 



1 



F8 



C 

N 

Z 
V 



SETC sets the carry flag. May be used before an arithmetic or rotate in- 
struction. The I El and IE2 enable bits are not affected. 



LABEL SETC 



Set the carry bit in the status 

register 

Status register = OAxh 



12-81 



STSP 



Store Stack Pointer 



STSP 



Syntax 

Execution 

Options 



Status Bits 
Affected 

Description 



Example 



[<label>] STSP 
(SP) - (B) 

in St operands bytes cycles opcode 
STSP none 1 8 FE 

None 

STSP copies the contents of the stack pointer to Register B. This instruc- 
tion can be used to test the stack size. The indexed addressing mode may 
be used to reference operands on the stack. 

LABEL STSP ;Copy the contents of stack pointer 
;to Register B 



12-82 



SUB 



Subtract 



SUB 



Syntax 


[<label>] SUB 


<s>,<Rd> 






Execution 


(Rd) 


- (s) -> (Rd) 






Options 


inst 


operands 


bvtes cycles 


opcode 


operation 




SUB 


B,A 


1 8 


6A 


(A) - (B) - (A) 




SUB 


Rs,A 


2 7 


1A 


(A) - (Rs) - (A) 




SUB 


Rs,B 


2 7 


3A 


(B) - (Rs) - (B) 




SUB 


Rs,Rd 


3 9 


4A 


(Rd) - (Rs) -* (Rd) 




SUB 


#iop8,A 


2 6 


2A 


(A) - iop8 - (A) 




SUB 


#iop8,B 


2 6 


5A 


(B) - iop8 -* (B) 




SUB 


#iop8,Rd 


3 8 


7A 


(Rd) - iop8 - (Rd) 


Status Bits 












Affected 


C 


Set to 1 if 


no borrow, otherwise set to 



Description 
Examples 



N Set on result 
Z Set on result 

V ((C XOR N) AND (Source[Bit 7] XOR Destination [Bit 7])) 

SUB performs 2's complement subtraction. The carry bit is set to if a 
borrow is required. The carry bit could be thought as a "no-borrow" bit in 
this case. 

LABEL SUB R19,B ;(B) minus (R19) is 

;store(i in B 

SUB 076h,A ; (A) minus 076h is stored 
; in A 

SUB R4,R9 ;(R9) minus (R4) is stored 
;in R9 



12-83 



SWAP 



Swap Nibbles 



SWAP 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 



Examples 



[<label>] SWAP <Rn> 

Bits (7,6,5,4, / 3,2,1,0) -* Bits (3,2,1,0, / 7,6,5,4) 

inst operands bytes cycles opcode 
SWAP A 1 1 1 B7 

SWAP B 1 11 C7 

SWAP Rn 2 9 D7 

C Set to bit 4 of original register or Bit of result register 

N Set on results 

Z Set on results 

V -0 

SWAP exchanges the first four bits with the second four bits. This in- 
struction is equivalent to four consecutive RL (rotate left) instructions. It 
manipulates four bit operands, especially useful for packed BCD operations. 

LABEL SWAP R45 ; Switch Lo and Hi nibbles of R45 

SWAP A ; Switch Lo and Hi nibbles of A 

SWAP B ; Switch Lo and Hi nibbles of B 



12-84 



TRAP 



Trap to Subroutine 



TRAP 



Syntax 


[<label>] TRAP 


<n> where n = 


thru 1 5 


Execution 


(SP) + 1 
(PC MSB) - 
(SP) + 1 
(PC LSB) 
(Entry vector) -* 


(SP) 

((SP)) 

(SP) 

((SP)) 

(PC) 






Options 


inst 
TRAP 


operands by 


tes cycles 


opcode 
EF 


Entry-vector 
MSB LSB 




1 


14 


7FDE 7FDF 




TRAP 


1 1 


14 


EE 


7FDC 7FDD 




TRAP 


2 1 


14 


ED 


7FDA 7FDB 




TRAP 


3 1 


14 


EC 


7FD8 7FD9 




TRAP 


4 1 


14 


EB 


7FD6 7FD7 




TRAP 


5 1 


14 


EA 


7FD4 7FD5 




TRAP 


6 1 


14 


E9 


7FD2 7FD3 




TRAP 


7 1 


14 


E8 


7FD0 7FD1 




TRAP 


8 1 


14 


E7 


7FCE 7FCF 




TRAP 


9 1 


14 


E6 


7FCC 7FCD 




TRAP 


10 1 


14 


E5 


7FCA 7FCB 




TRAP 


11 1 


14 


E4 


7FC8 7FC9 




TRAP 


12 1 


14 


E3 


7FC6 7FC7 




TRAP 


13 1 


14 


E2 


7FC4 7FC5 




TRAP 


14 1 


14 


El 


7FC2 7FC3 




TRAP 


15 1 


14 


EO 


7FC0 7FC1 


Status Bits 












Affected 


None 










Description 


Trap is 


a one-byte s 


ubroutine call. The operand <n> 



identifies a location in the trap vector table, addresses 07FC0h to 07FDFh 
in memory. The contents of the two-byte vector location form a 1 6-bit trap 
vector to which a subroutine call is performed. The TRAP is more efficient 
than a CALL when invoking the same routine more than once because less 
bytes are needed. The subroutine addresses are stored like all other ad- 
dresses in memory, with the least significant byte in the higher-addressed 
location, as indicated above. 



Example label trap 

.sect trap, OVFCOh 



; Execute subroutine at TRAPONE 

;Define section starting 
;at 7FC0h 



.word TRAP 15, TRAP 14 ;Define TRAPS 15 AND 14 

; subroutine entry points 



12-85 



TST 



Test. Set Flags from Register 



TST 



Syntax 


[<label>] TST < [A],[B]> 


Execution 


C,N,Z,V bits affected 


Options 


inst 
TST 
TST 


operands bvtes cycles opcode 
A 1 9 BO 
B 1 10 C6 


Status Bits 
Affected 


C 

N 

Z 
V 


-0 

Set or cleared based on operand 

Set or cleared based on operand 

^0 


Description 


TST 


sets the status bits according to th 



lows conditional Jumps on the value in the register. 



Example 



LABEL TST A 



TST B 



; Check for zero and negative 
; conditions in register A 

; Check for zero and negative 
; conditions in register B 



12-86 



XCHB 



Exchange >A/ith Register B 



XCHB 



Syntax 

Execution 

Options 



Status Bits 
Affected 



Description 
Examples 



[<label>] XCHB <Rn> 
(B) --> (Rn) 



in St operands 
XCHB A 
XCHB B 
XCHB Rn 



bytes cycles opcode 
1 10 B6 

1 10 C6 

2 8 D6 



operation 

(A) - - (B) 

(B) - - (B) (TST B) 
(Rn) - - (B) 



C *-o 

N Set on original contents of B 
Z Set on original contents of B 

V -0 

XCHB exchanges a register with Register B without going through an in- 
termediate location. The XCHB instruction with the B Register as the op- 
erand is equivalent to the TST B instruction. 

LABEL XCHB A ; Exchange Register B with 
; Register A 

XCHB R3 ; Exchange Register B with R3 



12-87 



XOR 



Exclusive OR 



XOR 



Syntax 


[<label>] XOR 


<s> 


,<d> 






Execution 


(s) XOR (d) -» (d) 








Options 


inst 


operands 


bvtes 


cycles 


opcode 


operation 




XOR 


A,Pd 


2 


9 


85 


(A) XOR (Pd) -* (Pd) 




XOR 


B,A 


1 


8 


65 


(B) XOR (A) ^ (A) 




XOR 


B,Pd 


2 


9 


95 


(B) XOR (Pd) -> (Pd) 




XOR 


Rs,A 


2 


7 


15 


(Rs) XOR (A) - (A) 




XOR 


Rs,B 


2 


7 


35 


(Rs) XOR (B) ^ (B) 




XOR 


Rs,Rd 


3 


9 


45 


(Rs) XOR (Rd) -* (Rd) 




XOR 


#iop8,A 


2 


6 


25 


iop8 XOR (A) -* (A) 




XOR 


#iop8,B 


2 


6 


55 


iop8XOR (B) - (B) 




XOR 


#iop8,Rd 


3 


8 


75 


iop8XOR (Rd) -* (Rd) 




XOR 


#iop8,Pd 


3 


10 


A5 


iop8XOR (Pd) - (Pd) 


Status Bits 














Affected 


C 


*-o 












N 


Set on result 










Z 


Set on result 










V 


*-o 










Description 


XOR 


performs a 


bit-wise excl 


usive OR operation on the operc 



. The 
XOR instruction can be used to complement bits in the destination operand. 
This operation can also toggle a bit in a register. If the bit value in the 
destination needs to be the opposite from what it currently is, then the 
source should contain a 1 in that bit location. 



Examples 



LABEL XOR R98,R125 

XOR #01,R20 
XOR B,A 



;XOR (R98) with (R125), 
; store in R125 

;Toggle bit in R20 

;XOR (B) with (A), store 
; in register A 



12-88 



introduction 



TIVIS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module HH 



Analog-To-Digital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Infomiation 



Appendixes 



13. Design Aids 



This section contains sample TMS370 applications to aid the programmer In 
system development. 

This section covers the following topics: 

Section Page 

13.1 Microprocessor Interface Example 13-2 

13.1.1 Read Cycle Timing 13-7 

13.1.2 Write Cycle Timing 13-10 

13.1.3 Design Options 13-12 

13.1.4 Software Examples For Bank Switching 13-13 

1 3.2 Programming with the TMS370 Family 13-15 

13.3 Serial Communications 13-18 

13.3.1 SPI Port Interfacing 13-18 

13.3.2 SCI Port Interfacing 13-19 

13.4 Analog/Digital Converter 13-21 

13.5 Sample Routines 13-22 

1 3.5.1 T1 PWM Pin Setup 1 3-22 

13.5.2 Clear RAM 13-23 

13.5.3 RAM Self Test 13-23 

13.5.4 ROM Checksum 13-24 

13.5.5 Binary-to-BCD Conversion 13-25 

13.5.6 BCD-To-Binary Conversion 13-25 

13.5.7 BCD String Addition 13-26 

13.5.8 Fast Parity 13-27 

13.5.9 Bubble Sort 13-27 

13.5.10 Table Search 13-28 

13.5.11 16-by-1 6 (32-Bit) Multiplication 13-29 

13.5.12 Keyboard Scan 13-29 

13.5.13 Divide 1 13-31 

13.5.14 Divide Instruction 2 13-31 



13-1 



Design Aids 



13.1 Microprocessor Interface Example 

The following exercise Is one method of Interfacing the TMS370 family with 
common memory. The goals of this example are as follows: 

• Interface with the maximum amount of memory 

• Use the least expensive logic elements 

• Use a minimum amount of parts 

• Maintain sufficient system speed 

The example shown in Figure 13-1 Illustrates a balance of these goals. In this 
case, the TMS370C850 is used with three TMS27C256s to provide 96K bytes 
of EPROM and two HM6264LP-15s to give 16K of RAM. Peripheral devices 
using up to 64 bytes of memory space may also interface to the bus. This gives 
a total memory of 1 1 6K; 1 1 2K of external memory and 4K memory internal to 
the microprocessor. The current timings for the EPROM and RAM memory 
devices are given in Table 13-1. Since specifications change from time to 
time, always check the latest data sheets for the devices used. 



13-2 



Design Aids 



ui 



R/W 
CSE2 
CSET 
CSPF 
CSH3 
CSH2 



ADDRESS 0-14 

DATA 0-7 

MC 




vss 



UI - TMS370C850 8-BIT MICROPROCESSOR 
U2, U3, U4 - TMS370C850 32K x 8 EEPROM 
U5 - UNSPECIFIED 64 BYTE MEMORY 
U6, U7 - HM6264-15 8K x 8 RAM 



Figure 13-1. Microprocessor Interface Example 



13-3 



Design Aids 



The devices used in the TMS370/lnterface Example Circuit are: 
TMS370C850 - 8-bit CMOS microcomputer 
TIVIS27C256 - 32K x 8 EPROM 
HM6264LP - Hitachi 8K x 8 RAM 



The timing specifications for the TMS27C256-30 EEPROM devices are as 
follows: 



Symbol 


Description 


Min 


Max 


ta(A) 


Access time from address 


-- 


300 ns 


ta(E) 


Access time from enable 


-- 


300 ns 


^dis 


Output disable time 


ns 


105 ns 


tv(A) 


Output data valid after addr. change 


ns 


-- 



Reference: 1986 Tl MOS Memory Data book 

The timing specifications for the HM6264P-1 5 RAM device are as follows: 



Svmbol 


Description 


Min 


Max 


^AA 


Address access time 


-- 


150 ns 


^OHZ 


Out disable to output in high Z 







tcoi 


Chip selection to output 


-- 


150 ns 


^HZI 


Chip Deselection to output in high Z 


ns 


50 ns 


^CW 


Chip select to end of write 


100 ns 


-- 


twp 


Write pulse width 


90 ns 


-- 


tow 


Data to write time overlap 


60 ns 


-- 


^DH 


Data hold from write time 


ns 


-- 



Reference: #M10 Hitachi Memory Data Book 

The TMS370 family is designed to use a clock speed of 20 MHz. This means 
that slower peripheral devices may not be able to react quick enough to op- 
erate properly. The TMS370C050 has the ability to insert Wait states to slow 
the bus accesses in three different ways. The first way uses the AUTOWAIT 
DISABLE bit at SCCR1.4 to add 1 wait state to all external accesses. The 
second way uses the PF AUTOWAIT bit at SCCR0.5 to add 2 wait states to 
the external peripheral file access in order to acco mmad ate slower devices. 
The third way allows the external device to pull the WAIT pin low and add as 
many wait states as is required to service the slower device. The table below 
shows the various combinations. 



13-4 



Design Aids 



Table 13-1. Walt State Control Bits 



Wait State 
Control Bits 


No. of Clock Cycles 
per Access 


PF Auto 
Wait 


Autowait 
Disable 


PF 
File 


External 
Memory 








3 


3 





1 


2 


2 


1 





4 


3 


1 


1 


4 


2 



13-5 



Design Aids 



Table 13-2. Memory Interface Timing 



SYMBOL 


PARAMETER 


MIIM 
(nS) 


MAX 
(nS) 


tc:t 


CLKOUT (system clock)cycle time 


200 


2000 


tw(COH) 


CLKOUT high pulse duration 


.5te 


.5t c+20 


tw(COL) 


CLKOUT low pulse duration 


.5tc-20 


.5tc 


td(COL-A) 


Delay time. CLKOUT low to address, R/W, 
and OCF 




.25tc+40 


tv(A) 


Address valid to EDS, CSE1, CSE2, CSH1 
CSH2,CSH3, and CSPFlow 


.5tc-50 
.5tc-50 




tsu(D) 


Write data setup time to EDS high 


.75t c-40t 




th(EH-A) 


Address, R/W, and OCF hold time from EDS, 
CSE1, CSE2, CSH1,CSH2, CSH3, and CSPF high 


.5tc-40 




th(EH-D)W 


Write data hold time from EDS high 


.75tc+15 




td(DZ-EL) 


Delay time, data bus high impedance to 
EDS low (read cycle) 


.25tc -30 




td(EH-D) 


Delay time,EDS high to data bus enable 
(read cycle) 


1 .25t c-40 




Td(EL-DV) 


Delay time, EDS low to read data valid 




t c-65t 


th(EH-D)R 


Read data hold time from EDS high 







tsu(WT-COH) 


WAIT setup time to CLKOUT high 


.25tc+75§ 




th(COH-WT) 


WAIT hold time from CLKOUT 







td(EL-WTV) 


Delay time, EDS low to WAIT valid 




.5t c-70 


tw 


Pulse duration; EDS, CSE1, CSE2, CSH1, CSH2, 
CSH3, and CSPF low 


t c-40^ 


tc+40t 


td(AV-DV)R 


Delay time, address valid to read data valid 




1.5tc-75t 


td(AV-WTV) 


Delay time, address valid to WAIT valid 




tc-85 


td(AV-EH) 


Delay time, address valid to EDS high 
(end of write) 


1 .5t c-40* 





Notes: t 
t 
§ 



tcis defined to be 2/fosc 

and may be referred to as a machine state or simply a state. 

If wait state, PF Wait, or Auto-Wait feature is used, add 

tc to this value for each wait state invo ked. 

If the Auto- Wait feature is enabled, the WAIT 

input may assume a "Don't Care" condition until the third 

cycle of the access. 



The following paragraphs discuss the more important signal timings that need 
to be considered when interfacing the TMS370 with external memory. With 
each system design there are usually trade-offs due to speed and/or budget 
constraints. The timings given here reflect worst case specifications and typ- 
ical values have been avoided where possible. 



13-6 



Design Aids 



13.1.1 Read Cycle Timing 

The TMS370 requires a minimum amount of address-to-data access time de- 
pendent on the CPU clock speed and the number of wait states used. When 
interfacing the TMS370 with external memory devices, the following require- 
ments need to be met or incorrect data may be read. These requirements are 
based on a 20 MHz clock frequency. 

13.1.1.1 Valid Address To Data Read Time Requirement 

The valid address to data read time requirement is the basic read cycle re- 
quirement that must be met by the external device. This requirement is de- 
scribed as the period from the instant the TMS370 outputs a valid address 
until the TMS370 requires data on the data bus pins. This requirement is 
variable by using wait states to delay the moment the TMS370 reads data. 



VALID 
ADDRESS - 
ON BUS 
(FROM TMS370) 




z 



DATA 
ON BUS ~ 
(FROM MEMORY) 



DATA 
REQUIRED ■ 
BY TMS370 
(FROM MEMORY) 



Figure 13-2. Valid Address-To- Data Read Timing 



Formula 


Time 


1.5tc-75 


225 ns(too fast) 


2.5tc -75 


425 ns(ok) 


3.5tc -75 


625 ns(ok) 




450 ns(too slow) 




300 ns(ok) 




150ns(ok) 



Name Description 

td(AV-DV)R TMS370 (0 wait) requires data 

tciCAV-DVJR TMS370 (1 wait) requires data 

td(AV-DV)R TMS370 (PF wait) requires data 

ta(A) TMS27C256-45 provides data 

ta(A) Ti\/IS27C256-30 provides data 

tAA HM6264-1 5 provides data 

As indicated above, the EPROM (TMS27C256) cannot provide the the data 
quick enough when the TMS370 device runs at full speed (zero wait states.) 
Therefore, the TMS370 device should use the Auto-Wait feature (SCC1.4) to 
add a wait state (one clock cycle) to the timing, in order to slow the bus ac- 
cesses. The wait state extends the access time (data required by TMS370) 
until 425 ns, and by that time the EPROM is ready with the data. The Auto- 
Wait feature allows the TMS370 to be used in low cost applications where 
cheaper, slower memory devices are to be used. The HM6264-1 5 can exceed 
the TMS370's minimum address-to-data setup time with no wait states. The 
Auto- Wait feature may be turned off when accessing external RAM compa- 
rable to the Hitachi device to speed system throughput. 



13-7 



Design Aids 



A peripheral device may have up to 625 ns to respond to the TMS370 if the 
Peripheral Wait states are enabled. If the extra wait states are not needed, the 
TMS370 treats the peripheral device like other memory. 



13.1.1.2 Chip Select Low To Data Read Requirements 

This parameter states the amount of delay from the time the chip select signal 
goes low to the t ime the TMS370 expects valid data on the bus. The chip se- 
lect (CSxx or EDS) signal (s) must be used with external memory to validate the 
memory cycle. Connnecting the Chip Select (CSxx) pin of the TMS370 to the 
EPROM's enable (E) pin allows the EPROM to enter the low power Standby 
mode when not providing data. This significantly lowers the power require- 
ments for the system because only one EPROM operates in the full-power 
operating mode at any one tim e. The HM6264 also enters a low-power 
standby mode whenever the CS1 pin is used with a TMS370 chip select pin. 



Name 

td{EL-DV) 
td(EL-DV) 
td(EL-DV) 
ta(E) 

tcoi 



Description 

TMS370 (0 wait) requires data 
TMS370 (1 wait) requires data 
TMS370 (pf wait) requires data 
TMS27C256-30 provides data 
HM6264-15 provides data 



Formula Time 



tc-65 
2tc-65 

3tn-65 



1 35 ns(too fast) 
335 ns(ok) 
535 ns{ok) 
300 ns(ok) 
150 ns(ok) 



EDS/ 

CSxx 

(FROM TMS370) 



*a(E) 
or 

tcOl 



td(EL-DV) 



DATA 
ON BUS ' 
(FROM MEMORY) 



V7/7Z. 



DATA 
REQUIRED ' 
BY TMS370 
(FROM MEMORY) 



V. 



z. 



Figure 13-3. Chip Select Low To Data Read Timing 



13-8 



Design Aids 



13.1.1.3 Chip Select High To Next Data Bus Drive Requirements 

The TMS370 and the Memory device should not drive the bus at the same 
time. This can lead to increased stress and noise spiking on the Vcc and Vss 
lines, reducing the reliability of the device. Memory devices often continue to 
drive the bus for a short time after the chip select signal goes high. This nor- 
mally doesn't present a problem unless the chip select signal is delayed by 
interface circuitry and the data is not. If the chip select high transition is de- 
layed long enough (and the data is not), the TMS370 will have initiated a 
write cycle while the memory is still providing (reading) data. 



Name 

td(EH- 
tdis 
tdis 
tOHZ 


Description 

D) TMS370 (all) drives bus 

TMS27C256-45 releases bus 
TMS27C256-30 releases bus 
HM6264-15 releases bus 


Formu 

1.25tc- 


la 

40 


Time 

210 ns 
130 ns 
105 ns 
50 ns 




^ td(EH-D) 

*-tdis -*-i 
1 








EDS/ 
CSxx 










(FROM TMS370) 








^:i^///////////. 














(FROM MEMORY) 








DATA 


v// 




ON BUS 








v// 



(FROM TMS370) 

Figure 13-4. Chip Select High To Next Data Bus Drive Timing 



13.1.1.4 Read Data Hold After Chip Select High Requirements 

The high transition of the Chip Select signal indicates the end of a data 
transfer (in this case, a Read) cycle. The memory device must provide data up 
to this point, otherwise, incorrect data may be read. Most memories will con- 
tinue to hold (or drive) the data bus for a short time after they are deselected, 
althought the data may or may not be valid. After that period, the memories 
put their data outputs into the high-impedence state. 



Name Decsription 

td(EH-D)R TMS370 (ail) needs data 

tv(A) TMS27C256-30 data 

tHzl HM6264-1 5 holds data 



Formula Time 

ns 
ns 
ns 



13-9 



Design Aids 



EDS/ 

CSxx 

{FROM TMS370) 



DATA 
REQUIRED "y 



BY TMS370 



(FROM MEMORY) 



td(EH-D)R 




Figure 13-5. Read Data Hold After Chip Select High Timing 



13.1.2 Write Cycle Timing 



The write cycle timing is defined primarily by the characteristics of the RAM 
interfacing with the TMS370. The Hitachi HM6264 used in the example offers 
two types of write cycles and this application uses the type where th e ou tput 
enable (OE) pin is always fixed low. With the CS2 pin tied to Vcc, the CS1 and 
R/W signals determine the read and write cycle boundaries. A seperate ad- 
dress decoder may be used instead of the chip sele ct fu nctions, but the EDS 
must be used to validate the memory cycle. The EDS signal has the same 
timing as the chip select signals. Figure 13-6 shows the write cycle parame- 
ters that need to be met and are discussed in the following paragraphs. 



Name 

% 
% 
tew 



Description 



Formula Time 



TMS370 (no wait) pulse width provided tc-40 160 ns 

TMS370 (pf wait) pulse width provided 3tc-40 560 ns 

HM6264-15 pulse width required 100 ns 



13.1.2.1 Write Data Setup Time Requirements 

The write data setup time is the period the RAM needs to receive data before 
the chip select signal goes high (inactive). 



Name Description 

tsu(D) TMS370 (no wait) provides data 

tsu(D) TMS370 (pf wait) provides data 

tow HM6264-15 requires data 



Formula Time 

.75tc-40 110 ns 
2.75tc-40 510 ns 
60 ns 



13-10 



Design Aids 



R/W 
(FROM TMS370) 



EDS/ 

CSxx 

(FROM TMS370) 



DATA 

ON BUS 

(FROM TMS370I 



' tsu(D) 



l"^«h(EH-D)W- 
I 



V//////////A 



DATA 

REQUIRED 

BY RAM 

(FROM TMS370) 



y//////A 



Figure 13-6. Write Data Setup Timing 



In the interface example the TMS370, even with no wait state, satisfies the 
Hl\/I6264-15 RAM's setup requirement. In a system design where bus tran- 
ceivers have been added, however, setup timing becomes more important. 

13.1.2.2 Data Hold After Chip Select High 

The TI\/IS370 must hold valid data on the bus until the RAM no longer needs 
it, otherwise, incorrect data may be written into the RAM. Most RAM do not 
need data present on the pins following the chip select's high transition. The 
TMS370 generally holds data much longer than required by most RAM. 



Name 

th(EH-D)W 
tOH 



Description 

TMS370 (all) provides data 
HM6264-15 requires data 



Formula Time 



.75tc+15 



165 ns 
ns 



13-11 



Design Aids 



EDS/ 
CSxx 
(FROM TMS370)" 



' th(EH-D)W- 

-I 



DATA/^ 
ON BUS ' 
(FROM TMS370) 



—zzzzzzzzzz. 



BY RAM 



(FROM TMS370) 

Figure 13-7. Write Data Hold After Chip Select High 



13.1.3 Design Options 



The interface example ilustrated in Figure 13-1 shows a compromise of sys- 
tem speed and cost. As with all projects, a priority of design goals must be 
established. Below are some suggestions for optimizing a system toward these 
goals. 



13.1.3.1 Lower Cost 



If system cost becomes more important, then slower ROMs which are less 
expensive should be used. The slowest EPROM for this device is the 
TMS27C256-45 with 450 ns access time. However, even with one wait state 
the TMS370 needs data before this EPROM can supply it. A 1 9 MHz or lower 
crystal oscj^llator solves the problem by extending the clock cycle time. The 
EPROM's E pin can no longer be used as enable strobe_because of the slower 
response time. The system must use the EPROM's G pin which provides 
sufficient time. 

A designer still desiring the low power standby mode needs to connect the I 
pins of all of the EPROM's to one or more general purpose I/O pins on the 
TMS370. Software can then turn off the EPROMs when not in use. Since the 
RAMs have no trouble meeting the requirements of a 20 MHz 
clock, a slower crystal speed presents no problem. 

A. Access time from address to valid data (@ 19 MHz, tc=210.5) 

TMS370 (1 wait) requires data tD(AV-DV)R 2.5t c-75 451ns 
TMS27C256-45 provide data tA(A) 450 ns (ok) 



B. Access time from enable low to valid data 
TMS370 (1 wait) requires td(EL-DV) 



19 MHz, tc=210.5) 
2tc-65 335 ns 



13-12 



Design Aids 

TMS27C256-45 provides data tA(E) I pin 450 ns{not ok) 

TMS27C256-45 provides data tEN(G) G pin 135ns(ok) 

13.1.3.2 Faster Speed 

If the main objective is system speed, then the slowest EPROM that will work 
with the TMS370 running without wait states should be used. The TMS370 
at 20 MHz has a read access time requirement of 225 ns, therefore the 
TMS27C256-20 EPROM which provides data in 200^ ns should be used. As 
with the low cost suggestions above, the EPROM's E pin is not fast enough 
to use the chip select strobe. The EPROM's G pin should be used instead. To 
get a low power standby mode with the EPROMs, use general purpose output 
lines from the TMS370 to the EPROM's E pin. The pins should be software 
enabled before entering the EPROM's program. 

A. Access time from address to valid data: 

TMS370 (no wait) requires data tD(AV-DV)R 1.5tc-75 225 ns 
TMS27C256-20 provide data tA(A) 200 ns (ok) 

B. Access time from enable low to valid data: 

TMS370 (no wait) requires tD(EL^DV) t^-65 135 ns 

TMS27C256-20 provides data tA(Ei E_pin 200 ns (not ok) 

TMS27C256-20 provides data tEN(G) Gpin 75 ns (ok) 

13.1.4 Software Examples For Bank Switching 

The following programs show how memory bank switching can be used by 
the circuit in Figure 13-1. Memory bank switching allows two or more me- 
mory devices to s hare t he same addresses. The programmable chip select 
(CSHx, CSEx, and CSPF) signals are used to enable the memory devices or 
"banks" one at a time during a read or write cycle. 

In the interface example, the three EPROM devices share addresses 8000h 
though F FFFh. Only one EPROM device (or bank), selected by either CSH1, 
CSH2, or CSH3, will be reading data at any one time. The two RAM devices 
are each mapped at addresses 2000h through 3FFFh. The wri te an d rea d cy- 
cles involve one R AM device at a time as determined by the CSE1 and CSE2 
signals. The CSPF signal controls the peripheral memory device which in our 
example is unspecified but defined to contain 64 bytes of memory. This de- 
vice is mapped at addresses lOCOh through lOFFh. 

To use external memory, the TMS370Cx50 must be configured for the micro- 
computer mode so that the chip select signals are available for use. The ex- 
ternal memory devices must have 3-state outputs, since these devices share 
the data bus. 



13-13 



Design Aids 



13.1.4.1 Initialize to EPROM/RAM Bank 1 

The following program initializes the ports to use bank 1 of the EPROM and 
the RAM as used in Figure 1 3-1 . The TMS370 must be in the microcomputer 
mode since the chip selects are not available in the microprocessor mode. 
After an external reset the TMS370 executes from the internal memory. 



PORTI OR #020h,P010 
AND #0EFh,P011 



MOV 
MOV 


#OFFh 
#OFFh 


P021 
P025 


MOV 


#07Fh 


P029 


MOV 


#000h 


P02B 


MOV 
MOV 


#000h 
#0E7h 


P02C 
P02E 


MOV 


#ODOh 


P02D 


MOV 


#0E7h 


P02F 



Enable Peripheral file 

auto-wait cycles 

Enable General memory wait 

cycles (default condition 

after reset) 

Set Port A up as a Data Bus 

Set Port B up as the Low 

Address bus 

Set Port C 0-6 up as the High 

address bus 

C7 is not needed for address 

so make it a 

general purpose input. 

Set all CSxx to 1 when CSxx 

are outputs 

Enable CSHl, CSEl, and 

R/W functions. 

Turn all Chip Selects to outputs. 

Pull-ups resistors are important 

for power-up since CSxx are high 

impedance floating inputs. 



13.1.4.2 Changing to EPROM Bank 2 

The following program illustrates how to change the EPROM bank while 
leaving the RAM banks unaffected. In this example, the program runs out of 
internal memory and disables all EPROM banks and then enables EPROM 
bank 2 for use. For this reason, the program must not reside in an EPROM. 
The program could test various EPROM bank 2 memory locations before ex- 
ecuting the branch instruction in order to verify that EPROM bank 2 exists 
within the system. 



AND #0B9h,P02D 
OR #004h,P02D 
BR R0M2 



;Disable all EPROM banks (cannot 

;be done in EPROM banks. 

; Enable EPROM bank 2. When turned off, 

;pin outputs a 1 because of the 

; initial setup above, could be done 

; in 1 instruction if conditions of 

; other chip selects was known. 



13-14 



Design Aids 



13.1.4.3 Change To EPROM Bank 3 and RAM Bank 2 

This routine provides switching from one EPROM bank to another while op- 
erating from an EPROM bank. Only one instruction (in EPROM bank 2) is 
needed. The code within the EPROM banks must be synchronized, and the 
instruction at the address after the move instruction must be a valid instruction 
within the new EPROM bank. 

G0R0M3 MOV #003h,P02D ; Enable ROM bank 3 and RAM bank 2. 

R0M3 ;This address must be the same 

;as the beginning routine address 
; in bank 3 if executing from EPROM. 

13.1.4.4 Change RAM Banks 

This method shows how to change RAM banks without affecting the exe- 
cution out of the current EPROM bank. The RAM banks are selected and 
deselected the same as EPROM banks. When changing RAM or EPROM 
banks, the software must insure that only one bank is selected at a ny on e time. 
This example disables the CSE1 and CSE2 signals and enables the CSE2 signal. 

AND #07Eh,P02D ;Turn off all RAM banks (execute 
;from EPROM or on chip) 
OR #001h,P02D ;Turn on RAM bank 2. When turned off, 
;pin outputs a 1 because of the 
; initial set-up above 

13.2 Programming with the TMS370 Family 

The following example demonstrates the self-programming ability of the 
TMS370 family. This feature can be used to program any byte of the onboard 
data and program EEPROM by passing the appropriate data and address to 
this routine. 

This program consists of 3 major sections: the procedure that loads the core 
program into RAM (RAMJAM), the procedure that determines the bits that 
need to be changed (PROGRAM), and the procedure that changes these bits 
(RAMPROG). 

RAMJAM is a routine that moves the 19 byte core programming routine into 
RAM starting at address 20h in the Register area. It only needs to run once 
during the initialization portion of the program. 

PROGRAM attempts to save programming time by checking which portions 
of the 2 step programming procedure have to occur. If the data already in the 
array is the same as the new wanted data then no programming need occur. 
If the program can omit a 'write ones' or a 'write zeros' operation then 10 ms 
is removed from the total 20 ms programming time. Every programming step 
that this routine omits saves 1 ms. 

RAMPROG is the RAM resident routine which initiates, times and then stops 
the actual EEPROM programming. During this section of code the interrupts 
should be disabled to avoid having to use the Program memory. All program 
memory is disabled while programming the program EEPROM so neither a 
routine execution or interrupt vector access can occur during the program cy- 



13-15 



Design Aids 



cle. RAM PROG resides in RAM because it needs to program both Data and 
Program EEPROM for this general purpose example. 

All read and write access to an entire EEPROM array are disabled while any 
one byte in the array is being programmed. This means that a program cannot 
execute out of Program EEPROM while programming it. Likewise the pro- 
gram cannot execute out of Data EEPROM if it is being programmed. The 
only other place to locate the core routine which does the actual programming 
is in the RAM. This general purpose core program takes only 1 9 bytes of RAM 
and can program both the data and program EEPROM arrays. This core rou- 
tine could reside in program memory if only data EEPROM needed program- 
ming and vise versa. 

Unprotected data EEPROM may be programmed using only the Vcc power 
supply. Enter the WPO mode by placing 12V on the MC pin when program- 
ming program EEPROM or protected data EEPROM. 

The Program EEPROM array cannot be used while it is programming so the 
actual program code must reside in other memory, the most general being 
RAM. This section resides in the initialization routine and loads the code to 
program EEPROM into the RAM. (if only Data EEPROM needs programming 
the RAMPROG code can reside in regular ROM and the RAMJAM section 
removed.) 



TEMPI .EQU R3 

ETYPE .EQU R7 

EECTL .EQU lOlAh 

RAMJAM MOV #19,B 

FILLRAM MOV @RAMPR0G-1 (B ) , A 

MOV A,@20h-1(B) 
DJNZ B, FILLRAM 
JMP MOREINIT 



general purpose 16 bit 

register 

EEPROM array type 0= data, 

2=prograin 

index address for eeprom 

control register 

Transfer 19 bytes 

Move small program from ROM 

into RAM starting at 20h 

fill RAM 

Goto more initialization 

program 



The processor must be in single chip mode for correct operation during this 
core routine. 

A= EECTL value xx/blk/ 

ones/execute 

ETYPE = EEPROM array type 0=Data 

2=Program 

Routine's real address is 20h, 

EEPROG=20h 

EECTL index to B (data=0, 

program =2) 

Load proper EECTL register 

Wait 10 ms for eeprom write 

llcy: (18 cycles *.2 us/cycle) 

* 2778 = 10 ms 
7cy: ( at 20MHz) 
stop programming pulse 
clear out EECTL 

exit from internal Ram program 
19 bytes total 

The following program is used to write to any location in the data or program 
EEPROM. 



RAMPROG 


MOV 


ETYPE, B 




MOV 


A,EECTL(B) 


WAITIO 


MOVW 
INCW 


#2778, TEMPI 
#-1, TEMPI 


EXITRAM 


JC 
CLR 
MOV 
RTS 


WAITIO 

A 

A,EECTL(B) 



13-16 



Design Aids 



EXITW 



Parameters used: ADDR1 = EEPROM address; A= data to write to eeprom 
array 

ETYPE = 0= data eeprom; 2= program eeprom 

ETYPE set before entering this routine 

general purpose temporary 

register 

contains acSdress for 

program operations 

starting address of RAM 

code which programs eeprom. 

initialize eeprom type to 

Data EERPOM 

Data EEPROM resides at 

IFOOh to IFFFh 

Set to Program EEPROM type 

save data 

read current data 

different bits=l 

if byte is already equal 

then exit 

different bits=0 

bits that change from 

1 to = 

If any Os, then must 

program the zero's 

If all Is, advance to 

program Is part 

No interruptions 

Move data to array location 

EECTL value = 1 (program Os) 

do the write of only the 

needed Os 

interrupt can happen now 

get the current data 

bits that change = 1 

bits that change from 

to 1 = 1 

are there any Is to program? 

No interruptions 

Move data to array location 

EECTL value=3 (program Is) 

do the write of only the 

needed Is 

interrupt can happen now 

Check new memory against 

wanted memory 

if equal then exit 

;ERROR handling routine here 
(back to calling program 



TEMP2 


•EQU 


R4 


ADDRl 


-EQU 


R6 


EEPROG 


.EQU 


20h 


PROGRAM 


CLR 


ETYPE 




CMP 


#01Fh,ADDRl-l 


ISSAME 


JEQ 
MOV 
MOV 
MOV 
XOR 
JZ 


ISSAME 

#2, ETYPE 

A,TEMP2 

@ADDR1,A 

TEMP2,A 

EXITW 




INV 
OR 


A 

TEMP 2, A 




BTJZ 


#OFFh, A, WRITEO 




JMP 


ONES 


WRITEO 


DINT 
MOV 
MOV 
CALL 


A,@ADDR1 

#1,A 

EEPROG 


ONES 


EINT 
MOV 
XOR 
AND 


(aADDRl,A 
TEMP 2, A 
TEMP2,A 


WRITEl 


JZ 

DINT 

MOV 

MOV 

CALL 


LASTCHK 

A,@ADDR1 
#3, A 
EEPROG 


LASTCHK 


EINT 
MOV 


@ADDR1,A 




CMP 
JEQ 


TEMP2,A 
EXITW 



RTS 



The following example is the same as the PROGRAM routine above but with 
actual values given for each step. The values shown are the LSB nibble of a 
byte expressed in binary and choosen because they give all possible bit com- 
binations. In this example the memory address already has x1 1 00 and we want 
to program xlOlO to that address. Before calling the EEPROG routine, the 
program writes new data to the EEPROM address located in register AD- 
DRESS and then passes data in register A which specifies either a write ones 
or a write zeros operation. 



TEMP 2 @ADDRESS 



PROGRAM CLR 
CMP 
JEQ 
MOV 



xlOlO 
ETYPE ; xlOlO 
#01Fh,ADDRl-l;xl010 
ISSAME ; xlOlO 
#2, ETYPE ; xlOlO 



xllOO 




xllOO 


Data EEPROM type 


xllOO 


Data EERPOM at IFxxh 


XllOO 


Keep as data EERPOM 


XllOO 


Set Program EEPROM 




type 



13-17 



Design Aids 



ISSAME 


MOV 


A,TEMP2 


xlOlO 


xlOlO 


xllOO 


save data 




MOV 


@ADDR1,A 


xllOO 


xlOlO 


xllOO 


read current data 




XOR 


TEMP2,A 


xOllO 


xlOlO 




different bits = 1 




JZ 


EXITW 








if A =0 data the same 




INV 


A 


xlOOl 






different bits = 




OR 


TEMP2,A 


xlOll 


xlOlO 




is bit to change to 



program O's if any 

O's 

check writel' s 




BTJZ 


#FF, A, WRITEO ;xl011 








JMP 


ONES 








WRITEO 


DINT 




xlOll 


xlOlO 


xllOO 


disable interupt 




MOV 


A,@ADDR1 


xlOll 


xlOlO 


xlOll 


move data to address 




MOV 


#1,A 


xOOOl 






program to writeO's 




CALL 


@EEPROG 








do writeO's 




EINT 




xOOOO 


xlOlO 


xlOOO 


enable interupts 


ONES 


MOV 


(aADDRl,A 


xlOOO 


xlOlO 


xlOOO 


read new current data 




XOR 


TEMP2,A 


xOOlO 


xlOlO 




bits that change = 1 




AND 


TEMP2,A 


xOOlO 


xlOlO 




1 is bit to change to 1 




JZ 


LASTCHK 










WRITEl 


DINT 




xOOlO 


xlOlO 


XlOOO 


disable interupts 




MOV 


A,@ADDR1 






xOOlO 


move data to address 




MOV 


#3, A 


xOOll 






program to writel 's 




CALL 


OEEPROG 








do writel 's 




EINT 




xOOOO 


xlOlO 


xlOlO 


enable interupts 


LASTCHK 


MOV 
CMP 
JEQ 


OADDRljA 

TEMP2,A 

EXITW 


xlOlO 


xlOlO 


xlOlO 


read new current data 
compare to data wanted 
the same then return 




CALL 


@ERROR 


If the program 


gets here 


there has been an 








error 









EXITW 



RTS 



13.3 Serial Communications 



All devices in the TMS370 family provide serial communication capability with 
peripheral devices. The TMS370Cx10 series provides one serial (SPI) port 
providing communication capability with peripheral devices. The 
TMS370Cx50 series provides two serial (SPI and SCI) ports for enhanced 
communications capability with peripheral devices. 



13.3.1 SPI Port Interfacing 



The SPI port provides synchronous communication with peripherals such as 
shift registers, display drivers, A/D converters, and another CPU. Synchro- 
nous transmission is supported by programmable parameters such as character 
length (one to eight bits) and bit transfer rate (eight options). In the example 
below, the SPI port is configured as a Master/Slave dual CPU interface. This 
full-duplex setup has the master CPU initiating data transfer by sending the 
SPICLK signal to the slave. Data is then transmitted between the CPUs si- 
multaneously until the clock signal stops. Either or both of the data lines may 
send valid or dummy data, depending on the software. 



13-18 



Design Aids 



MASTER 
CPU 


DATA 




SLAVE 
CPU 


SPISIMO 

SPISOMI 

SPICLK 




SPISIMO 
SPISOMl 
SPICLK 


DATA 


CLOCK . 







Figure 13-8. Master/Slave CPU Interface Example 



13.3.2 SCI Port Interfacing 



The SCI port (TMS370Cx50 only) provides communication with peripheral 
devices in either an Asynchronous or Isosynchronous format. This makes it 
especially suited for communicating with a variety of devices. The format pa- 
rameters of the SCI are software programmable and are as follows: 



Parameter 

Mode 

Baud rate 

Character length 

Parity 

No. of stop bits 

Interrupt priorities 



Options 

Asynchronous, Isosynchronous 

64K possibilities 

1 to 8 bits 

Even, Odd, Off 

1 or 2 

Receiver/transmitter 



In the figure below, the SCI port is configured for a RS-232-C type interface. 
Since the TMS370 family uses TTL-level I/O, the transmit and receive data 
signals must be converted to RS-232 levels. The 75188 and 75189 devices 
provide this function. In the asynchronous format, the clock signal does hot 
need to be transmitted, but is generated locally at both ends. 




SCITXD 



SCIRXD 



75188 



TTL LEVEL 



75189 



+ 12 V 



TX OUT 



RX IN 



Figure 13-9. SCI/RS-232 Interface Example 



13-19 



Design Aids 



The following routine automatically calculates the baud rate for the SCI port 
by timing the length of the start bit. Many times this eliminates the need for 
external select switches which can cause confusion. 

This routine converts the Receiver pin to a general purpose input pin and then 
samples this pin until it finds the start bit. Sampling Is controlled by the baud 
rate counter, which takes 32 cycles for one complete count. At each count, 
or every 32 cycles, the input pin is sampled. When the start bit is received, it's 
low state is sampled until the high state of the first data bit (of an odd ASCII 
value) is detected. The number of times the start bit is sampled is used by the 
baud rate registers to figure the baud rate. 



IDLE 



START 
BIT 



DATA 
BIT 1 



DATA 
BIT 2 



HWAITSTRT-I— WAITBIT— H SETU 



Figure 13-10. Auto Baudrate Wavefornn 



0050 
0051 
0052 
0053 
0054 
0055 
0057 
0057 
005D 
005E 
005E 
005E 
0000 
0000 
0000 
7000 
7000 
7000 
7000 
7002 
7004 
7007 
7007 
700B 
700B 
700B 
700C 
700C 
700C 
700F 
7013 
7013 
7016 
7016 
7019 
7019 
701C 
701C 
701F 
7022 
7025 
7025 
7025 
7027 



SCICCR 

SCICTL 

BAUDMSB 

BAUDLSB 

TXCTL 

RXCTL 

RXBUF 

TXBUF 

SCIPCl 

SCIPC2 

SCIPRl 

COUNT 



. EQU P050 
.EQU P051 
.EQU P052 
.EQU P053 
•EQU P054 
.EQU P055 
,EQU P057 
.EQU P059 
,EQU P05D 
.EQU P05E 
.EQU P05E 
.EQU R04 



.TEXT 07000h ; INITIALIZE SCI PORT WITH 

A CR (RETURN) 
AUTOBAUD ;Baud automaticaly 

set on Odd ASCII 

character 

D504 CLR COUNT ; clear count register 
D503 CLR COUNT 1 ; COUNT- 1 
F7005E MOV #0,SCIPC2 ;set RxD to general 

purpose input pin 
A6085EFC WAITSTRT BTJO #8 ,SCI0C2 ,WAITSTRT ;wait for 

a start bit to go low 



B3 



WAITBIT INC 



700104 INCW #1, COUNT 
A7085EF8 BTJZ #8,SCIPC2, 



70FF04 SETUP INCW #-1, COUNT 

715304 MOV COUNT , BAUDLSB 

715203 MOV COUNT- 1, BAUDMSB 

F7225E.MOV #22h,SCIPC2 

F7025D MOV #2, SCIPCl 

F77750 MOV #01110111b, SCICCR 



SCI communication control register 

SCI control register 

baud rate counter MSB 

baud rate counter LSB 

Transmitter control 

Receiver control 

Receiver buffer 

Transmitter buffer 

Port control 1 (SCLK) 

Port control 2 (TXD,RXD) 

priority register 

temporary counting register 



dummy, gives 32 
clock states 
(1 min baud) 
increment counter 
WAITBIT ;wait until start bit 
ends (ASCII char=odd) 
one less than count 
into baud reg 
since the SCI starts 
from count 0. 
initialize baud rate 
registers. 

Enable Rx and Tx pins 
enable SCLK pin (if needed) 
8-bits length, even parity, 
1 stop ;bit 

only even, odd, or none parity 
determined 
by SCICCR value 



13-20 



Design Aids 

7025 F73351 MOV #00110011b,SCICTL; enable Tx, Rx, SCLK = internal 

702C ;program after input character 

7028 ;finishes) 

7028 F70154 MOV #1,TXCTL ; enable TX interrupts 

702B F70155 MOV #1,RXCTL ; enable RX interrupts 

702E 8057 MOV RXBUF,A ;clear out garbage from SCI (Place in 

7032 jprogram after input character finishes) 

7032 FOOC EINT 

This routine can be improved to give greater flexibility and accuracy using 
some of the following suggestions: 

1. Time more than one bit and then divide by the number of bits to give a 
greater accuracy. This means that a more carefully choosen character must 
be used to start the autobaud routine. The current routine can use 50 per cent 
of the ASCII values (all odd ASCII values). 

2. Add routine to check the parity of the incoming character and set the parity 
of the SCI port accordingly. Again, this means a limited number of characters 
will correctly autobaud the routine. 

3. Add routines to compare the count of another bit in the character to the 
start bit count as an accuracy check. This gives the same problems as before. 

13.4 Analog/Digital Converter 

The A/D converter provides the TMS370Cx50 with built-in data acquisition 
capability with 8-bit resolution. Any or all of the A/D pins may be used as a 
single-ended input with reference to analog ground (Vss3)- Pins not used 
for A/D conversion may be software configured as a standard digital input pin. 
The high reference voltage (Vref) may be either Vcc3 O"" supplied by one of 
the inputs. If the sampled input is higher than Vref. the conversion value 
placed in the A/D data register is FFh, indicating full scale. If the sampled 
input is lower than Vss3, then the value OOh is placed in the A/D data register. 

A variety of functions may be performed by the CPU using the A/D converter. 
Industrial applications may include temperature sensing, fluid level monitor- 
ing, and recharging circuit status as indicated in the figure below. If the 
sending units are designed for greater than Vref, then a resistance network may 
be needed to keep the A/D input voltage within the meaningful range of Vref 
to ground. This is especially true in the case of a fluid level sensor, where the 
full linear range may be required. 



13-21 



Design Aids 



+5 VDC 



TEMPERATURE 
SENSING 



+5 VDC 
o 



TMS370CX50 



THERMISTER 
K^ 




+5 VDC 



FLOAT POTENTIOMETER 





(j)+VDC 






_.\AA^ 




BATTERY 


VOLTAGE 
REGULATOR 






< 


STATUS 






1 


f 








J 




~ 






+ 







VcC3^efJ 



ANO 
AN1 
AN2 
AN3 
AN4 
AN5 
AN6 
AN7 



*SS3 



T 



Figure 13-11. A/D Converter Sample Applications 



13.5 Sample Routines 



The following section contains sample routines that show the various ways 
the TMS370 handles comrnon software tasks. 



13.5.1 T1PWIVI Pin Setup 



The following examples start and stop the PWM function with a certain value 
on the PWM pin. Starting the T1 PWM pin with a specific value can be done 
with one instruction as shown in the examples below. The value of the data 
out bit will become the initial value of the PWM pin. 

MOV #60h,P04E ; Start with PWM pin high 



MOV #20h,P04E 



; Start with PWM pin low 



The examples below show the two instructions needed when changing the 
T1 PWM pin from a PWM pin to a general purpose output pin with a specific 
value. The first instruction changes the pin to a general purpose output pin 
with the same-value as the current PWM pin. The second instruction changes 
the pin to a particular value. 

MOV #50h,P04E ;Stop with PWM pin high. 
MOV #50h,P04E 



MOV 
MOV 



#10h,P04E 
#10h,P04E 



;Stop with PWM pin low. 



The following examples keep the current value on the pin when starting or 
stopping the PWM functin. Starting the function requires four instructions 
while stopping the function takes only one. 



MOV #20h,A 
BTJZ #80h,P04E,SKIP 
MOV #60h,A 
SKIP MOV A,P04E 



Start with PWM pin same as 
current state. 



13-22 



Design Aids 



MOV #10h,P04E 



;Stop with PWM pin same as 
; current state. 



13.5.2 Clear RAM 



This routine clears all the internal RAM registers. It can be used at the begin- 
ning of a program to initialize the RAM to a known value. 





REGISTER 


FUNCTION 






A 




Holds the initialization value 






B 




Index 


nto the RAM 


0000 




0001 


.TEXT 


7000h 


; absolute start address 


7000 


52FE 


0002 
0003 


CLEAR MOV 


#254, B 


; number of register to clear 
;-2 


7002 


B5 


0004 
0005 


CLR 


A 


;load the initialization 
;value of zero 


7003 


ABOOOl 


0006 
0007 


LOOP MOV 


A, KB) 


; clear the location indexed 
;bY B+1 


7006 


CAFB 


0008 
0009 


DJNZ 


B,LOOP 


;loop until all RAM is 
; cleared 


7008 




0010 






;A and B end up as zeros. 



13.5.3 RAM Self Test 



This routine performs a simple alternating 0/1 test on the RAM. The RAM is 
tested by writing a AA,55 pattern to the entire RAM and then checking the 
RAM for this pattern. The inverted pattern is then written to RAM and re- 
checked. Finally, the entire RAM is cleared. If an error is found, a bit is set in 
the flag register. The error flag bit should be cleared before the routine is 
started. 







AFTER 


AFTER 


REGISTER 


BEFORE 


NO ERROR 


ERROR 


A 


XX 





? 


B 


XX 





? 


Rn 


XX 





? 


FLAG 


XX 





Bit 0=1 



0000 
OOOA 
7000 
7002 
7004 
7004 
7007 
7008 
700A 
700B 
700D 
7010 
7012 
7013 
7015 
7016 
7018 
701A 



2255 
52FD 

AB0002 

BC 

CAFA 

BC 

52FD 

AD0002 

06** 

BC 

CAF8 

BO 

OlEA 

02** 

B5 



Passing data 
Registers affected 
Ending data 



None 

All 

All registers = 

Bit in FLAG = 1 if error was found 



0001 
0002 
0003 
0004 
0005 
0006 
0007 
0008 
0009 
0010 
0011 
0012 
0013 
0014 
0015 
0016 
0017 
0018 



.TEXT 7000H 
FLAG .EQU RIO 

MOV #55h,A 
FILLR MOV #OFDh,B 



FILLl MOV 
RR 

DJNZ 
RR 
MOV 

COMPAR CMP 
JNE 
RR 

DJNZ 
CLRC 
JN 
JZ 

FILLO CLR 



A, 2(B) 

A 

B, FILLl 

A 

#OFDh,B 

2(B) ,A 

ERROR 

A 

B, COMPAR 

FILLR 
EXIT 
A 



absolute start address 

error register 

Start RAM fill with 55h 

Set RAM start address - 2 

(don't change register A or B) 

fill RAM with aa to 55 pattern 

change to beginning number 

fill entire ram with pattern 

change to beginning number 

refresh index 

check for errors 

exit if values don't match 

change from 55 to AA to 55 

check the entire RAM 

is reg A now 55, AA or 00? 

=AA, change to opposite pattern 

=00, 

=55, clear the ram now 



13-23 



Design Aids 



701B 00E5 
701D 74010A 
7020 
7020 



0019 JMP 

0020 ERROR OR 
0021 

0022 EXIT .EQU 



FILLR ;repeat the fill and check routine 
#1,FLAG ;set bit zero in the flag 
;register 
$ ; continue program here 



13.5.4 ROM Checksum 



This routine checks the integrity of the ROIVI by performing a checksum on the 
entire ROM. All ROM bytes from 7002h to 7FDFh are added together in a 
16-bit word. The sum is checked against the value at the beginning of the 
ROM (7000h, 7001 h). If the values don't match, then an error has occured 
and a bit is set in a register. The error flag bit should be cleared before the start 
of the routine. 



Note: Addresses 7FE0h through 7FEBh are reserved for Tl use only and 
should not be used in a checksum calculation. 







REGISTER 




BEFORE 


NO ERROR ERROR 






A 




XX 


? 






B 




XX 


? 






R2 




XX CHKSUM MSB CHKSUM MSB 






R3 




XX CHKSUM LSB CHKSUM LSB 






R4 




XX 


70h 70h 






R5 




XX 


01 h 01 h 






R6 




XX 


FFh FFh 






R7 




XX 


FFh FFh 






FLAG 




XX 


Bit 1=0 Bit 1=1 


0000 




0001 




TEXT 7000h 


absolute start address 


OOOF 




0002 FLAG 




EQU R15 


error status 


3039 




0003 CHECKSUM 


EQU 12345 


value to be checked 


7000 


3039 


0004 




WORD CHECKSUM 


put correct checksum into 


7002 




0005 






ROM 


7002 




0006 






other initialization 


7002 




0007 






program here 


7002 


887FDF05 


0008 ROMCHK MOVW #7FDFh,R5 


starting address (end of 


7006 




0009 






memory) 


7006 


880FDD07 


0010 


MOVW 


#0FDDh,R7 


number of bytes to add + 1 


700A 


88000003 


0011 


MOVW 


#0,R3 


reset summing register 


700E 




0012 








700E 


9A05 


0013ADDLOP MOV 


@R5,A 


get ROM byte 


7010 


480003 


0014 


ADD 


A,R3 


add to 16-bit sum 


7013 


790002 


0015 


ADC 


#0,R2 


add any carry 


7016 


70FF05 


0016 


INCW 


#-l,R5 


decrement address 


7019 


70FF07 


0017 


INCW 


#-l,R7 


decrement byte counter 


701C 


03F0 


0018 


JC 


ADDLOP 


continue until byte count 


701E 




0019 






goes past 


701E 




0021 








701E 


8A7000 


0022 


MOV 


7000h,A 


compare MSB stored to MSB 


7021 




0023 






sum 


7021 


4D0002 


0024 


CMP 


A,R2 




7024 


06** 


0025 


JNE 


ERROR 


set error bit if different 


7026 


8A7001 


0026 


MOV 


7001h,A 


compare LSB stored to 


7029 




0027 






LSB sum 


7029 


4D0003 


0028 


CMP 


A,R3 




702C 


02** 


0029 


JEQ 


EXIT 


set error bit if different 


702E 


74020F 


0030 ERROR OR 


#2, FLAG 


set bit 1 in the flag 


7031 




0031 






register 


7031 




0032 EXIT 


•EQU 


continue program here 



13-24 



Design Aids 



13.5.5 Binary-to-BCD Conversion 

This program converts a 16-bit binary word to a packed 6 nibble value. 



0000 




7000 


B5 


7001 


C5 


7002 


D502 


7004 


721005 


7007 


DF04 


7009 


DF03 


700B 


4EG202 


700E 




700E 


3E01 


7010 




7010 


lEOO 


7012 


DA05F2 


7015 




7015 


F9 



REGISTER BEFORE 



A 

B 

R2 
R3 
R4 
R5 

0001 

0002 BN2BCD 

0003 

0004 

0005 

0006 LOOP 

0007 

0008 

0009 

0010 

0011 

0012 

0013 

0014 

0015 



XX 
XX 
XX 

BINARY MSB 

BINARY LSB 

XX 

•TEXT 7000H 
CLR A 



CLR 
CLR 
MOV 
RLC 
RLC 
DAC 



B 

R2 

#16, R5 

R4 

R3 

R2,R2 



DAC R1,B 

DAC RO,A 

DJNZ R5,L00P 

RTS 



AFTER 
BCD MSB 

BCD 

BCD LSB 

ZERO 

ZERO 

ZERO 



absolute start address 
prepare answer registers 



move loop count to register 

shift higher binary bit out 

carry contains higher bit 

double the number then add 

the binary bit 

binary bit (a 1 in carry on 

the 1st time is 

doubled 16 times). 

do this 16 times, once for 

each bit 

back to calling routine 



13.5.6 BCD-To-Binary Conversion 

This routine converts a four digit number to binary. The maximum BCD num- 
ber is 9999 decimal. Operands originate and are stored in general purpose 
RAM. The BCD number is composed of the four digits D3, D2, D1, and DO 
contained in the bytes DH and DL. The binary number is calculated by divid- 
ing the number into powers of ten (Binary = D3*1000 + D2*100 + 01*10 + 
D0*1 ). Multiplying by 10 is easier if the number is further broken up in other 
numbers so that D2*10 = D2*(8+2) = D2*8+D2*2. Likewise, multiplying by 
1000 can be calculated by D3*(1000) = D3* (1024-24) = D3* (1024- 
(8+1 6)) = D3*1 024- (D3*8 + D3*1 6). This may seem complex but it works 
quickly and uses few bytes. 



Binary number MSB 
Binary number LSB 
Decimal number MSB 
Decimal number LSB 
DO=ones , Dl=tens, 
D2=hundreds, D3=thousands 
clear out binary MSB 
DO to BO 
convert DO 

D1*10=D1*8+D1*2 

isolate Dl 

B=D1*16 

B=D1 

A=D1*16/2=D1*8 

B=D1*2 

A=D1*10 (D1*8+D1*2) 

D1:D0 converted 

get upper two digits 
isolate D2 
R0:R1=D2*100 



0000 




0010 




-TEXT 


7000h 


0002 




0011 


BH 


.EQU 


R2 ; 


0003 




0012 


BL 


.EQU 


R3 ; 


0004 




0013 


DH 


.EQU 


R4 ; 


0005 




0014 


DL 


.EQU 


R5 ; 


7000 




0017 








700C 




0018 








700C 


D502 


0023 


TOP 


CLR 


BH ; 


700E 


420503 


0024 




MOV 


DL , BL 


7011 


730F03 


0025 




AND 


#OFh, BL ; 


7014 




0026 








7014 


1205 


0027 




MOV 


DL,A ; 


7016 


23F0 


0028 




AND 


#OFOh,A ; 


7018 


CO 


0029 




MOV 


A,B ; 


7019 


D701 


0030 




SWAP 


Rl ; 


701B 


BC 


0031 




RR 


A ; 


701C 


CE 


0032 




RL 


B ; 


701D 


68 


0033 




ADD 


B,A 


701E 


480003 


0034 




ADD 


RO , BL 


7021 




0035 








7021 


3204 


0036 




MOV 


DH , B ; 


7023 


530F 


0037 




AND 


#OFh,B ; 


7025 


5C64 


0038 




MPY 


#100, B ; 



13-25 



Design Aids 



7027 


,480103 


0039 


702A 


490002 


0040 


702D 




0041 


702D 


1204 


0042 


702F 


23F0 


0043 


7031 


CO 


0044 


7032 


CD 


0045 


7033 


68 


0046 


7034 


4A0003 


0047 


7037 


7B0002 


0048 


703A 


BO 


0049 


703B 


CD 


0050 


703C 


480102 


0051 


703F 




0052 



ADD 


R1,BL 


add to current total 


ADC 


R0,BH 


D2:D1:D0 converted 


MOV 


DH,A 


isolate D3 


AND 


#OFOh,A 


A=D3 * 16 


MOV 


A,B 


B=D3 * 16 


RRC 


B 


B=D3 * 8 


ADD 


B,A 


A=D3 * 24 


SUB 


RO,BL 


BH:BL=BH:BL-24*D3 


SBB 


#0,BH 




CLRC 




setup for rotate 


RRC 


B 


B=D3*4 


ADD 


R1,BH 


BH:BL=BH:BL+D3*4*256 



13.5.7 BCD String Addition 



The following subroutine uses the addition instruction to add two multi-digit 
numbers together. Each number is a packed BCD string, less than 256 bytes 
(512 digits), stored at memory locations STR1 and STR2. This routine adds 
the two strings together and places the result in STR2. The strings must be 
stored with the most significant byte in the lowest numbered register. The 
TMS370 family instruction set favors storing all numbers and addresses with 
the most significat byte in the lower numbered location. 



REGISTER 
A 
B 

R2 
STR1 
STR2 



BEFORE 

XX 

XX 

XX 
BINARY MSB 
BINARY LSB 



AFTER 

?? 



?? 

no change 

STR1 + STR2 



FUNCTION 

Accumulator 

Length of string 

Temporary save register 

BCD string 

Target string, 6 bytes max 



0000 
0000 
0000 
80E0 
80F0 
7000 
7000 
7001 
7002 
7005 
7007 
700A 
700B 
700D 
700E 
7011 
7013 



;Decimal Addition Subroutine. Stack must have 3 available bytes, 



;0n output: STR2 
0001 

0002 STRl 

0003 STR2 



BO 

FB 

AA80DF 

D002 

AA80EF 

FC 

1E02 

FB 

AB80EF 

CAEF 

FC 



STRl + STR2 
.TEXT 7000h 
.EQU 80E0h 
.EQU 80F0h 
0004 

0005 ADDBCD CLRC 

0006 PUSH ST 

0007 LOOP MOV 
MOV 



7014 F9 



0008 
0009 
0010 
0011 
0012 
0013 
0014 
0015 
0016 
0017 



MOV 

POP 

DAC 

PUSH 

MOV 

DJNZ 

POP 

RTS 



STRl-l(B) ,A 

A,R2 

STR2-1(B) ,A 

ST 

R2,A 

ST 

A,STR2-1(B) 

B,L00P 

ST 



absolute start address 

start of first string 

start of second string 

and result 

clear carry bit 

save status to stack 

load current byte 

save it in R2 

load next byte of STR2 

restore carry from last add 

add decimal bytes 

save the carry from this add 

; store result 
;loop until done 
;restore stack to starting 
;position 
;back to calling routine 



Notice the use of the Indexed Addressing mode to reference the bytes of the 
decimal strings. Also the need to push the status register between decimal 
additions, to save the decimal carry bit. Register B is used to keep count of the 
number of bytes that have been added. 



13-26 



Design Aids 



13.5.8 Fast Parity 



This routine presents a quick way to determine the parity of a byte, by exclu- 
sive ORing all the bits of the byte together, a single bit will be derived which 
is the even parity of the word. When exclusive ORing an even number of Is 
will combine to form a 0, leaving either an odd 1 or bit. This routine keeps 
splitting the byte in half and exclusive ORing the two halves. 



REGISTER 
A 
B 

CARRY 

************* 

* STEP 

* Byte 



BEFORE AFTER FUNCTION 

TARGET ?? Passing byte from program 

XX ?? Length of string 

XX Parity Status bit,result to calling routine 

********************************************************* 

1 SUBROUTINE 

bits 7654 3210 TO FIND 

XOR 7654 [MSN above] EVEN PARITY 



xxxx ABCD 



STEP 2 



STEP 3 



-> AB CD 

XOR AB [MS bits above] 



XX ab 



> a b 

XOR a [MS bit] 



************************************ 


0000 




0001 


.TEXT 


7000h 


7000 


CO 


0002 


PARITY MOV 


A,B 


7001 


B7 


0003 


SWAP 


A 


7002 




0004 






7002 


65 


0005 


XOR 


B,A 


7003 




0006 






7003 


CO 


0007 


MOV 


A,B 


7004 


BC 


0008 


RR 


A 


7005 




0009 






7005 


BC 


0010 


RR 


A 


7006 


65 


0011 


XOR 


B,A 


7007 


CO 


0012 


MOV 


A,B 


7008 


BC 


0013 


RR 


A 


7009 


65 


0014 


XOR 


B,A 


700A 


BC 


0015 


RR 


A 


700B 




0016 






700B 


F9 


0017 


RTS 




700C 




0018 






700C 




0019 






700C 




0020 







Is 



X P {answer} 



absolute start address 

duplicate the target byte 

line up the ms nibble with the 

nibble 

exclusive OR the nibbles to get a 

nibble answer 

duplicate the nibble answer 

line up bits 0,1 of the answers to 

bits 

2 , 3 of the answer 

XOR to get a new 2-bit answer 

duplicate this 2 bit answer 

line up bit with bit 1 

XOR to get final even parity answer 

rotate answer into the carry bit 

and bit 7 

carry = = even # of I's 

carry = 1 = odd # of I's 

use JC, JN or JNC in next executed 

instruction 



13.5.9 Bubble Sort 



This routine will sort up to 256 bytes using the bubble sort method. Longer 
tables could be sorted using the Indirect Addressing mode. 

REGISTER FUNCTION 

A Temporary Storage Register 

B Index into the Table 

R2 Holds flag to indicate a byte swap has been made 



0000 

2000 

0002 

7000 D502 

7002 52FF 

7004 AA2000 



0001 

0002 TABLE 

0003 FLAG 

0004 SORT 



.TEXT 7000h 
.EQU 2000h 



0005 



.EQU 

CLR 

MOV 



0006 LOOPl MOV 



R2 
FLAG 
#OFFh,B 
TABLE(B) ,A 



; absolute start address 

; start of data table in RAM 

; ' swap has been made' flag 

; reset swap flag 

;load table offset value 

;look: at entry in table 



13-27 



Design Aids 



7007 


ADIFFF 


0007 


CMP 


TABLE-l(B) ,A 


700A 


OB** 


0008 


JHS 


L00P2 


700C 




0009 






700C 


D302 


0010 


INC 


FLAG 


700E 




0011 






700E 


88 


0012 


PUSH 


A 


700F 


AAIFFF 


0013 


MOV 


TABLE-l(B) ,A 


7012 


AB2000 


0014 


MOV 


A,TABLE(B) 


7015 


B9 


0015 


POP 


A 


7016 


ABIFFF 


0016 


MOV 


A,TABLE-1(B) 


7019 


CAE9 


0017 


L00P2 


DJNZ B,L00P1 


701B 




0018 






701B 


76FF02E1 


0019 


BTJO #OFFh, FLAG, SORT 


701F 




0020 






701F 


F9 


0021 
0022 


RTS 





look at next lower byte 

if higher or equal, skip to 

next value 

entry is not lower, set swap 

flag 

store upper byte 

take lower byte 

put where upper was 

get the old upper byte 

put where the lower byte was 

loop until all the table is 

looked at 

if swap was made, then 

resweep table 

if no swap was made, then 

table is done 



13.5.10 Table Search 



Table searches are efficiently performed by using the CM PA (Compare Reg- 
ister A Extended) instruction. In the following example, a 150 byte table is 
searched for a match with a 6-byte string. 



REGISTER 
A 
B 

R2 
TABLE 
STRING 



BEFORE 
XX 
XX 
XX 
XX 
XX 



AFTER FUNCTION 



?? 

?? 

?? 
no change 
no change 



0000 
2000 
OOOA 
7000 
7000 
7003 
4005 
7007 
7008 
700A 
700D 
700F 
7012 
7014 
7014 
7016 
7016 
7016 



729602 

5206 

D602 

C2 

07** 

AA2000 

D602 

AD0009 

06EF 



0001 

0002 TABLE 

0003 STRING 
0004 

0005 SEARCH 

0006 LOOPl 

0007 L00P2 
0008 

0009 
0010 
0011 
0012 
0013 



.TEXT 7000h 
.EQU 2000 
.EQU RIO 



#150, R2 

#6,B 

R2 

B 
NOFIND 
MOV TABLE ( B ) , A 
XCHB R2 



MOV 

MOV 

XCHB 

DEC 

JNC 



Table Length 
Long string in table 
Target string, 6 bytes max 

absolute start address 

start of data table in RAM 

start of target string, 

6 bytes max 

table length = 150 bytes 

string length = 6 bytes 

swap pointers, long string in B 

reduce index into table 

table end? if so, no match found 

load test character 

swap pointers, string pointer in 



CMP STRING-1(B),A ;match? 

JNE LOOPl ;if not, reset string pointer 

;else test 

;next character 

; match found 

;no match found 



DJNZ 
.EQU 
.EQU 



B,L00P2 

$ 

$ 



CAEF 0014 

0015 MATCH 

0016 NOFIND- 
0017 

The Indexed Addressing mode is used in this example and has the capability 
to search a 256-byte string, if needed. Register B alternates between a pointer 
into the 6 byte test string and a pointer into the longer table string. 



13-28 



Design Aids 



13.5.11 16-by-16 (32-Bit) Multiplication 

This example multiplies the 16 bit value in register pair R2,R3 by the value in 
register pair R4,R5. The results are stored in R6,R7,R8,R9, and Register A and 



****** 

* 16 



B are altered. 

************************************************** 



■BIT MPY: 



X 



XH 
YH 



XL 
YL 



XLYLm 
XHYLm XHYLl 
XLYHm XLYHl 
+ XHYHm XHYHl 



XLYLl 



X VALUE 
Y VALUE 



1 = LSB 
m = MSB 



****** 

XH 

XL 

YH 

YL 

RSLT3 

RSLT2 

RSLTl 

RSLTO 

MPY32 



RSLT3 RSLT2 RSLTl RSLTO 
************************************************** 

.EQU R2 /higher operand of X 

.EQU R3 ; lower operand of X 

.EQU R4 ; higher operand of Y 

.EQU R5 ; lower operand of Y 

.EQU R6 ;MSB of the final result 
.EQU R7 
. EQU R8 

.EQU R9 ;LSB of the final result 



CLR 
CLR 
MPY 
MOV 
MOV 
MPY 
ADD 
ADC 
MPY 
ADD 
ADC 
ADC 
MPY 
ADD 
ADC 
RTS 



RSLT2 

RSLT3 

XL,YL 

B, RSLTO 

A, RSLTl 

XH,YL 

Rl, RSLTl 

R0,RSLT2 

XL,YH 

Rl, RSLTl 

R0,RSLT2 

#0,RSLT3 

XH,YH 

R1,RSLT2 

R0,RSLT3 



I clear the present value 

multiply LSB ' s 

store LSB in result register 

store MSB in result register 1 

get XHYL 

add to existing result XLYL 

add carry if present 

multiply to get XLYH 

add to existing result XLYL+XHYL 

add to existing results and carry 

add if carry present 

multiply MSB's 

add once again to the result register 

do the final add to the result reg 

return to call subroutine 



13.5.12 Keyboard Scan 



This routine reads a 16 key keyboard, returns the hex digit of the key and de- 
bounces the key to avoid noise. A 'valid key' flag is set when a new key is 
found. 



TMS370 



DO 
D1 
D2 
D3 
D4 
D5 
D6 
D7 



8 g 
C D 



KEYS 



Figure 13-12. Keyboard Scan Values 



13-29 



Design Aids 













AFTER AFTER 


REGISTER 


BEFORE 


NO KEY NEW KEY FUNCTION 




A 




XX 




COLUMN Temporary 




B 




XX 




ROW Temporary 




R2 




XX 




1 6 KEY # Temp store for Key value 




R3 




OLD KEY 


OFFh KEY # Holds key pressed now 




R4 


DEBOUNCED 





Debounce counter, old key 














or new 




R5 


GENERAL ?xxxxxxxO?xxxxxxx1 One bit of register is 1 








BITS 






if new key 


0000 




0001 




.TEXT 


07000h 




0002 




0002 


FLAG 


• EQU 


R2 


"swap has been made" flag 


002F 




0003 


DDIR 


.EQU 


P02F 


Port D data direction register 


002E 




0004 


DDATA 


.EQU 


P02E 


Port D data register 


7000 




0005 








THESE ASSIGNMENTS NEED TO BE 


7000 




0006 








DONE IN THE MAIN INITIALIZATION 


7000 




0007 










7000 


F7002E 


0008 


START 


MOV 


#00, DDATA 


clear these registers 


7003 


720005 


0009 




MOV 


#0,R5 


clear register that say key found 


7006 


F7F02F 


0010 




MOV 


#OFOh,DDIR 


set data direction register 4 


7009 




0011 








output , 


7009 




0012 








4 input 


7009 




0013 








THIS IS THE BEGINNING OF THE 


7009 




0014 








KEYBOARD SCAN ROUTINE 


7009 




0015 










7009 


5208 


0016 


GETKEY 


MOV 


#8,B 


initialize row pointer 


700B 


D502 


0017 




CLR 


R2 




700D 


CF 


0018 


LOOP 


RLC 


B 


select next row 


700E 


03** 


0019 


JC 


NOKEY 


last row? if so no key was found. 


7010 


780402 


0020 




ADD 


#4,R2 


add number of keys/row to key 


7013 




0021 








accumulator 


7013 


512E 


0022 




MOV 


B , DDATA 


activate row 


7015 


802E 


0023 




MOV 


DDATA , A 


read columns 


7017 


F7002E 


0024 




MOV 


#0, DDATA 


clear row 


701A 


230F 


0025 




AND 


#OFh,A 


isolate column data 


701C 


02EF 


0026 




JZ 


LOOP 


if no keys found then check next 


701E 




0027 








row 


701E 


D202 


0028 


KEYLSB 


DEC 


R2 


decrement column offset 


7020 


BD 


0029 




RRC 


A 


find column 


7021 


07FB 


0030 




JNC 


KEYLSB 


if not column then, try again 


7023 




0031 










7023 


4D0203 


0032 


NEWKEY 


CMP 


R2,R3 


is the new key the same as the old 


7026 




0033 








key 


7026 


02** 


0034 




JEQ 


DEBONS 


if it is then debounce it 


7028 


420203 


0035 




MOV 


R2 , R3 


brand new key, move it to current 


702B 




0036 








key value 


702B 


720704 


0037 




MOV 


#07, R4 


set up debounce count, debounce 7 


702E 




0038 








times 


702E 


7D0204 


0039 


DEBONS 


CMP 


#2,R4 


is the debounce count 1 or 0? 


7031 


09** 


0040 




JL 


GOODKY 




7033 


DA04D3 


0041 




DJNZ 


R4, GETKEY;. 


.f greater than 1 then debounce is 


7036 




0042 








not finished, go read key again 


7036 


770104** 


0043 


GOODKY 


BTJZ 


#01,R4,NONI 


:W;if debounce count = then key 


703A 




0044 








was here last time 


703A 


D204 


0045 




DEC 


R4 . 


if it was one this is a new valid 


703C 




0046 








key, make old key 


703C 




0047 










703C 


740105 


0048 




OR 


#1,R5 


set new key flag in BIT register. 


703F 




0049 








the 


703F 


F9 


0050 




RTS 




found new key so return to main 


7040 




0051 








calling routine uses this flag 


7040 


72FF03 


0052 


NOKEY 


MOV 


#0FFh,R3 


no key was found, set key value to 


7043 




0053 








unique 


7043 




0054 








value 


7043 


F9 


0055 


NONEW 


RTS 




if jumped to NONEW it is still the 


7044 




0056 








same key 


7044 




0057 








held down do nothing 



13-30 



Design Aids 



13.5.13 Divide 1 



The routine divides a 16-bit number by an 8-bit number to give a 16-bit 
quotient and an 8-bit remainder. The DIV instruction is used to accomplish 
this task. 



0000 




0021 




.TEXT 7000h 


700B 




0022 


OVERFLOW .EQU R7 


700B 




0023 






700B 




0024 






700B 




0025 






700B 




0026 






700B 




0027 






700B 


B5 


0028 


Divides 


CLR A 


700C 


F4F803 


0029 




DIV R3,A 


700F 


08** 


0030 




JV OVERF 


7011 


D004 


0031 




MOV A,R4 


7013 




0032 






7013 


62 


0033 




MOV B,A 


7014 


3202 


0034 




MOV R2,B 


7016 


F4F803 


0035 




DIV R3,A 


7019 




0036 






7019 


08** 


0037 




JV OVERF 


701B 


D005 


0038 




MOV A,R5 


701D 


F9 


0039 




RTS 


701E 




0040 






701E 


D311 


0041 


OVERF 


INC OVERFLC 


7020 


F9 


0042 




RTS 



divisor -R3, quotient LSB-R5 

dividend MSB-Rl, quotient MSB-R4 

dividend LSB-R2, remainder -B 
uses RO 

clear MSB of first dividend 

divide MSB of dividend to get MSB 

exit if overflow 

quotient. Move MSB of quotient 

to storage. 

move remainder to MSB of dividend 

move dividend LSB to LSB position 

divide to get quotient LSB and 

remainder 

exit if overflow 

store the quotient LSB next to MSB 

remainder in B 



13.5.14 Divide Instruction 2 



0000 
700B 
700B 
700B 
700B 
700B 
700B 
700B 
700B 
700B 
700B 
700B 
700E 
700E 
700F 
7010 
7012 
7014 
7015 
7016 
7018 
701A 
701C 
701D 
701D 
701F 
701F 
7021 
7021 
7023 
7025 



721006 

B5 

C5 

DF03 

DF02 

CF 

BF 

07** 

3A05 

1B04 

F8 

00** 

1D04 

07** 
06** 
3D05 



.TEXT 7000h 






Before 


Aft 


ar 


A = 


Remainder 


MSB 


B = 


Remainder 


LSB 


R2= Dividend MSB 


Quotient 


MSB 


R3= Dividend LSB 


Quotient 


LSB 


R4= Divisor MSB 


Divisor 


MSB 


R5= Divisor LSB 


Divisor 


LSB 


R6= XXX 


Zero 





This program divides a 16-bit dividend by a 16-bit divisor and produces a 
16-bit quotient with a 16-bit remainder. All numbers are unsigned positive 
numbers. All values can range from to FFFFh. The same principle can be 
applied to larger or smaller divide routines to allow different sizes of quotients, 
dividends, divisors, and remainders. 

0026 
0027 
0028 
0029 
0030 
0031 
0032 
0033 
0034 
0035 
0036 
0037 
0038 
0039 
0040 
0041 
0042 
0043 
0044 
0045 
0046 
0047 
0048 
0049 
0050 
0051 
0052 
0053 
0054 
0055 
0056 



DIV16 MOV #16, R6 

CLR A 
CLR B 
DIVLOP RLC R3 
RLC R2 
RLC B 
RLC A 
JNC SKI PI 
SUB R5,B 
SBB R4,A 
SETC 

JMP DIVEND 

SKIPl CMP R4,A 

JNC DIVEND 
JNE MSBNE 
CMP R5,B 



Set loop counter to 16, 
one for each quotient bit 

Initialize result register 
Multiply dividend by 2 

Shift dividend into A:B for 

comparison to divisor 

Check for possible error 

condition that results when 

a 1 is shifted past the MSB, 

Correct by subtracting divisor 

and setting carry. 

If MSb=l then subtract is 

possible 

Compare MSBs of dividend 

and divisor 

Jump if divisor is bigger 

If equal compare LSBs. 

Compare LSBs. 



13-31 



Design Aids 



7027 07** 
7029 3A05 
702B 1B04 
702D 
702D 



0057 JNC DIVEND ; Jump if divisor is bigger 

0058 MSBNE SUB R5,B ;If smaller, subtract divisor 

0059 SBB R4,A ;from dividend. Carry gets 

0060 ; folded into next rotate and 

0061 ;gets doubled each time. 



702D DA06E0 0062 DIVEND DJNZ R6,DIVL0P ;Next bit, is divide done? 



7030 DF03 
7032 DF02 
7034 



0063 
0064 
0065 



RLC 
RLC 



R3 
R2 



;Finish last rotate. 



13-32 



*ii^ti^aotJii! 



|TM§^|0/F^mHy|Di^ 



CPU and Memory Organization 



System and Digital I/O Confipiration 



Interrupts and System Reset 



££PROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module Mi* 



Analog-To^Olgital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specificattons 



Customer Infonnatlon 



Appendixes 



14. Development Support 



Texas Instruments provides extensive development support for the TMS370 
family. The TMS370 series unified development support tools consists of the 
following components: 

• Assembly Language Tools 

• Extended Development Support (XDS-^ ) System with associated soft- 
ware 

• EEPROM Programmer 

• TMS370C810 and TMS370C850 Devices (for prototyping) 

These development tools are designed to work with an IBM, IBM compatible 
or Tl PC. The TMS370 system designer can use a text editor to generate the 
assembler source code, then use the assembly language tools to assemble the 
source modules and link the assembled modules. The object file may then be 
tested with either the XDS System or a TMS370C8xO device, both which 
provide full speed in-circuit emulation. The XDS and debugger software 
provides realtime breakpoint/trace/timing functions to facilitate hardware and 
software integration during system development. 

The EEPROM Programmer provides the means of programming the device 
used for prototyping and emulation. The TMS370C8xO devices can be used 
for prototyping and emulation of masked ROM parts, as well as a medium for 
submitting the program to Tl for masked ROM production. 

This section discusses key features of the TMS370 development tools. For a 
detailed desciption of system components, refer to the documents listed in 
Section 1 .5 on page 1 -8. The topics included in this section are as follows: 



Section Page 

14.1 The Assembly Language Tools 14-2 

14.1.1 The Assembler 14-3 

14.1.2 The Linker 14-3 

14.1.3 The Archiver 14-5 

14.1.4 Code Conversion Utility 14-5 

14.2 The XDS System 14-6 

14.2.1 XDS System Configuration Requirements 14-6 

14.2.2 The Debugger Function 14-8 

14.2.3 Breakpoint/Trace/Timing Functions 14-11 

14.2.4 XDS System Operating Considerations 14-16 

14.3 TheTI EEPROM Programmer 14-17 

14.4 Prototyping/Preproduction Devices 14-19 



3 XDS is a registered trademark of Texas Instruments Incorporated. 



14-1 



Development Support - Assembly Language Tools 



14.1 The Assembly Language Tools 

The TMS370 assembly language tools (Figure 14-1) include an assembler, 
linker, archiver, and a code conversion utility. These tools are available from 
Tl on a 5 1 /4 inch floppy diskette for IBM, IBM compatible and Tl PC's. The 
PC should be running PC-DOS or MS-DOS version 2.1 or later, and have at 
least 51 2K bytes of memory space available for the assembler and linker op- 
eration. 



Macro 

Source 

Files 




Archiver 



Macro 
Library 



•> Assembler 



COFF 

Object 

Files 



Code 

Conversion 

Utility 

T 



Llnl<er 



w//// /// /// ^ 





COFF 

Object 

Files 




Executable 
COFF Object 
File 




Archiver 



Library of 

Object 

Files 



EPROM 
Programmer 



' ^//// / ///// /m^//////////A 



TMS370 



XDS Emulator 

with 

Debugger 



Absolute 
Lister 



Figure 14-1. Software Development Flow 



14-2 



Development Support - Assembly Language Tools 



14.1.1 The Assembler 

The TMS370 assembler translates assembly language source files into ma- 
chine language object files. Source files can contain instructions, assembler 
directives, and macro directives. The assembler directives control various as- 
pects of the assembly process, such as the source listing format, symbol defi- 
nition, conditional assembly blocks, macro library definition, and how the 
machine code is placed into the TMS370 memory space. 

The assembler is a one-pass assembler. The format of the object files created 
by the assembler and linker is called Common Object File Format (COFF). 
COFF encourages and facilitates modular programming. It allows the assem- 
bler to maintain a section program counter (SPC) for each section of object 
code generated. The SPC defines the virtual program memory addresses as- 
signed to the associated object code. The assembler uses the SPC while it 
builds the symbol table. 

The symbol tables contained in the COFF object files allow the XDS debugger 
to provide the user with symbolic debugging. The XDS also provides for 
direct referencing of any assembler label and arithmetic expressions involving 
assembler labels when the labels are part of the downloaded COFF object file. 
The COFF object files are also used by the Tl EEPROM programmer to form a 
PC memory image of the data loaded for programming. 

14.1.2 The Linker 

The TMS370 linker creates executable modules by combining COFF object 
files. The concept of user definable COFF sections is basic to the linker oper- 
ation. The linker accepts several types of files as input : 

• Relocatable COFF object files produced by the TMS370 assembler 

• Command files 

• Archive object libraries 

• Output modules created by a previous linker run (these are referred to 
as partially linked files) 

As the linker combines object files, it performs the following tasks: 

• Allocates sections into the target system's configured memory 

• Relocates symbols and sections to assign them to final addresses 

• Resolves undefined external references between input files 

The linker supports a C-like command language that controls memory con- 
figuration, section definition, and address binding. The language supports 
expression assignment and evaluation, and provides two powerful directives, 
MEMORY and SECTIONS, that allow you to: 

• Define a memory model that conforms to target system memory 



14-3 



Development Support - Assembly Language Tools 



Combine object file sections 

Allocate sections into specific areas of memory 

Define overlayed memory structures 

Define or redefine global symbols at link time 

igure 14-2 shows the operation of the linker on two source code files. Each 
file has been assembled and contains four default sections and one named 
section. The various sections are arranged in the order dictated either by the 
linker's default method or by a user supplied control file. The executable ob- 
ject module shows the combined sections, and the memory map indicates the 
location of the sections in memory. 



flletob) 



Executable 
Object Module 



.reg 



:bss;: 



litext? 



WMm 



(named section) 



flle2.obj 



.reg 



'Siim;] 



mm 



Wmm 



(named section) 







m 

m 



flle1 
(.reg) 



flle2 
(.reg) 



:(^t)ss) 



(;tj$s); 



;:;(>^^xt);;; 



mmm 



mmmm 

iiiiii 

iiiiiii 
[datal 



■1 



Tables 





Memory Map 


02h 


Programmable 

registers 

(.reg) 


100h 


Space for 

Variables 

(.bss) 


2000h 
3000h 


Executable 
Code 
(.text) 


7000h 


l^li:iiifrKiiillsiO:i? 




irtlt 




Tables 



Figure 14-2. Linker Output Generation 



14-4 



Development Support - Assembly Language Tools 



14.1.3 The Archiver 

The archiver provides file management by allowing a group of files to be col- 
lected into a single library. For example, macros can be collected by the ar- 
chiver, then fetched by the assembler as directed by the source file. Object 
modules can also be collected into a library for convenient access by the linker. 
While not necessary for program development, the archiver can provide valu- 
able organization in the building of the executable COFF object file. 



14.1.4 Code Conversion Utility 

The code conversion utility converts COFF object files to the Intel hex object 
format. Code conversion is necessary when not using the Tl EEPROM Pro- 
grammer, since most other (non-TI) EPROM programmers do not accept 
COFF object files as input. Code in the Intel hex object format can be down- 
loaded to most EPROM programmers. 



14-5 



Development Support - XDS System 



14.2 The XDS System 



The XDS System is a self contained package that provides full-speed, in-cir- 
cuit emulation and debugging functions required for program development of 
the TMS370 family devices. Key features of the XDS emulation function in- 
clude: 

20 MHz full-speed in-circuit emulation of all TMS370 family members 

Realtime hardware breakpoint/trace/time analysis capibilities 

Execution of programs from internal XDS memory (64K) or target me- 
mory 

Support of both microcomputer and microprocessor modes 

Large trace buffer, 2048 samples 

Full logic tracing with logic analyzer interface cable 

he XDS System hardware includes a chassis, power supply, power and in- 
terfacing cables, and a three board set consisting of an emulator, communi- 
cations board, and a breakpoint/trace/timing board. At the heart of the XDS 
system is a special system emulator chip containing all the peripheral modules 
and I/O line circuits that precisely duplicate the TMS370's logic and per- 
formance. The internal XDS memory can be used to emulate on-chip ROM 
and/or external memory. 

The XDS debugger function is provided by software which runs on a PC. The 
software provides interactive control of the emulator with the following fea- 
tures: 

Window oriented user interface with menu-driven command structure 

Direct symbolic referencing from downloaded assembly symbol tables 

Full symbolic expression analysis that recognizes all assembly language 
operators 

Symbolic reverse assembler 

Ability to display and change registers and memory 



14-6 



Development Support - XDS System 



14.2.1 XDS System Configuration Requirements 

A functional XDS System configuration consists of the XDS System and the 
following user-supplied components: 

• IBM, IBM compatible or Tl PC with 51 2K bytes minimum and serial 
communication port 

• MS/PC-DOS version 2.1 or later 

• Monitor (preferably color, to better highlight field and value changes) 




TARGET 
SYSTEM 

Figure 14-3. Typical XDS System Configuration 



14-7 



Development Support - XDS System 



14.2.2 The Debugger Function 



The XDS debugger function is provided by software that runs on a PC. This 
program provides window oriented, interactive programming that facilitates 
the development of applications for TMS370 family devices. The user devel- 
ops an executable COFF object file using a text editor and the TMS370 as- 
sembly language tools. The debugger function allows the object file to be 
downloaded into the target device or the emulator memory of the XDS Sys- 
tem. The debugger and emulator functions then provide evaulation of 
microprocessor/program operation. 

A user debugging a system needs to focus on a number of different areas such 
as the code being executed, the registers of the target machine, and the vari- 
ables in the program. The debugger aids this by using a menu-oriented com- 
mand language that allows control of the debugging process. The command 
language is designed to be both simple for the inexperienced user and efficient 
for the expert. This is accomplished by limiting command menus to just one 
or two levels, so that nearly everything in the debugger can be controlled by 
a simple two-letter command without wasting keystrokes. Commands re- 
quiring additional input or qualification provide a prompt for that information 
or a menu of subcommands. 

he top level screen (Figure 14-4) of the debugger consists of the following 
elements: 

Available command menu 

Status line 

information windows 

Function key reminder line 



14-8 



Development Support - XDS System 



Debug 1 0i splay ^cute 0Gg0efn^oint @va[ 



Bonfig||r/Time|lDad NQjuleRtltR 
HALTED; POINT 







— code 








START: 










PC 7002 


SP 01 


ST cnzv21 


1 7000 52E0 


MOV 


EO,B 




A 00 


B EO 


40 010000 


7009 en 


LDSP 






r f i 1 


^ 


—1 -f-irif 


BEGIN; 


1 u 






R2 00 


" R3 00 


SP (01) EO 


7003 88702F5D 


MOVW 


702F,R93 




R4 00 


R5 00 


- 1(00) 00 


7007 720F5F 


MOV 


F,R95 




R6 00 


R7 00 


- 2(FF) 00 


oloopi 










R8 00 


R9 00 


- 3(FE) 00 


2 700A 8800085B 


MOVW 


0008, R91 




RIO 00 


R11 00 


- 4(FD) 00 


700E 


8E701C 


CALL 


@XFER 




R12 00 


R13 00 


- 5(FC) 00 


7011 


7A485D 


SUB 


48,R93 




R14 00 


R15 00 


- 5(FB) 00 






— disp 


1 ^.. 




R15 00 


R17 00 


- 7(FA) 00 








7000 


52 EO FD 88 70 2F 5D 72 


R.,.p/Jr 


R18 00 


R19 00 


- 8(F9) 00 


7008 


OF 5F 88 00 08 5B 8E 70 


._,,,[,p 


R20 00 


R21 00 


- 9(F8) 00 


7010 


1C 7A 48 5D 7B 00 5C DA 
5F FO 00 E7 72 50 5E 9A 


,zH](,\, 
,,,rP\ 






/ U 1 u 

7018 


system :nt[ 


regO 10000000b 


7020 


5D 9B 5B 70 01 5D 70 01 


J.EpJp, 


system :nt[ 


regl 00000000b 


7028 


5B DA 5E 


F3 F9 F9 FA 20 


[,^,,,, 


system cntl 


reg2 00001000b 


7030 


20 20 20 20 20 20 20 20 




interrupt a 


cntl 00000000b 


7038 


20 20 20 20 20 20 20 20 




interrupt b 


cntl 00000000b 


7040 


20 20 20 20 20 20 20 20 




interrupt c 


cntl 00000000b 


70^8 


20 20 20 20 20 20 20 20 




timer A counter 


0001 8h 



Inspect 



ISUpdateliE^iE 



^P 



Figure 14-4. XDS Debugger Top Level Screen 



The available command menu displays the single keystroke commands that 
can be used from that menu. Pressing the indicated key either performs the 
associated action or calls up a prompt or menu of subcommands. The status 
line indicates the current status of the system. The function key reminder line 
displays several functions provided by the function [F] keys. 

The following paragraphs describe the information windows, which take up 
the area under the status line and above the function key reminder line. Some 
windows are based on virtual buffers in the XDS System, which means that 
the debugger keeps track of more information than can be displayed at one 
time. To view all of the information, the user simply scrolls through the win- 
dow. The debugger automatically accesses the emulator whenever scrolling 
passes beyond the buffer's current contents. The user can easily move from 
window to window to make specific changes and view data. Information 
displayed in the windows is updated automatically whenever the microcon- 
troller stops running, and manually with a function key. Updates or new val- 
ues are highlighted for easy recognition. 



14-9 



Development Support - XDS System 



14.2.2.1 Code Window 



The code window (located in the upper left corner) displays disassembled 
object code being debugged. The current instruction at the PC is identified 
with a highlighted address. Also, instructions at which simple breakpoints 
have been set are marked with a numeric "breakpoint ID" to the left of the 
address. Immediate values in instructions are displayed in hexidecimal. 

This window can be scrolled downward, and simple breakpoints can be added 
or removed. Upward scrolling is possible only up to the top of the virtual 
buffer, since backward disassembly is impossible. 

14.2.2.2 Display Window 

he display window is located in the lower left corner of the window area, 
his window displays miscellaneous debugger information such as: 

Memory, dumped in hexadecimal format 
Peripheral file register contents 
Symbols in the symbol table 

Object module names (with current module highlighted) 
PC text file with available control keys for "find" functions 
'his window can be scrolled up and down. 

14.2.2.3 CPU Registers Window 

The contents of five registers (A, B, PC, SP, and ST) are displayed in the CPU 
registers window in the upper right corner. The contents of these registers can 
be modified from this window. Scrolling is not needed since all available in- 
formation is shown. 

14.2.2.4 Register File Window 

The register file window (located to the right of center) shows the contents 
of the register file, 20 registers at a time. The data can be scrolled up or down, 
and changed at will. 



14-10 



Development Support - XDS System 



14.2.2.5 Stack Window 



The stack window, located to the far right of center, dislays the contents of the 
current program stack within the register file. The stack window differs from 
the regsiter file window in that a) when updated, the window automatically 
changes the display to reflect the offset of each register from the current top 
of stack and b) the registers are displayed in reverse order, so that "higher" 
on the stack corresponds to "higher" in the window. 



14.2.2.6 Expression Window 



The expression window (located in the lower right corner) is used to display 
aribitrary expressions specified by the user. When prompted by the debugger 
for an address or a value, an arbitrary complex expression may be entered. The 
debugger evaluates expressions using the symbol table and the emulator. 
Expressions can consist of numeric constants, symbols, and register names, 
seperated by operators. All expressions are evaluated displayed as a 16-bit 
value in both hexadecimal and decimal. For example, if the expression "PC 
+ 23h" is entered and the current value in the PC is 7000h, the debugger 
displays "PC+23h = 07023h = 28707". The debugger then prompts for a 
"save" upon which the expression is displayed in the window. 



14.2.3 Breakpoint/Trace/Timing Functions 

The Breakpoint, Trace and Timing (BTT) board of the XDS System monitors 
various microcontroller activities at the hardware level. The board can be 
programmed to take certain actions triggered by the occurence of specified 
qualifiers, depending on what state the board is in. The BTT is always in one 
of four states (Figure 1 4-5). Up to four actions can be qualified per state, with 
certain restrictions. A qualified event in one state can cause a transition to 
another state with a new set of parameters and actions becoming affective. 
This allows multilevel or sequenced breakpoints to be used for complex de- 
bugging problems. 

The occurance of specified qualifiers results in an action taken by the BTT 
board. These qualifiers consist of the following: 

ADDRESS The BTT monitors the memory bus during all memory cycles. 
Two address qualifiers can be used to trigger an action on a 
particular address or range of addresses. These can be used to 
define two distinct single point addresses, an inclusive range 
(any address within the range qualifiers), or an exclusive range 
(any address outside the range qualifiers). A mask can be 
specified to selectively ignore some or all of the external qual- 
ifier bits. 

DATA The BTT also monitors the value on the data bus during each 

memory cycle. Two data qualifiers can be used with the data 
bus in exactly the same way as the two address qualifiers are 
used with the address bus. A mask can be specified to selec- 
tively ignore some or all of the external qualifier bits. 



14-11 



Development Support - XDS System 



CYCLE Memory cycle types can be specified to qualify to trigger an 

action. Memory cycle types are read, write, and instruction 
fetch. Any one or any combination of these cycles can be 
qualified. 

EXTERNAL The BTT can monitor the logic level of the eight external probe 
lines. A qualifier can be used to trigger an action on a partic- 
ular value from these inputs. A mask can be specified to se- 
lectively ignore some or all of the external qualifier bits. 

Actions that can be taken by the BTT board on the basis of the above qualifiers 
consist of the following: 



BP/EVENT 



TRACE 



JUMP 



POINT TIMER 



RANGE TIMER 



Triggering a breakpoint/event may cause either a hardware 
breakpoint, decrement the state counter or transfer control 
to the next (or beginning) state. 

A cycle which satisfies the TRACE qualifiers will be stored 
in the TRACE buffer. This provides a history of the pro- 
gram execution for later inspection. 

The BTT has four separate states in which different sets of 
actions can be specified. The JUMP action forces a tran- 
sition into a different state when triggered. 

The BTT has two timers that can be started or stopped by 
qualified actions. The POINT TIMER action uses the two 
address qualifiers to control one timer. The timer is started 
when the first address is qualified and stopped when the 
other address is qualified. 

The RANGE TIMER actions also control the BTT timers but 
differ from the point timer action in that one action starts 
a timer and a separate action stops it. Thus, there are ac- 
tually two actions, "range timer start" and "range timer 
stop." 



14-12 



Development Support - XDS System 



START 



STATE 

ACTION OA t 
ACTION OB BP' 
ACTION ON 



STATE 1 



ACTION 1A 
ACTION IB BP 



ACTION 2A 
ACTION 2B BP 



LOOP 
COUNT 



3 

END 

STATE 



TRACE 
DELAY COUNT 



MAX 
TRACE 



TIME OUT 
TIMER 



^ BP-BREAKPOINT/EVENT 



Figure 14-5. BIT Operation 



ACTION 3A 
ACTION SB BP 




TIMER 1 



TIMER 2 



TRACE 
BUFFER 



14-13 



Development Support - XDS System 



Bill gesetgoad^veQxitf^ort 
STATE 



ACT 1 1 



Trace 



addr = START 

,. BEGIN 

mask OFFFFh 

cycles lAQ 

extern IGNORE 



•aval lable- 



BP/event 

Trace 

Jump 

PointTimer 

RangerTimer 



lEdi 



ast 



ACT I 



BP/event 



addr = xLoop 
cycles lAQ 
extern IGNORE 



ACTION; RangeTimer 

start # 1 

addr = START 
cycles ALL 
extern IGNORE 



ACTION; RangeTimer 
stop # 1 

addr = BEGIN 
cycles ALL 
extern IGNORE 



■locals- 



mode; ADDR ONLY 
trace mode; TRIX 
event count; 100 



iNextStatJaoca 



lohal 



globals 

delay count; 100 

max trace; 

end state; 

loop count; 1 

time out; 0008.000 000 000 



elp 



Figure 14-6. BTT Screen 



The trace sample function of the BTT board provides "snapshot" storage of 
bus cycle activity. Up to 2047 samples, each 104 bits wide, can be stored by 
the circular trace buffer. As more samples are stored, the buffer wraps around, 
replacing the oldest samples with the newest ones. Each sample contains the 
following information: 

Address and data bus values 



Bus-cycle access type (read, write, instruction fetch) 

External logic-probe values 

BTT state and breakpoint/event indicators 

Time stamp from free-running timer (hours though nanoseconds) 

he trace buffer screen provides a chronological display of the trace samples, 
igure 1 4-7 shows the screen display for the trace functions. 



14-14 



Development Support - XDS System 



Inspect Trace; |33sition B:p l^^ttomj 
Sample = 909, Total = 2047: 



Dokup ^ve iflners 3]rmatTime ^cute 



INDX ST 


h IT, s. ms vs ns EXTERNAI_ 


lYCI.r. 


AUUk 


!JA!A 


R[VrRSh ASI^^^ 


0909 


0;00rD0,417 084 600 1111 




mwt 


UU5U 


57 




0910 


0;00i00,417 084 800 1111 




lAQ 


7014 


7B 


SBB 


0911 


0:00i00.417 085 000 1111 




READ 


7015 


00 




0912 


0i00;00.417 085 200 1111 




READ 


7016 


5C 




0913 


0:00;00.417 085 300 1111 




READ 


005C 


70 




0914 


0i00i00,417 085 400 1111 




WRITE 


005C 


70 




0915 


0;00i00,417 085 600 1111 




lAQ 


7017 


DA 


DJNZ R95 


0915 


0:00:00,417 085 800 1111 




READ 


7018 


5F 




0917 


0:00:00,417 085 900 1111 




READ 


005F 


OB 




0918 


0:00:00,417 086 000 1111 




WRITE 


005F 


OA 




0919 


0:00:00,417 086 200 1111 




READ 


7019 


FO 




0920 E 


0:00:00,417 086 600 1111 




lAQ 


700A 


88 


MOVW 


0921 


0:00:00,417 086 800 1111 




READ 


700B 


00 




0922 


0:00:00,417 087 000 1111 




READ 


700C 


08 




0923 


0:00:00,417 087 300 1111 




READ 


700D 


5B 




0924 


0:00:00,417 087 500 1111 




WRITE 


005B 


08 




0925 


0:00:00,417 087 700 1111 




WRITE 


005A 


00 






timer 1; 0:00:00,409 97 


3 80( 


D 


timer 


2: 0:00:00,000 000 000 1 


t 


mer 1 avg: 0:00:00,000 39 


9 50( 


} 









Figure 14-7. Trace Sample Screen 



The BTT board has three timers. Two timers are controlled by event quali- 
fication, while the third is free running. The timers allow timing statistics to 
be taken, such as the time the microcontroller spends executing a particular 
routine. This aids the programmer in developing efficient code and evaluating 
system performance. The display format of the trace buffer screen can be al- 
tered by the user to show one of the following statistics determined by the 
timers: 

• Time stamps referenced from starting time 

• Delta or time between trace samples 

• Time samples referenced from selected trace sample 



14-15 



Development Support - XDS System 



14.2.4 XDS System Operating Considerations 

The emulation hardware of the XDS System generally exhibits the same char- 
acteristics as the actual TMS370 devices. There are, however, a few subtle 
differences that the designer should be aware of when building a prototype 
circuit for use with the XDS System. 

14.2.4.1 Mode Control Pin 

To allow the XDS System to function without being attached to a target sys- 
tem, a 20K ohm pull down resistor should be connected to the mode control 
line in the XDS unit. This increases the minimum input current needed to drive 
this line high (l|) from 100 uA to 300 uA. If a pull up resister is used to put 
the device in the microcomputer mode, then it's value should be no greater 
than 1 K ohm when using the XDS System. 



14.2.4.2 Reset 



The XDS System adds an analog switch and a 51 K ohm pull up resister to the 
reset line. This increases the current necessary to pull this line to a logic low 
from 10 uA to 100 uA. 



14.2.4.3 Clock In 



The XDS System cannot drive a crystal located on the target system. There- 
fore, either the crystal must be moved to socket Y1 of the emulator board, or 
a TTL level external clock be connected. 



14-16 



Development Support - EEPROM Programmer 



14.3 The Tl EEPROM Programmer 

The Tl EEPROM Programmer is an interactive, menu driven system that pro- 
vides a method of programming TMS370 prototyping devices and industry- 
standard UVEPROMs. The Programmer can interact either directly with a PC 
or through the XDS for easy programming, modifying, and reading of the tar- 
get memory device. Sockets are provided for all members of the TMS370 fa- 
mily as well as UVEPROMs such as the 2732, 2764, 27128, and 27256. 

The Tl EEPROM Programmer system (as shown in Figure 14-8) consists of 
the Tl EEPROM Programmer and an IBM compatible or Tl PC running EEP- 
ROM programmer software under MS/PC-DOS. The Tl EEPROM Program- 
mer comes complete with power and interface cables, EEPROM programmer 
software for the PC, and a user guide. 




EEPROM/UVEPROM PROGRAMMER 



Figure 14-8. Typical EEPROM/UVEPROM Programmer Configuration 



14-17 



Development Support - EEPROM Programmer 



he programmer software provides both interactive and limited batch control 
with the following features: 

Window oriented screens with a menu-driven command structure 

Block erase for TMS370 family devices only 

Programming mode bit selection for TMS370 family devices only 

Relocatable programming capability which allows source data bytes 
within certain address range to be programmed at specified address 

Reverse assembly code display 

Intermediate PC memory which provides a storage area for downloading 
a COFF file or uploading from devices 

Ability to inspect and patch loaded data in PC memory 

Ability to generate a COFF file from PC memory content 

Ability to save or load Programmer Configuration to or from 
Configuration/Batch file 

he Tl EEPROM Programmer, unlike most other EPROM programmers, can 
use COFF object files developed by the assembler/linker as input for pro- 
gramming the TMS370 devices. Other EPROM programmers will require that 
the object files be converted into the Intel hex object format before program- 
ming. 



14-18 



Development Support - Prototyping/Preproduction Devices 



14.4 Prototyping/Preproduction Devices 

The TMS370C850 and TMS370C810 devices can be used as prototyping 
devices for the Ti\/IS370C050 and TMS370C010 devices respectively. The 
TI\/IS370C8xO devices replace the mask ROM with 4 kilobytes of EEPROM. 
These devices are assembled in the same package types as the masked ROM 
parts so they can plug into the same target application as the final masked 
device. The TMS370C850 and TMS370C810 provide form factor preprod- 
uction parts with zero leadtime for field testing and production qualifications, 
thereby reducing the overall time to market. Both TMS370C8xO devices can 
be programmed directly from the assembler or linker output file with the Tl 
EEPROM Programmer. 



14-19 



Development Support - Prototyping/Preproduction Devices 



14-20 



Introduction 



TMS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface ISCU Port 



Serial Feripheral Interface (SPI) Module BC 



Analog*To-Digltal Converter Module 



Assembly Languas^ Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Infomnation MIS. 



Appendixes 



15. Electrical Specifications 

This section contains electrical and timing information for the TMS370 family 
devices. Specifications that apply to the TMS370Cx10 devices are presented 
first, followed by specifications that apply to the TMS370Cx50 devices. 
Specifications for the TMS370Cx10 devices generally apply also to the 
TMS370Cx50 devices, since a TMS370Cx50 device essentially consists of a 
related TMS370Cx10 plus additional circuitry. 

Section Page 

15.1 TMS370Cx10 Specifications 15-2 

15.2 TMS370Cx50 Specifications 15-10 



Caution: 

Stresses beyond those listed under "Absolute Maximum Rat- 
ings" may cause permanent damage to the device. This is a 
stress rating only and functional operation of the device at 
these or any other conditions beyond those indicated in the 
"Recommended Operating Conditions" section of this specifi- 
cation is not implied. Exposure to absolute maximum rated 
conditions for extended periods may affect device reliability. 



15-1 



Electrical Specifications - TMS370Cx10 Devices 



15.1 TMS370Cx10 Specifications 

The specifications given in the following tables apply to the TMS370C010 
andTMS370C810. 

Table 15-1. Absolute Maximum Ratings over Operating Free-Air 
Temperature Range (unless otherwise noted) 

Supply voltage range, Vcc^ -0.3 V to 7 V 

Input voltage range: All pins except MC -0.3 V to Vcc+0.3V 

Input voltage range: MC -0.3 V to 14 V 

Input buffer current ±10 mA 

Maximum source current, Ice 170 mA 

Maximum drain current, Iss 170 mA 

Continuous power dissipation 1 W 

Storage temperature range -65X to 150°C 



t Unless otherwise noted, all voltages are with respect to Vss- 



Table 15-2. Recommended Operating Conditions 





MIN NOM MAX 


UNIT 


vcc 


Supply voltage (see Note 1) 




4.5 


5 5.5 


v 


vqc 


RAM data retention supply voltage 




3 


5.5 


V 


V|L 


Low-level input voltage 


All pins except MC and XTAL2/CLKIN 


Vss 


0.8 


v 


MC.normal operation 


Vss 


0.3 


V 


XTAL2/CLK1N 


Vss 


0.8 


V 


V|H 


High-level input voltage 


All pins except MC and XTAL2/CLKIN 


2 


Vcc 


V 


MC/Write Protect Override (WPG) 


11.7 


12 


V 


XTAL2/CLKIN 


0.8VCC 


Vcc 


V 


RESET 


O.TVCC 


Vcc 


V 


ta 


Operating free-air temperature 


A version 


-40 


85 


'C 


L version 





70 


'C 



NOTES: 1 . All voltage values are with respect to Vss- 

2. RESET is externally released while Vcc '^ within the recommended operating range of 4.5 V-5.5 V and externall y activa ted when 
Vcc<'*.5 V or Vcc>5-5 V. RAM data retention is valid throughout the 2 MHz-20 MHz frequency range. An active RESET initializes 
(clears) RAM locations OOOOh and 0001 h. 



15-2 



Electrical Specifications - TMS370Cx10 Devices 



Table 15-3. Electrical Characteristics over Full Range of Operating Conditions 



PARAMETER 


TEST CONDITIONS 


MIN TYP MAX 


UNIT 


Vol Low-level output voltage 


Iql = 1.4 mA 


0.4 


V 


Vqh High-level output voltage 


lOH = -50 M.A 


0.9VCC 


V 


lOH = -2 mA 


2.4 


V 


l| Input current 


MC 


OVsV|S 12V 


400 


VA 


I/O pins 


V s V| s Vcc 


±10 


(^ 


Iql Low-level output current 


Vol = 0.4 V 


1.4 


mA 


'oh High-level output current 


VoH = 0.9VCC 


-50 


^A 


VoH = 2.4 V 


-2 


mA 


Supply current 
. (Operating mode) 
^^ Osc Power bit = 

(see Note 3) 


TMS370C010 


Operating, Notes 1 and 2 
CLKIN frequency = 20 MHz 


48 


mA 


TMS370C810 


80 


TMS370C010 


Operating, Notes 1 and 2 
CLKIN frequency = 12 MHz 


33 


TMS370C810 


55.6 


TMS370C010 


Operating, Notes 1 and 2 
CLKIN frequency = 2 MHz 


14 


TMS370C810 


25 


Supply current 
. (Standby mode) 
^^ Osc Power bit = 

(see Note 4) 


TMS370C010 


Standby, Notes 1 and 2 
CLKIN frequency = 20 MHz 


20.8 


mA 


TMS370C810 


28 


TMS370C010 


Standby, Notes 1 and 2 
CLKIN frequency = 12 MHz ns 


13.6 


TMS370C810 


18.2 


TMS370C010 


Standby, Notes 1 and 2 
CLKIN frequency = 2 MHz 


4.6 


TMS370C810 


6 


Supply current 
(Standby mode) 
^^ Osc Power bit = 1 
(See Note 5) 


TMS370C010 


Standby, Notes 1 and 2 
CLKIN frequency = 12 MHz 


10.8 


mA 


Standby, Notes 1 and 2 
CLKIN frequency= 20 MHz 


3.8 


, Supply current 
CC (Halt mode) 


TSM370C010 


Halt mode, Note 2 
XTAL2/CLKIN < 0.2 V 


50 


nA 


TMS370C810 


100 



NOTES: 1 . Single chip mode, ports conf gured as inputs, or outputs with no load. All inputs s 0.2 V or s Vcc ■ 

2. All ports configured as inputs, or outputs with no load. All inputs s 0.2 V or a Vcc ~ 0-2 V. 

3. Maximum operating current for TMS370C010 = 1 .9(fx) -i- 10.2 mA. 
Maximum operating current for TMS370C810 = 3.06(fx) -i- 18.9 mA. 

4. Maximum standby current for TMS370C010 = 0.9(fx) -I- 2.8 mA. 
Maximum standby current for TMS370C810 = 1.2(fx) + 3.56 mA. 

5. Maximum standby current for TMS370C01 = 0.7(fx) -i- 2.4 mA. 



15-3 



Electrical Specifications - TMS370Cx10 Devices 



XTAL2/CLKIN 



XTAL1 



CI* 



u 



^ CRYSTAL/ ^ 

CERAMIC RESONATOR^ 



XTAL2/CLKIN 



XTAL1 



C2^ 



EXTERNAL 
CLOCK SIGNAL 



NO CONNECTION 



The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. 

The values of CI and C2 should be the values recommended by the crystal/ceramic resonator manufacturer. 



Figure 15-1. Recommended Crystal/Clock Connections 



LOAD VOLTAGE 



1.2 kU 



Vo 



20 pF 



CASE 1: Vo = VoH = 2.4 V; LOAD VOLTAGE = V 
CASE 2: Vo = Vql = 0.4 V; LOAD VOLTAGE = 2.1 V 

Figure 15-2. Output Loading Circuit for Test 



15-4 



Electrical Specifications - TMS370Cx10 Devices 



J 



•=i^ O.SVcc V (HIGH) 

0.8 V (LOW) 



Figure 15-3. XTAL2/CLKIN Measurement Points 



J"^ 



=ra(j 2 V (HIGH) 

0.8 V (LOW) 



Figure 15-4. General Measurement Points 



15-5 



Electrical Specifications - TMS370Cx10 Devices 



Table 15-4. External Clocking Requirements 



NO. 




MIN NOM MAX 


UNIT 


1 


<w(CI) XTAL2/CLK1N pulse duration (Note 1) 


20 


ns 


2 


V(CI) )aAL2/CLKIN rise time 


30 


ns 


3 


tf(ci) XTAL2/CLKIN fall time 


30 


ns 


4 


td(CIH-COL) Delay time. XTAL2/CLKIN rise to CLKOUT fall 


100 


ns 




fx Crystal operating frequency 


2 20 


MHz 



T For V|L and V|h, refer to "Recommended Operating Conditions". 

NOTE 1 . This pulse may be either a high pulse, as illustrated, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN 
cycle, or a low pulse, which extends from the earliest valid low to the f nal valid low in an XTAtJ2/CLKIN cycle. 



XTAL2/CLKIN 



V^^^^^^^^"A_y^^W^ 



I ! 



Figure 15-5. External Clock Timing 



Table 15-5. General Purpose Output Switching Time Requirements 





MIN NOM MAX 


UNIT 


tr Rise time 


INT2, INT3, SPISOMI. SPISIMO, SPICLK, T1IC/CR, T1PWM, T1EVT, T2IC1/ 
CR, T2IC2/PWM, T2EVT. SCITXD, SCIRXD, SCICLK 


45 


ns 


tf Fall time 


INT2, INT3, SPISOMI, SPISIMO, SPICLK, T1IC/CR, T1PWM,T1EVT, T2IC1/ 
CR, T2IC2/PWM, T2EVT, SCITXD, SCIRXD, SCICLK 


45 


ns 



— =r I I ic — 



I I 
! I I 



Figure 15-6. Switching Time Measurement Points 



15-6 



Electrical Specifications - TMS370Cx10 Devices 



Table 15-6. Recommended EEPROM Timing Requirements For Programming 





MIN NOM MAX 


UNIT 


'w(PGM)B Programming signal pulse duration to insure valid data is stored (byte mode) 


10 


ms 


*w(PGM)AR Programming signal pulse duration to insure valid data is stored (array mode) 


20 


ms 



15-7 



Electrical Specifications - TMS370Cx10 Devices 



Table 15-7. SPI Master External Timing Characteristics 



NO. 


PARAMETER 


MIN 


MAX 


UNIT 


38 


*c{SPC) 


SPICLK cycle time 


2tc 


256tc 


ns 


39 


<w{SPCL) 


SPICLK low pulse duration 


tc-45 


128tc 


ns 


40 


'w(SPCH) 


SPICLK high pulse duration 


tc-45 


128tc 


ns 


41 


<d(SPCL-SIMOV) 


Delay time, SPISIMO valid after SPICLK low (Polarity = 1) 


-50 


50 


ns 


42 


»v(SPCH-SIMO) 


SPISIMO data valid after SPICLK high (Polarity = 1) 


<w(SPCH)-50 


ns 



Table 15-8. SPI Master External Timing Requirements 



NO. 




MIN MAX 


UNIT 


43 


'su(SOMI-SPCH) SPISOMI setup time to SPICLK high (Polarity = 1) 


.25tc+150 


ns 


44 


'v(SPCH-SOIMI) SPISOMI data valid after SPICLK high (Polarity = 1) 





ns 



NOTE 1 . tc = system clock cycle time = 4/fx. 






38- 



SPICLK 



\ 



I h- 39 -J 

I ' 



if 



•40- 



\ 



r- — «H-4,i 



■42 ■ 



SPISIMO 



SPISOMI 



DATA VALID 



^43^ 

m m 



1—44 



DATA VALID 




NOTE 1 2. The diagram above is for Polarity = 1 . SPICLK is inverted from above diagram when Polarity = 0. 



Figure 15-7. SPI Master External Timing 



15-8 



Electrical Specifications - TMS370Cx10 Devices 



Table 15-9. SPI Slave External Timing Characteristics 



NO. 


PARAMETER 


MIN 


MAX 


UNIT 


48 


td(SPCL-SOMIV)S 


Delay time, SPISOMI valid after SPICLK low (Polarity = 1) 


3.25tc+100 


ns 


49 


*v(SPCH-SOMI)S 


SPISOMI data valid after SPICLK high (Polarity = 1) 


'w(SPCH)S 


ns 



Table 15-10. SPI Slave External Timing Requirements 



NO. 




MIN MAX 


UNIT 


45 


tc(SPC)S 


SPICLK cycle time 


etc 


ns 


46 


'w(SPCL)S 


SPICLK low pulse duration 


4tc-45 


ns 


47 


<w(SPCH)S 


SPICLK high pulse duration 


4tc-45 


ns 


50 


*su(SIMO-SPCH)S 


SPISIMO setup time to SPICLK high (Polarity = 1) 





ns 


51 


tv(SPCH-SIMO)S 


SPISIMO data valid after SPICLK high (Polarity = 1) 


3tc+100 


ns 



NOTE 1. tc = system clock cycle time = 4/fx. 



SPICLK 



SPISOMI 



SPISIMO 




NOTE 12. The diagram above is for Polarity- 1. SPICLK is inverted from above diagram when Polarity =0. 
NOTE 13. As a slave, the SPICLK pin is used as the input for the serial clock, which is supplied from the 
network master. 



Figure 15-8. SPI Slave External Timing 



15-9 



Electrical Specifications - TMS370Cx50 Devices 



15.2 TMS370Cx50 Specifications 

The specifications given in the following tables apply to the devices in the 
TMS370Cx50 catagory. 

Table 15-11. Absolute Maximum Ratings over Operating Free-Air 
Temperature Range (unless otherwise noted) 

Supply voltage range, Vqc^ -0.3 V to 7 V 

Supply voltage range for digital I/O, Vcc2^ ■0-3 V to 7 V 

Supply voltage range for analog, Vqcs' "0-3 V to 7 V 

Reference voltage range, Vref {non-Vcc3 

reference for A/D) Vss3-0.1 V to Vcc3+0.1 V 

Input voltage range: All pins except MC -0.3 V to Vcc"'"0.3V 

Input voltage range: MC -0.3 V to 14 V 

Input buffer current ±10 mA 

Maximum source current. Ice 170 mA 

Maximum drain current, Iss 170 mA 

Continuous power dissipation 1 W 

Storage temperature range -65°C to 150°C 



t Unless otherwise noted, all voltages are with respect to Vss- 



Table 15-12. Recommended Operating Conditions 





MIN 


NOM 


MAX 


UNIT 


VCC1 


Digital logic supply voltage (Note 1) 




4.5 


5 


5.5 


V 


Vqci 


RAM data retention supply voltage 




3 




5.5 


V 


VCC2 


Digital I/O supply voltage (Note 1) 




4.5 


5 


5.5 


V 


VCC3 


Analog supply voltage (Note 1) 




4.5 


5 


5.5 


V 


V|L 


Low-level input voltage 


All pins except MC and XTAL2/CLKIN 


Vss 




0.8 


V 


MC 


Vss 




0.3 


V 


XTAL2/CLKIN 


Vss 




0.8 


V 


V|H 


High-level input voltage 


All pins except MC and XTAL2/CLKIN 


2 




vcc 


V 


MC 


Vcc-0.3 




vcc 


V 


XTAL2/CLKIN 


0.8VCC 




Vcc 


V 


RESET 


O.TVcc 




Vcc 


V 


MC (mode control) voltage (Note 2) 


EEPROM write protect override 


11.7 


12 




V 


Microprocessor 


Vcc-0-3 


V 


Microcomputer 


Vcc-0-3 


V 


Ta 


Operating free-air temperature 


A version 


-40 




85 


•c 


L version 







70 


•c 



NOTES: 1 . All voltage values are with respect to Vss- 

2. The hardware protect ovcerride, microprocessor, or microcomputer mode can be selected only while RESET is high (active). 

3. RESET is externally released while Vcc 's within the recommended operating range of 4.5 V-5.5 V and externally activated when 
Vcc<4.5 V or Vcc>5.5 V. RAM data retention is valid throughout the 2 MHz-20 MHz frequency range. An active RESET initializes 
(clears) RAM locations OOOOh and 0001 h. 



15-10 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-13. Electrical Characteristics over Full Range of Operating Conditions 



PARAMETER 


TEST CONDITIONS 


MIN TYP MAX 


UNIT 


y Low-level output volt- 
O"- age 


Ports A, B, C, and 
D, and RESET 


Iql = 2 mA 


0.4 


V 


Other outputs 


'OL = 1-^ "^A 


0.4 


V 


Vqh High-level output voltage 


Iqh = -50 nA 


0.9VCC 


V 


l0H= -2 mA 


2.4 


V 


l| Input current 


MC 


OVsVi s 12V 


400 


vJ^ 


I/O pins 


V s V| S Vcc 


±10 


mA 


, Low/-level output cur- 
'OL rent 


Ports A, B, C, and 
D, and RESET 


Vol = 0-4 V 


2 


mA 


Other outputs 


Vol = 0.4 V 


1.4 


mA 


'oh High-level output current 


Vqh = 0.9VCC 


-50 


VA 


VoH = 2.4 V 


-2 


mA 


Supply current 
. (Operating mode) 
^C Osc Power bit = 

(see Note 4) 


TMS370C050 


Operating, Notes 1 and 3 
CLKIN frequency = 20 MHz 


67 


mA 


TMS370C850 


80 


TMS370C050 


Operating, Notes 1 and 2 
CLKIN frequency = 12 MHz 


46.2 


TMS370C850 


55.6 


TMS370C050 


Operating, Notes 1 and 3 
CLKIN frequency = 2 MHz 


20 


TMS370C850 


25 


Supply current 
. (Standby mode) 
^^ Osc Power bit = 

(see Note 5) 


TMS370C050 


Standby, Notes 2 and 3 
CLKIN frequency = 20 MHz 


20.8 


mA 


TMS370C850 


28 


TMS370C050 


Standby, Notes 2 and 3 
CLKIN frequency = 12 MHz 


13.6 


TMS370C850 


18.2 


TMS370C050 


Standby, Notes 2 and 3 
CLKIN frequency = 2 MHz 


4.6 


TMS370C850 


6 


Supply current 
. (Standby mode) 
^^ Osc Power bit = 1 

(See Note 6) 


TMS370C050 


Standby, Notes 2 and 3 
CLKIN frequency = 12 MHz 


10.8 


mA 


Standby, Notes 2 and 3 
CLKIN frequency = 2 MHz 


3.8 


, Supply current 
CC (Halt mode) 


TSM370C050 


Halt mode. Note 2 
XTAL2/CLKIN < 0.2 V 


50 


HA 


TMS370C850 


100 



NOTES: 1 . Single chip mode, ports configured as inputs, or outputs with no load. All inputs s 0.2 V or a Vcc - 0-2 V. 

2. All ports configured as inputs, or outputs with no load. All inputs s 0.2 V or 2: Vcc - 0.2 V. 

3. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 1 ns. Currents may 
be higher with a crystal oscillator. At 20 MHz this extra current = 0.1 mA x (total load capacitance + crystal capacitance in pF). 

4. Maximum operating current for TMS370C050 = 2.6(fx) + 1 5 mA. 
Maximum operating current for TMS370C850 = 3.06(fx) + 18.9 mA. 

5. Maximum standby current for TMS370C050 = 0.9(fx) + 2.8 mA. 
Maximum standby current for TMS370C850 = 1 .2(fx) + 3.56 mA. 

6. Maximum standby current for TMS370C050 = 0.7(fx) -I- 2.4 mA. (Osc Power bit valid only from 2 MHz to 1 2 MHz.) 



15-11 



Electrical Specifications - TMS370Cx50 Devices 



XTAL2/CLKIIM 



XTAL1 



CI* 



^D^ 



^ CRYSTAL/ '^ 

CERAMIC RESONATOR* 



XTAL2/CLKIN 



C2^ 



EXTERNAL 
CLOCK SIGNAL 



XTAL1 



NO CONNECTION 



Figure 15-9. Recommended Crystal/Clock Connections 



LOAD VOLTAGE 



1.2 kfi 



Vo 



20 pF 



CASE 1: Vq = Vqh = 2.4 V; LOAD VOLTAGE = V 

CASE 2: Vo = Vql = 0.4 V; LOAD VOLTAGE = 2.8 V FOR PORTS A, B, C, and D, and RESET 

LOAD VOLTAGE = 2.1 V FOR OTHER OUTPUTS 



Figure 15-10. Output Loading Circuit for Test 



15-12 



Electrical Specifications - TMS370Cx50 Devices 



.y^iz 



^=^ O.SVcc V (HIGH) 

0.8 V (LOW) 



Figure 15-11. XTAL2/CLKIN Measurement Points 



2 V (HIGH) 

0.8 V (LOW) 



Figure 15-12. General Measurement Points 



15-13 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-14. External Clocking Requirements 



NO. 




MIN NOM MAX 


UNIT 


1 


*w(CI) 


XTAL2/CLKIN pulse duration (Note 1) 


20 


ns 


2 


»r(CI) 


XTAL2/CLKIN rise time 


30 


ns 


3 


»f(CI) 


XTAL2/CLKIN fall time 


30 


ns 


4 


k](CIH-COL) 


Delay time, XTAL2/CLKIN rise to CLKOUT fall 


100 


ns 




fx 


Crystal operating frequency 


2 


20 


MHz 



' For V|L and V|n, refer to "Recommended Operating Conditions". 

NOTE 1 . This pulse may be either a high pulse, as illustrated, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN 
cycle, or a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle. 



XTAL2/CLKIN 



A \ / K A 

II I I t- 



t^^t- 4 



CLKOUT 



/ 



Figure 15-13. External Clock Timing 



Table 15-15. Peripheral Module and General Purpose Output Switching Times 





MIN NOM MAX 


UNIT 


\f Rise time 


INT2, INT3, SPISOMI, SPISIMO, SPICLK, T1IC/CR, T1PWM, T1EVT, T2IC1/ 
CR, T2IC2/PWM. T2EVT, SCITXD, SCIRXD, SCICLK 


45 


ns 


tf Fall time 


INT2, INT3, SPISOMI, SPISIMO, SPICLK, T1IC/CR, T1 PWM, T1EVT, T2IC1/ 
CR, T2IC2/PWM, T2EVT, SCITXD, SCIRXD, SCICLK 


45 


ns 



^fv 



I I 
] I I 



Figure 15-14. Switching Time Measurement Points 



15-14 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-16. Recommended EEPROM Timing Requirements For Programming 





MIN NOM MAX 


UNIT 


•w(PGM)B Programming signal pulse duration to insure valid data is stored (byte mode) 


10 


ms 


'w(PGM)AR Programming signal pulse duration to insure valid data is stored (array mode) 


20 


ms 



Table 15-17. Switching Characteristics and Timing Requirements 



NO. 




MIN MAX 


UNIT 


5 


tc CLKOUT (system clock) cycle time 


200 2000 


ns 


6 


'w(COL) CLKOUT low pulse duration 


0.5tc-20 0.5tc 


ns 


7 


'w(COH) CLKOUT high pulse duration 


0.5tc 0.5tc+20 


ns 


8 


tcj(coL-A) Delay time, CLKOUT low to address, R/W, and OCF valid 


0.25tc+40 


ns 


9 


fv(A) Address valid to EDS, CSE1, CSE2, CSH1, CSH2, CSH3, and CSPF low 


0.5tc-50 


ns 


10 


•su(D) Write data setup time to EDS high 


0.75tc-40f 


ns 


11 


, Address, R/W, and OCF hold time from EDS, CSE1 , CSE2, CSH1 , CSH2, 
»h(EH-A) CSH3, and CSPF high 


0.5tc-40 


ns 


12 


'h(EH-D)W Write data hold time from EDS high 


0.75tc+15 


ns 


13 


*d(DZ-EL) Delay time, data bus high Impedance to EDS low (read cycle) 


0.25tc-30 


ns 


14 


•d(EH-D) Delay time, EDS high to data bus enable (read cycle) 


1.25tc-40 


ns 


15 


'd(EL-DV) Delay time, EDS low to read data valid 


tc-65f 


ns 


16 


'h(EH-D)R Read data hold time from IDS high 





ns 


17 


*su(WT-COH) WAIT setup time to CLKOUT high 


0.25tc+75* 


ns 


18 


'h(COH-WD WAIT hold time from CLKOUT high 





ns 


19 


*d(EL-WTV) Delay time, EDS low to WAIT valid 


0.5tc-70 


ns 


20 


tyy Pulse duration; EDS. CSE1 , CSE2, CSH1 , CSH2, CSH3, and CSPF low 


tc-40'f tc+40'l' 


ns 


21 


'd(AV-DV)R Delay time, address valid to read data valid 


1.5tc-75''' 


ns 


22 


kJ(AV-WTV) Delay time, address valid to WAIT valid 


tc-85 


ns 


23 


'd(AV-EH) Delay time, address valid to EDS high (end of write) 


1.5tc-40f 


ns 



' If wait states, PFWait, or the Auto-Wait feature are used, add t^ to this value for each wait state invoked. 

* If the Auto-Wait feature is enabled, the WAIT input may assume a "Don't Care' condition until the third cycle of the access. 

NOTE 1 . tc = system clock cycle time = 4/fx. 



15-15 



Electrical Specifications - TMS370Cx50 Devices 



EDS, CSE1. CSE 2, CSH1 , 
CSH2. CSH3, CSPF 



I I 



X 



-T 21 



°ATA "°p°?;,^^^ I )i(~ I READ DATA D^ 



19 -A 

17-f 



"1 I 



if 



! I- 



/■ READ DATA X 
\ VALID J 



!¥ 



^^ 



^~~\ 



READ DATA 



X 



DISABLE f\ DATA 



1^ 



w 



Figure 15-15. External Read Timing 



15-16 



Electrical Specifications - TMS370Cx50 Devices 



EDS. CSE1. CSE2, CSH1 
CSH2. CSH3, CSPF 




Figure 15-16. External Write Timing 



15-17 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-18. SPI Master External Timing Characteristics 



NO. 


PARAMETER 


MIN 


MAX 


UNIT 


38 


<c{SPC) 


SPICLK cycle time 


2tc 


256tc 


ns 


39 


tw(SPCL) 


SPICLK low pulse duration 


tc-45 


128tc 


ns 


40 


tw(SPCH) 


SPICLK high pulse duration 


tc-45 


128tc 


ns 


41 


td(SPCL-SIMOV) 


Delay time, SPISIMO valid atter SPICLK low (Polarity = 1) 


-50 


50 


ns 


42 


<v(SPCH-SIMO) 


SPISIMO data valid after SPICLK high (Polarity = 1 ) 


'w(SPCH)-50 


ns 



Table 15-19. SPI Master External Timing Requirements 



NO. 




MIN MAX 


UNIT 


43 


*su(SOMI-SPCH) SPISOMI setup time to SPICLK high (Polarity = 1) 


.25tc+150 


ns 


44 


'v(SPCH-SOMl) SPISOMI data valid after SPICLK high (Polarity = 1) 





ns 



NOTE 1 . tc = system clock cycle time = 4/fx. 






38- 



SPICLK 



\ 



I h- 39 -J 

I 1 



■A 



I 1 

p- — *t-4i r 



■40- 



■ 42. 



\ 



SPISIMO 



SPISOMI 



DATA VALID 



r^-^n 



a_44 



I DATA VALID I 




NOTE 15. The diagram above is for Polarity = 1. SPICLK is inverted from above diagram when Polarity = 0. 



Figure 15-17. SPI Master External Timing 



15-18 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-20. SPI Slave External Timing Characteristics 



NO. 


PARAMETER 


MIN 


MAX 


UNIT 


48 


td(SPCL-SOMIV)S 


Delay time, SPISOMI valid after SPICLK low (Polarity = 1 ) 


3.25tc + 100 


ns 


49 


tv(SPCH-SOMI)S 


SPISOMI data valid after SPICLK higti (Polarity = 1 ) 


<w(SPCH)S 


ns 



Table 15-21. SPI Slave External Timing Requirements 



NO. 




MIN MAX 


UNIT 


45 


<c(SPC)S 


SPICLK cycle time 


8tc 


ns 


46 


*w(SPCUS 


SPICLK low pulse duration 


4tc-45 


ns 


47 


*w(SPCH)S 


SPICLK high pulse duration 


4tc-45 


ns 


50 


tsu(Slf^O-SPCH)S 


SPISIMO setup time to SPICLK high (Polarity = 1) 





ns 


51 


tv(SPCH-SIMO)S 


SPISIMO data valid after SPICLK high (Polarity = 1) 


3tc+100 


ns 



NOTE 1. \q = system clock cycle time = 4/fx. 



SPICLK 



SPISOMI 



SPISIMO 




NOTE 15. The diagram above is for Polarity=1 . SPICLK is inverted from above diagram when Polarity = 0. 
NOTE 16. As a slave, the SPICLK pin is used as the input for the serial clock, which is supplied from the 

network master. 

Figure 15-18. SPI Slave External Timing 



15-19 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-22. SCI Isosynchronous Mode Timing Charateristics For Internal Clock 



NO. 


PARAMETER 


MIN 


MAX 


UNIT 


24 


tc(SCC) 


SCICLK cycle time 


2tc 


131,072tc 


ns 


25 


»w(SCCL) 


SCICLK low pulse duration 


tc-45 


65,536tc 


ns 


26 


<w(SCCH) 


SCICLK high pulse duration 


tc-45 


65,536tc 


ns 


27 


td(SCCL-TXDV) 


Delay time, SCITXD valid after SCICLK low 


-50 


50 


ns 


28 


V(SCCH-TXD) 


SCITXD data valid after SCICLK high 


'w(SCCH)-50 


ns 



Table 15-23. SCI isosynchronous Mode Timing Requirements For Internal Clock 



NO. 




MIN 


MAX 


UNIT 


29 


<su(RXD-SCCH) 


SCIRXD setup time to SCICLK high 


0.25tc+145 


ns 


30 


W(SCCH-RXD) 


SCIRXD data valid after SCICLK high 





ns 



NOTE 1 . tc = system clock cycle time = 4/fx. 



SCICLK 



SCITXD 



SCIRXD 




Figure 15-19. SCI Isosynchronous Mode Timing For Internal Clock 



15-20 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-24, SCI Isosynchronous Mode Timing Charateristics For External Clock 



NO. 


PARAMETER 


MIN 


MAX 


UNIT 


34 


td(SCCL-TXDV) 


Delay time, SCITXD valid after SCICLK low 


4.25tc+145 


ns 


35 


'v(SCCH-TXD) 


SCITXD data valid after SCICLK high 


»w(SCCH) 


ns 



Table 15-25. SCI Isosynchronous Mode Timing Requirements For External Clock 



NO. 




MIN MAX 


UNIT 


31 


'c(SCC) 


SCICLK cycle time 


lOtc 


ns 


32 


»w(SCCL) 


SCICLK low pulse duration 


4.25tc+120 


ns 


33 


tw(SCCH) 


SCICLK high pulse duration 


tc+120 


ns 


36 


tsu(RXD-SCCH) 


SCIRXD setup time to SCICLK high 


40 


ns 


37 


tv(SCCH-RXD) 


SCIRXD data valid after SCICLK high 


2tc 


ns 



NOTE 1 . tc = system clock cycle time = 4/fx 



SCICLK 



SCITXD 



SCIRXD 




Figure 15-20. SCI Isosynchronous Mode Timing For External Clock 



15-21 



Electrical Specifications - TMS370Cx50 Devices 



Table 15-26. A/D Converter Recommended Operating Conditions 





MIN 


NOM 


MAX 


UNIT 


VCC3 


Analog supply voltage 


4.5 


5 


5.5 


V 


VcC-0-3 




VcC + 0.3 


V 


VSS3 


Analog ground 


Vss-0.3 




Vss+0.3 


V 


Vref 


Non-Vcc3 reference (Note 1) 


2.5 


VCC3 


VCC3+0-1 


V 


Analog input for conversion 


VSS3 




Vref 


V 



NOTE 1. Vref TiList be stable, within ±1/2 LSB of the required resolution, during the entire conversion time. 



Table 15-27. A/D Converter Operating Characteristics Over Full Range Of 

Operating Conditions 



PARAMETER 


TEST CONDITIONS 


MIN TYP MAX 


UNIT 


' Absolute accuracy (Note 1) 


VcC3 = 5.5 V, Vref = 5.1 V 


±1 


LSB 


Differential/integral linearity error (Note 2) 


2.5 V < Vref < 5.8 V 


±0.5 


LSB 


'CC3 


Analog supply current 


Converting 


2 


mA 


Not converting 


5 


HA 


l| 


Input current, AN0-AN7 


0VsV|S5.5V 


2 


HA 


Vref iiput charge current 




1 


mA 


Zref 


input impedance of Vref 


XTAL2/CLKINS 12 MHz 


24 


kn 


12 MH2<XTAL2/CLKINs20 MHz 


10 


kn 


Conversion time (excluding sample time) 




164tc 


ns 



NOTES: 1 . Absolute resolution = 20 mV. At Vref = 5. 1 V, this is 1 LSB. As Vref decreases, LSB size decreases and thus absolute error in terms of 
LSBs increases. 
2. Excluding quantization error of 1/2 LSB. 



Table 15-28. Analog Timing Requirements 





MIN 


NOM 


MAX 


UNIT 


'su(S) 


Analog input setup to sample command 





ns 


»h(AN) 


Analog input hold from start of conversion 


18fc 


ns 


'w(S) 


Duration of sample time per kilohm of source impedance (Note 1 ) 


1 


(iS/kn 



N0TE1. 



The value given is valid for a signal with a source impedance greater than 1 kfl. If the source impedance is less than 1 kfl, use a 
minimum sampling time of 1 jis. 



15-22 



Electrical Specifications - TMS370Cx50 Devices 















1 


■"i 


ANALOG 
IN 


MM 

1 






' )mm 




1 

p-tsu(S) 
1 , 




1 
1 
1 


SAMPLE 
START 


y 

1 




A 




r 


^ h(Ai\J) 

1 


CONVERT 
START 


f" ^w(S) 


r 


A 



Figure 15-21. Analog Timing 



15-23 



Electrical Specifications - TMS370Cx50 Devices 



15-24 



Introduction 



TMS370 Family Devicos 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts and System Beset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface ISCII Port 



Serial Peripheral Interface (SPI) Module mR 



Analog>To-Digitat Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Speciflteiations 



Customer Information 



Appendixes 



16. Customer Information 



This section includes general information on mask-ROM prototyping, 
TMS370 physical characteristics, and parts ordering. Topics covered in this 
section include: 

Section Page 

16.1 Mask ROM Prototype and Production Flow 16-2 

16.2 Mechanical Package Information 16-5 

16.3 TMS370 Family Numbering and Symbol Conventions 16-9 

16.3.1 Device Prefix Designators 16-9 

16.3.2 Device Numbering Convention 16-10 

16.3.3 Device Symbols 16-10 

16.4 Development Support Tools Ordering Information 16-13 

16.4.1 TMS370 Macro Assembler, Linker, and Utilities 16-13 

16.4.2 TMS370 EEPROM Programmer 16-13 

1 6.4.3 TMS370 XDS System 1 6-1 3 

1 6.4.4 Complete TMS370 Development System 1 6-13 



16-1 



Customer Information - Mask ROM Prototype and Production Flow 



16.1 Mask ROM Prototype and Production Flow 

The TMS370 family includes two mask-ROM microcontrollers; the 
TMS370C010 and the TMS370C050. The ROM is manufactured containing 
customer's application code. The custom-programmed nature of these de- 
vices requires a standard, defined interface between the customer and the 
factory during production. Figure 16-1 shows this standard of 
prototype/production flow for customer ROM receipt. 



CUSTOMER SUBMITS 
ROM CODE 



CUSTOMER suBMrrs 

MICROCOMPUTER SPEC 

(If REQUIRED) 



CUSTOMER SUBMITS 
NCRF 



Tl PERFORMS 
ROM RECEIPT 




YES 



Tl ORDERS MASKS, 

MANUFACTURES,AND 

SHIPS 25 PROTOTYPES 




YES 



CUSTOMER RELEASE 
TO PRODUCTION 



Tl SHIPS 
PRODUCTION DEVICES 



Figure 16-1. Prototype and Production Flow 



16-2 



Customer Information - Mask ROM Prototype and Production Flow 

1) Customer Required Information 

For Tl to accept the receipt of a customer ROM algorithm, each of the 
following three items must be received by the Tl factory: 

a) The customer completes and submits a New Code Release Form 
(NCRF - available from Tl Field Sales Office) describing the cus- 
tom features of the device (e.g., customer information, prototype 
and production quantities and dates, any exceptions to standard 
electrical specifications, customer part numbers and symbols, 
package type, etc.). 

b) If non-standard specifications are requested on the NCRF then the 
customer submits a copy of the discription of the microcomputer, 
including the functional description and electrical specification 
(including absolute maximum ratings, recommended operating 
conditions, and timing values). Tl will then respond to the re- 
quested specification changes. 

c) When the customer has completed code development and has 
verified the code with the development system, the object file is 
submitted in Intel hex object format to the Tl factory using an ac- 
ceptable transfer media. Acceptable media include the following: 

• Modem transfer: PC-to-PC via Xmodem, Ymodem, or Zmo- 
dem protocol or Microstuf's Crosstalk XVI protocol. 

• MS-DOS formatted 5 1/4" floppy disk compatible with IBM 
orTI PC 

• EPROM devices (currently supported: TMS2764, 
TMS27C64, TMS27128, TMS27C128). 

• TMS370C8xO EEPROM devices. 

The completed NCRF, customer specification (if required), and ROM 
code should be given to the local representive or sent to the nearest Field 
Sales Office. 

2) Tl Performs ROM Receipt 

Code review and ROM receipt is performed on the customer's code and 
a unique manufacturing ROM code number (such as R150x123FN) is 
assigned to the customer's algorithm. All future correspondence should 
indicate this number. The ROM receipt procedure reads the ROM code 
information, processes it, reproduces the customer's ROM object code 
on the media requested on the NCRF, and returns the processed and the 
original code to the customer for verification of correct ROM receipt. 
(Note: The customer must provide the EPROM/EEPROM device if that 
type of media has been requested on the NCRF). All TMS370 mask 
ROM devices contain ROM space that is reserved for Tl use only. The 
contents of this reserved space is changed when Tl processes the mask 
ROM with the customer's object code. Therefore, the customer should 
not use locations 7FE0h through 7FEBh in their algorithm or checksum 
routine. 

3) Customer ROM Receipt Approval 

16-3 



Customer Information - Mask ROM Prototype and Production Flow 

The customer then verifies that the ROM code received and processed 
by Tl is correct and that no information was misinterpreted in the trans- 
fer. The customer must then return an algorithm approval form (available 
from the field sales office) for correct ROM receipt verification or re- 
submit the code for processing. This written confirmation of verification 
constitutes the contractual agreement for creation of the custom mask 
and manufacture of ROM verification prototype units. 

4) Tl Orders Masks, Manufacturing, and Ships 25 Prototypes 

Tl generates the prototype photomasks, processes, manufactures, and 
tests 25 microcomputer prototypes containing the customer's ROM 
pattern for shipment to the customer for ROM code verification. These 
microcomputer devices have been made using the custom mask but are 
for the purposes of ROM verification only. Prototype devices are sym- 
bolized with a P preceding the manufacturing ROM code number (eg., 
PR150x123FN) to differentiate them from production devices. 

5) Customer Prototype Approval 

The customer verifies the operation of these prototypes in the system 
and responds with written customer prototype approval or disapproval. 
This written customer prototype approval constitutes the contractual 
agreement to initiate volume microcomputer production using the veri- 
fied prototype ROM code. 

6) Customer Release to Production 

With customer algorithm approval, the ROM code is released to pro- 
duction and Tl will begin shipment of production devices according to 
customer's final specification and order requirements. 

Two lead times are quoted in reference to the preceding flow: 

• Prototype lead time - elapsed time from the receipt of written ROM re- 
ceipt verification to the delivery of 25 prototype devices. 

• Production lead time - elapsed time from the receipt of written customer 
prototype approval to delivery of production devices. 

For the latest TMS370 family lead times, contact the nearest Tl field sales of- 
fice. 



Note: All TMS370 family devices contain mask ROM space reserved for 
Tl use only. This space includes locations 7FE0h through 7FEBh. This 
reserved area should therefore not be used in the customer's software al- 
gorithm, nor should it be used during mask ROM/firmware development. 
The reserve location contents are changed by Tl. 



16-4 



Customer Information - Mechanical Package Information 



16.2 Mechanical Package Information 

The TMS370 microcomputer family devices are assembled in two package 
types according to the type of material and outline used for the package. These 
package types are: 

• Plastic dual-inline package (DIP) 

• Plastic leaded chip carrier (PLCC) 

Package types are designated in the device symbol by the suffix on the cus- 
tomer's ROM code number for devices manufactured with customer ROM 
code (eg., R150x123FN) and by the suffix of the standard device number for 
devices with EEPROM. Table 1 6-1 indicates the package type, suffix indicator, 
and family members supported on that package type. 

Table 16-1. Package Types 



PACKAGE TYPE 


SUFFIX 
INDICATOR 


FAMILY MEMBERS 


28-pin plastic DIP 
(100-mil pin spacing) 


N 


TMS370C010, TMS370C810 


28-pin PLCC 
(50-mil pin spacing) 


FN 


TMS370C010, TMS370C810 


68-pin PLCC 
(50-nnil pin spacing) 


FN 


TMS370C050, TMS370C850 



16-5 



Customer Information - Mechanical Package Information 



EITHER OR BOTH 
INDEX MARKS 





« 36.6 (1.4401 MAX m 




1 — II — II — II — ini — II — II — II — II — 11 — II — II — II — 1 








ZJ 


'^ 
















"-LZJi iL-TT II luunm—jmcui ii iLiznrrr 



. 15,24 ± 0.25 
0.600 ± 0.010 



105° 
■90° 



0.28 ± 0.08 
(0.011 ± 0.003) 




0,51 (0.020) 
MIN 1 

SEATING -t- 
PLANE 




I 



0.46 ± 0.08 
(0.018 ± 0.003) 
PIN SPACING 2.54 (0.1001 T.P. 
(SEE NOTE D) 



-^14 



5.08 (0.200)_ 
MAX 




Ti 



-0.84 (0.33) MIN 



> 1,27 ± 0.51 

1,40 ± 0.18 (0.050 ± 0.020) 
<°0^^*°0"' 3.17(0.125). 

MIN 



ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 

NOTE D. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position. 



Figure 16-2. 28-pin Plastic Dual-Inline Package, 100-MIL Pin Spacing (Type N 

Package Suffix) 



16-6 



Customer Information - Mechanical Package Information 

4,50 (0.177) 




1.22 (0.048) 



1.07 (0.042) 



o 



11.43 (0.450) 



11.58 (0.456) 



12.32 (0.485) 



12,57 (0.496) 




2.79(0.110) 



2.41 (0.095) 
0.94 (0.037) 



X 



12.57 (0.496) 



11.43 (0.450) 
11.58 (0.456) 



0.69 (0.027) 
"I 



10,92 (0.432) 
10.41 (0.410) 
(AT SEATING PLANE) 

1.27 (0.050) 

T.P. 

(SEE NOTE B) 



1 



SEATING PLANE 
(SEE NOTE C) 



0.81 (0.032) 



0,66 (0.026) 



0,25 (0.010) 



1,52 (0.060) 
MIN 



n 

0,64 (0.025) MIN 



0,51 (0.0241 
0,36 (0.014) 

LEAD DETAIL 



ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 

NOTES: A. Center line of center pin each side is within 0,10 (0.004) of package centerline as determined from this dimension. 

B. Location of each pin is within 0,127 (0.005) of time position with respect to center pin on each side. 

C. The lead contact points are planar within 0.10 (0.004). 

Figure 16-3. 28-Pin Plastic- Leaded Chip Carrier Package (Type FN Package 

Suffix) 



16-7 



Customer Information - Mechanical Package Information 

4,50 (0.177) 



4,24 (0.167) 

2,79 (0.110) 

-2,41 (0.095) 

1,35 (0.053) 



1,19 (0.047) 



■0,25 (0.010) R MAX 
IN 3 PLACES 




1,27 (0.050) T.P. 
(SEE NOTE B) 



23,62 (0.930) 
23,11 (0.910) 
(AT SEATING PLANE) 



0,94 (0.037) 
0,69 (0.027) 



SEATING PLANE 



:z 



24,33 (0.956) 



-T 



24,13 (0.950) 
25,27 (0.995) 



(SEE NOTE A)- 



25,27 (0.995) 
25,02 (0.985) 



24,33 (0.956) 



24,13 (0.950) 
(SEE NOTE A) 



1.22 (0.048) 



25,02 (0.985) 



0,81 (0.032) 



1,52 (0.060) IVIIN 




0,64 (0.025) MIN 



0,36 (0.014) 

LEAD DETAIL 

NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centeriine as determined by this dimension. 
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side. 

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES. 

Figure 16-4. 68-Pin Plastic Leaded Chip Carrier Package (Type FN Package 

Suffix) 



16-8 



Customer Information - Numbering and Symbol Conventions 



16.3 TMS370 Family Numbering and Symbol Conventions 

All TMS370 devices are marked with information as to the type, package, co- 
pyright date(s), place of manufacture, and manufacturing data. 

16.3.1 Device Prefix Designators 

To provide expeditious system evaluations by customers during the product 
development cycle, Texas Instruments assigns a prefix designator with three 
options: TMX, TMP, and TMS. 

TMX, TMP, and TMS are representative of the evolutionary stages of product 
development from engineering prototypes through fully qualified production 
devices. Figure 16-5 depicts this evolutionary development flowchart. Pro- 
duction devices shipped by Texas Instruments have the TMS designator sig- 
nifying that they have demonstrated the high standards of Texas Instruments 
quality and reliability. 



TMXxxxx 



Experimental devices that may not be represent- 
ative of the final device's electrical specifications 
and have not completed reliability verification. 



TMPxxxx 



Devices that conform to the electrical 
specifications but have not completed 
quality and reliability verification. 



TMSxxxx 



Fully qualified production devices. 



Figure 16-5. Development Flowchart 



TMX devices are shipped against the following disclaimer: 

1) Experimental product and its reliability has not been characterized. 

2) Product is sold "as is". 

3) Product is not warranted to be exemplary of final production version if 
or when released by Texas Instruments. 

TMP devices are shipped against the following disclaimer: 

1 ) Customer understands that the product purchased hereunder has not 
been fully characterized and the expectation of reliability cannot be de- 
fined; therefore, Texas Instruments standard warranty refers only to the 
device's specifications. 

2) No warranty of merchantability or fitness is expressed or implied. 

TMS devices have been fully characterized and the quality and reliability of the 
device has been fully demonstrated. Texas Instruments' standard warranty 
applies. 



16-9 



Customer Information - Numbering and Symbol Conventions 



16.3.2 Device Numbering Convention 

Figure 16-6 illustrates the numbering and symbol nomenclature for the 
TMS370 family. 



TMS370C810 FN L 

U U I 



PREFIX: TMS-STANDARD PREFEX FOR 
FULLY QUALIFIED DEVICES 

FAMILY: 370-TMS370 8-BIT 

MICROCONTROLLER FAMILY 

TECHNOLOGY: C-CMOS 
PROGRAM MEMORY: 0-MASK ROM 
8-EEPROM 



TEMPERATURE RANGE: A- -40 C TO 85 C 
L- 0°C TO 70°C 
S- 25°C 

PACKAGE TYPE: N-PLASTIC DIP 

FN-PLASTIC LEADED CHIP CARRIER 



PRODUCT CONFIGURATION 



Figure 16-6. TMS370 Family Nomenclature 



16.3.3 Device Symbols 

The device symbolization of the TMS370 family members can be divided into 
two catagories: those with factory programmed mask ROM, and those with 
user programmed memory. 

16.3.3.1 TMS370 Family Members with Mask-ROM 

TMS370 family members with mask-ROM are custom-programmed devices 
where the ROM is mask programmed according to the customer's application 
code. These devices follow the prototyping and production flow outlined in 
Section 1 6.3. Since they are semi-custom devices, they receive a unique ROM 
code identification number. 



* 



LINE 1: (a) 

LINE 2: 

LINE 3: (f)©198BTI 

LINE 4: (g) 12345678 



(b) 123456789012 (c) 980 



(d) R1X0DXXFN 



(h) PHILIPPINES 



(e) FRSYYWW 



KEY: 

(a)TEXAS INSTRUMENTS TRADEMARK 

(b)OPTIONAL CUSTOMER PART NUMBER 

(c)EIA IDENTIFICATION NUMBER 

(d) CUSTOMER'S ROM CODE& PACKAGE TYPE 

(e)TRACKING MARK & DATE CODE 

( f )TI MICROCODE COPYRIGHT 

(g)LOT CODE 

(h)ASSEMBLY SITE 



Figure 16-7. Tl Standard Symbolization for Mask ROM Device In 28-Pln N-Type 

Package 



16-10 



Customer Information - Numbering and Symbol Conventions 



LINE 1: (a) 123456789012 

LINE 2: (b)RIXODXXFN 

LINE 3: (c)980 (d) FRSYYWW 

LINE 4: (e) 12345678 

LINE 5: (f)019B6TI 

(BACKSIDE) (g) PHILIPPINES 



KEY: 

(a)OPTIONAL CUSTOMER PART NUMBER 

(b)CUSTOMER'S ROM CODE 4 PACKAGE TYPE 

{c)EIA IDENTIFICATION NUMBER 

(d)TRACKING MARK & DATE CODE 

(e)LOT CODE 

(f )TI MICROCODE COPYRIGHT 

(a)ASSEMBLY SITE (BOTTOM OF PACKAGE) 



Figure 16-8. Tl Standard Symbolization for Mask ROM Device in 28-Pin FN Type 

Paclcage 



LINE 1: (a) 123458789012 

LINE 2: (c)RIXODXXFN 

LINE 3: (d) 

LINE 4: 

LINE 5: (g)©1986TI 

(BACKSIDE) 



*. 



(b)980 

(b)FRSYYWW 
(f) 12345678 

(h)PHILIPPINES 



KEY: 

(a)OPTIONAL CUSTOMER PART NUMBER 

(b)E!A IDENTIFICATION NUMBER 

(c)CUSTOMER'S ROM CODE& PACKAGE TYPE 

{d)TEXAS INSTRUMENTS TRADEMARK 

(e)TRACKING MARK & DATE CODE 

(f)LOT CODE 

(g)TI MICROCODE COPYRIGHT 

(h)ASSEMBLY SITE 



Figure 16-9. Tl Standard Symbolization for Mask ROM Device in 68-Pin FN Type 

Package 



16.3.3.2 TMS370 Family Members with Program EEPROM 

TMS370 family members with on-chip program EEPROM are standard device 
types, and therefore have a standard identification. The TMS370 family 
members with program EEPROM include the TMS370C810 and the 
TMS370C850. 



LINE 1: 

LINE 2: (a) 

LINE 3: (d) ©1986TI 

LINE 4: (f) PHILIPPINES 



(b) TMS370C810N 

(c) FRSYYWW 
(e) 12345678 



KEY: 

(a)TEXAS INSTRUMENTS TRADEMARK 

(b) STANDARD DEVICE PART NUMBER 

(c)TRACKING MARK & DATE CODE 

(d)TI MICROCODE COPYRIGHT 

(e)LOT CODE 

( f lASSEMBLY SITE 



Figure 16-10. Tl Standard Symbolization for Program EEPROM Device in 

N-Type Package 



16-11 



Customer Information - Numbering and Symbol Conventions 



LINE 1: (a) TMS370C850FN 

LINE 2: (b). 

LINE 3: 

LINE 4: (e) ©1986TI 

(BACKSIDE) 



^ 



(c) FRSYYWW 
(d) 12345678 

(f) PHILIPPINES 



KEY: 

{a)STANDARD DEVICE NUMBER 

(b)TEXAS INSTRUMENTS TRADEMARK 

(c)TRACKING MARK& DATE CODE 

(d)LOT CODE 

(e)TI MICROCODE COPYRIGHT 

( f )ASSEMBLY SITE (BOTTOM OF PACKAGE) 



Figure 16-11. Tl Standard Symboiization for EEPROM Device in FN-Type 

Package 



16-12 



Customer Information - Development Support Tools 



16.4 Development Support Tools Ordering Information 

All the necessary development support tools (excluding a PC) for the TMS370 
family are available from Tl separately or as a complete package. The devel- 
opement tools are designed to work with an IBM, IBM compatible or Tl PC 
with a minimum of 51 2K bytes of memory and a 5 1 /4 inch floppy disk drive. 

16.4.1 TMS370 Macro Assembler, Linker, and Utilities 

This software package includes all the utilities required for developing object 
code for the TMS370 devices. 



PART NUMBER DESCRIPTIOIM 

TMDS3740810-02 Assembler/Linker 

16.4.2 TMS370 EEPROM Programmer 

The TMS370 EEPROM Programmer provides the physical means to program 
the TMS370 prototype devices. The programmer comes with the necessary 
cables and control software for interfacing with an IBM compatible or Tl PC. 

PART NUMBER DESCRIPTION 

TMDS3760510 EEPROM Programmer 

16.4.3 TMS370 XDS System 

The XDS System provides software debugging and overall evaluation of a 
TMS370-based system. The XDS comes complete with necessary cables and 
debugging program. 

PART NUMBER DESCRIPTION 

TMDS3762210 XDS System 

16.4.4 Complete TMS370 Development System 

The components above (Assembler/Linker, EEPROM Programmer, and XDS 
System) are available as a single package providing full support of the 
TMS370 family devices. 

PART NUMBER DESCRIPTION 

TMDS3792210 TMS370 Development 



16-13 



Customer Information - Development Support Tools 



16-14 



Introduction 



TIVIS370 Family Devices 



CPU and Memory Organization 



System and Digital I/O Configuration 



Interrupts tmd System Reset 



EEPROM Modules 



Timer 1 Module 



Timer 2 Module 



Serial Communications Interface (SCI) Port 



Serial Peripheral Interface (SPI) Module MM 



Analog-To>D!gital Converter Module 



Assembly Language Instruction Set 



Design Aids 



Development Support 



Electrical Specifications 



Customer Infomfiatlon 



Appendixes 



A. Peripheral File Map 



This appendix summarizes the Peripheral File (PF) and control bit information 
into a single location for reference. 

Each PF register is presented as a row of boxes containing the control or sta- 
tus bits belonging to the register. The register symbol (e.g., SCCRO) and the 
PF hex address (i.e., P010) are to the left of each register. 

The read/write accessibility of each bit is indicated in parentheses below each 
bit symbol, with the following definitions: 

• R - read 

• W - write 

O P - write in the privilege mode only 

• C- clear only 
O S - set only 

• -0- cleared by RESET 

• -1 -set by RESET 

O -t - this bit exhibits special behavior during or after RESET; see the de- 
scription for this bit in the appropriate section (both bit and register are 
index entries). 

The register summary is followed by block diagrams of the major circuits. The 
control bits are shown in these diagrams in the following format: 

(xx.n) 4A.0 Bit location convention used in figures, where 'xx' is the 
hexadecimal address of the peripheral register containing 
the bit and 'n' is the bit number (7 = msb, = Isb). 



A-1 



Appendix A 



Bit#- 

SCCRO 
P010 



SCCR1 
P011 



SCCR2 
P012 



INT1 
P017 



INT2 
P018 



INT3 
P019 



DEECTL 
P01A 

PEECTL 
P01C 

AP0RT2 
P021 

ADATA 
P022 

ADIR 
P023 

BP0RT2 
P025 

BDATA 
P026 

BDIR 
P027 

CPORT2 
P029 

CDATA 
P02A 

CDIR 
P02B 

DPORT1 
P02C 

DP0RT2 
P02D 

DDATA 
P02E 

DDIR 
P02F 



7 


6 


5 


4 


3 


2 


1 





COLD 
START 
(RC-t) 


OSC 
POWER 
(RP-0) 


PF 
AUTO 
WAIT 
(RW-0) 


OSC 

FLT 

FLAG 

(RW-t) 


MODE 
PIN 
WPO 
(R-t) 


MC 

PIN 

DATA 

(R-t) 


... 


MP/MC 

Mode 

(R) 


— 


— 


... 


AUTOWAIT 

DISABLE 

(RP-0) 


... 


MEMORY 

DISABLE 

(RP-t) 


... 


... 


HALT/ 

STANDBY 

(RP-0) 


PWR- 

DWN/ 

IDLE 

(RP-0) 


OSC 
FLT RST 

ENA 
(RP-0) 


BUS 
STEST 
(RP-0) 


CPU 
STEST 
(RP-1) 


OSC 

FLT 

DISABLE 

(RP-0) 


INT1 

NMI 

(RP-0) 


PRIV- 
ILEGE 
DISABLE 
(RS-0) 


INT1 
FLAG 
(RC-0) 


INT1 

Pin 

DATA 

(R-0) 


... 


... 


... 


INT1 

POLARITY 

(RW-0) 


INT1 

PRIORITY 

(RW-0) 


INT1 
ENABLE 
(RW-0) 


INT2 
FLAG 
(RC-0) 


INT2 

PIN 

DATA 

(R-0) 


... 


INT2 

DATA 

DIR 

(RW-0) 


INT2 

DATA 

OUT 

(RW-0) 


INT2 

POLARITY 

(RW-0) 


INT2 

PRIORITY 

(RW-0) 


INT2 
ENABLE 
(RW-0) 


INT3 
FLAG 
(RC-0) 


INT3 

PIN 

DATA 

(R-0) 


... 


INT3 
DATA 

DIR 
(RW-0) 


INT3 

DATA 

OUT 

(RW-0) 


INT3 

POLARITY 

(RW-0) 


INT3 

PRIORITY 

(RW-0) 


INT3 
ENABLE 
(RW-0) 


BUSY 
(R-t) 


— 


... 


... 


... 


AP 
(RW-0) 


W1W0 
(RW-0) 


EXE 
(RW-0) 


BUSY 
(R-t) 


... 


... 


... 


... 


AP 
(RW-0) 


W1W0 
(RW-0) 


EXE 
(RW-0) 


PORT A CONTROL REGISTER 2 


PORT A DATA 


PORT A DIRECTION 


PORT B CONTROL REGISTER 2 


PORT B DATA 


PORT B DIRECTION 


PORT C CONTROL REGISTER 2 


PORT C DATA 


PORT C DIRECTION 


PORT D CONTROL REGISTER 1 


PORT D CONTROL REGISTER 2 


PORT D DATA 


PORT D DIRECTION 



A-2 



Appendix A 



SPICCR 
P030 



SPICTL 
P031 



SPIBUF 
P037 



S PI DAT 
P039 



SPIPC1 
P03D 



SPIPC2 
P03E 



SPIPRI 
P03F 



T1CNTR MSB 
P040 

T1CNTR LSB 
P041 

TIC MSB 
P042 

nC LSB 
P043 

T1CC MSB 
P044 

T1 CC LSB 
P045 

WDCNTR MSB 

P046 
WDCNTR LSB 

P047 

WDRST 
P048 

T1CTL1 
P049 



T1CTL2 
P04A 



T1CTL3 
P04B 



T1 CTL4 
P04C 



SPI 

SW 
RESET 
(RW-O) 


CLOCK 

POLARITY 

(RW-O) 


SPI 

BIT 
RATE2 
(RW-O) 


SPI 

BIT 
RATE1 
(RW-O) 


SPI 

BIT 
RATED 
(RW-O) 


SPI 
CHAR2 
(RW-O) 


SPI 
CHAR1 
(RW-O) 


SPI 
CHARO 
(RW-O) 


RECEIVER 

OVERRUN 

(R-0) 


SPI 
INT 
FLAG 
(R-0) 


— 


... 


... 


MASTER/ 
SLAVE 
(RW-O) 


TALK 
(RW-O) 


SPI 

INT 

ENA 

(RW-O) 


RCVD7 
(R-0) 


RCVD6 
(R-0) 


RCVD5 
(R-0) 


RCVD4 
(R-0) 


RCVD3 
(R-0) 


RCVD2 
(R-O) 


RCVD1 
(R-0) 


RCVDO 
(R-O) 


SDAT7 
(RW-O) 


SDAT6 
(RW-O) 


SDAT5 
(RW-O) 


SDAT4 
(RW-O) 


SDAT3 
(RW-O) 


SDAT2 
(RW-O) 


SDAT1 
(RW-O) 


SDATO 
(RW-O) 


— 


— 


... 


... 


SPICLK 
DATA 

IN 
(R-0) 


SPICLK 
DATA 
OUT 

(RW-O) 


SPICLK 

FUNCTION 

(RW-O) 


SPICLK 

DATA 

DIR 

(RW-O) 


SPISIMO 
DATA 

IN 
(R-0) 


SPISIMO 

DATA 

OUT 

(RW-O) 


SPISIMO 

FUNCTION 

(RW-O) 


SPISIMO 

DATA 

DIR 

(RW-O) 


SPISOMI 
DATA 

IN 
(R-0) 


SPISOMI 

DATA 

OUT 

(RW-O) 


SPISOMI 

FUNCTION 

(RW-O) 


SPISOMI 

DATA 

DIR 

(RW-O) 


SPI 
STEST 
(RP-O) 


SPI 

PRIORITY 

(RP-O) 


SPI 
ESPEN 
(RP-O) 


... 


... 


... 


... 


... 


Bit 15 




T1 COUNTER MSB 




Bits 


Bit 7 




T1 COUNTER LSB 




Bit 


Bit 15 




COMPARE REGISTER MSB 




Bits 


Bit 7 




COMPARE REGISTER LSB 




BrtO 


Bit 15 




CAPTURE/COMPARE REGISTER MSB 




Bits 


Bit 7 




CAPTURE/COMPARE REGISTER LSB 




BitO 


Bit 15 




WATCHDOG COUNTER MSB 




Bits 


Bit 7 




WATCHDOG COUNTER LSB 




BitO 


Bit 7 




WATCHDOG RESET KEY 




BitO 


WD 

OVRFL 

TAP SEL 

(RP-O) 


WD 

INPUT 

SELECT 2 

(RP-O) 


WD 

INPUT 

SELECT 1 

(RP-O) 


WD 

INPUT 

SELECT 

(RP-O) 


... 


T1 

INPUT 

SELECT 2 

(RW-O) 


T1 

INPUT 

SELECT 1 

(RW-O) 


T1 

INPUT 

SELECT 

(RW-O) 


WD 

OVRFL 

RST ENA 

(RS-O) 


WD 
OVERFL 
INT ENA 
(RW-O) 


WD 

OVERFL 

INT FLAG 

(RC-t) 


T1 
OVRFL 
INT ENA 
(RW-O) 


T1 

OVRFL 

INT FLAG 

(RC-O) 


... 


... 


T1 

SW 

RESET 

(S-O) 


T1EDGE 

INT 

FLAG 

(RC-O) 


T1C2 

INT 

FLAG 

(RC-O) 


T1C1 

INT 

FLAG 

(RC-O) 


Dual Comi 


oare Mode 


T1EDGE 
INT 
ENA 

(RW-O) 


T1C2 

INT 

ENA 

(RW-O) 


T1C1 

INT 

ENA 

(RW-O) 


T1EDGE 

INT 

FLAG 

(RC-O) 


— 


T1C1 

INT 

FLAG 

(RC-O) 


Capture/Coi 


•npare Mode 


T1EDGE 
INT 
ENA 

(RW-O) 


— 


T1C1 

INT 

ENA 

(RW-O) 


T1 
MODE 

=0 
(RW-O) 


T1C1 

OUT 

ENA 

(RW-O) 


T1C2 

OUT 

ENA 

(RW-O) 


Dual Comi 

T1C1 

RST 

ENA 

(RW-O) 


oare Mode 

T1CR 

OUT 

ENA 

(RW-O) 


T1 

EDGE 

POLARITY 

(RW-O) 


T1CR 
RST 
ENA 

(RW-O) 


T1EDGE 
DET 
ENA 

(RW-O) 


T1 
MODE 

=1 
(RW-O) 


T1C1 

OUT 

ENA 

(RW-O) 


... 


CapturefCot 

T1C1 
RST 

ENA 
(RW-O) 


npare Mode 


T1 

EDGE 

POLARITY 

(RW-O) 


... 


T1EDGE 
DET 
ENA 

(RW-O) 



A-3 



Appendix A 



Bit # - 


7 


6 


5 


4 


3 


2 


1 





T1PC1 
P04D 


... 


... 


... 


... 


T1EVT 
DATA 

IN 

(R-0) 


T1EVT 
DATA 
OUT 
(RW-0) 


T1EVT 
FUNCTION 
(RW-0) 


T1EVT 

DATA 

DIR 

(RW-0) 


T1PC2 
P04E 


T1PWM 
DATA 

IN 
(R-0) 


T1PWM 
DATA 
OUT 

(RW-0) 


T1PWM 
FUNCTION 

(RW-0) 


T1PWM 

DATA 

DIR 

(RW-0) 


T1IC/CR 
DATA 

IN 
(R-0) 


T1IC/CR 

DATA 

OUT 

(RW-0) 


niC/CR 
FUNCTION 

(RW-0) 


T1IC/CR 

DATA 

DIR 

(RW-0) 


T1PRI 
P04F 


T1 
STEST 
(RP-0) 


n 

PRIORITY 
(RP-O) . 


... 


... 


... 


... 


... 


... 


SCICCR 
P050 


STOP 

BITS 

(RW-0) 


EVEN/ 

ODD 

PARITY 

(RW-0) 


PARITY 
ENABLE 
(RW-0) 


ASYNC/ 

ISOSYNC 

(RW-0) 


ADDRESS 

IDLE 

WUP 

(RW-O) 


SCI 
CHAR2 
(RW-0) 


SCI 
CHAR1 
(RW-0) 


SCI 
CHARO 
(RW-0) 


SCICTL 
P051 


... 


... 


SCI 

SW 
RESET 
(RW-0) 


CLOCK 
(RW-0) 


TXWAKE 
(RS-0) 


SLEEP 
(RW-0) 


TXENA 
(RW-0) 


RXENA 
(RW-0) 


BAUD MSB 
P052 


BAUDF 
(msb) 


BAUDE 


BAUDD 


BAUDC 


BAUDB 


BAUDA 


BAUD9 


BAUDS 


BAUD LSB 
P053 


BAUD7 
(RW-0) 


BAUD6 
(RW-0) 


BAUDS 
(RW-0) 


BAUD4 
(RW-0) 


BAUD3 
(RW-0) 


BAUD2 
(RW-0) 


BAUD1 
(RW-0) 


BAUDO 

(Isb) 
(RW-0) 


TXCTL 
P054 


TXRDY 
(R-1) 


TX 

EMPTY 

(R-1) 


... 


... 


... 


... 


... 


SCITX 
INT ENA 
(RW-0) 


RXCTL 
P055 


RX 
ERROR 
(R-0) 


RXRDY 
(R-0) 


BRKDT 
(R-0) 


FE 
(R-0) 


OE 
(R-0) 


PE 
(R-0) 


RXWAKE 
(R-0) 


SCI RX 
INT ENA 
(RW-0) 


RXBUF 
P057 


RXDT7 
(R-0) 


RXDT6 
(R-0) 


RXDTS 
(R-0) 


RXDT4 
(R-0) 


RXDT3 
(R-0) 


RXDT2 
(R-0) 


RXDT1 
(R-0) 


RXDTO 
(R-0) 


TXBUF 
P059 


TXDT7 
(RW-0) 


TXDT6 
(RW-0) 


TXDTS 
(RW-0) 


TXDT4 
(RW-0) 


TXDT3 
(RW-0) 


TXDT2 
(RW-0) 


TXDT1 
(RW-0) 


TXDTO 
(RW-0) 


SCIPC1 
P05D 


... 


.... 


... 


... 


SCICLK 
DATA 

IN 
(R-0) 


SCICLK 

DATA 

OUT 

(RW-0) 


SCICLK 

FUNCTION 

(RW-0) 


SCICLK 

DATA 

DIR 

(RW-0) 


SCIPC2 
POSE 


SCITXD 
DATA 

IN 
(R-0) 


SCITXD 
DATA 
OUT 

(RW-0) 


SCITXD 

FUNCTION 

(RW-0) 


SCITXD 

DATA 

DIR 

(RW-0) 


SCIRXD 
DATA 

IN 
(R-0) 


SCIRXD 
DATA 
OUT 

(RW-0) 


SCIRXD 

FUNCTION 

(RW-0) 


SCIRXD 

DATA 

DIR 

(RW-0) 


SCIPRI 
P05F 


SCI 
STEST 
(RP-O) 


SCITX 
PRIORITY 
(RP-O) 


SCIRX 
PRIORITY 
(RP-O) 


SCI 
ESPEN 
(RP-O) 


... 


... 


... 


... 


T2CNTR MSB 
P060 


Bit 15 




T2 COUNTER MSB 




Bits 


T2CNTR LSB 
P061 


Bit 7 




T2 COUNTER LSB 




BitO 


T2C MSB 
P062 


Bit 15 




COMPARE REGISTER MSB 




Bits 


T2C LSB 
P063 


Bit 7 




COMPARE REGISTER LSB 




BitO 


T2CC MSB 
P064 


Bit IS 




CAPTURE/COMPARE REGISTER MSB 




Bits 


T2CC LSB 
P065 


Bit 7 




CAPTURE/COMPARE REGISTER LSB 




BitO 


T2IC MSB 
P066 


Bit 15 




T2 CAPTURE REGISTER MSB 




Bits 


T2IC LSB 
P067 


Bit 7 




T2 CAPTURE REGISTER LSB 




BitO 



A-4 



Appendix A 



Blt#- 

T2CTL1 
P06A 



T2CTL2 
P06B 



T2CTL3 
P06C 



T2PC1 
P06D 



T2PC2 
P06E 



T2PRI 
P06F 



ADCTL 
P070 



ADSTAT 
P071 



AD DATA 
P072 



ADIN 
P07D 



ADENA 
P07E 



ADPRI 
P07F 



7 


6 


5 


4 


3 


2 


1 







... 


... 


T2 OVRFL 

INT 

ENA 

(RW-0) 


T2 OVRFL 

INT 

FLAG 

(RC-0) 


T2 INPUT 
SELECT 

1 
(RW-0) 


T2 INPUT 
SELECT 


(RW-0) 


T2 

SW 
RESET 
(S-0) 


T2EDGE1 

INT 

FLG 

(RC-0) 


T2C2 

INT 

FLG 

(RC-0) 


T2C1 
INT 
FLG 

(RC-0) 


Dual Compare Mode 


T2EDGE1 

INT 

ENA 

(RW-0) 


T2C2 

INT 

ENA 

(RW-0) 


T2C1 

INT 

ENA 

(RW-0) 


T2EDGE1 

INT 

FLG 

(RC-0) 


T2EDGE2 

INT 

FLG 

(RC-0) 


T2C1 
INT 
FLG 

(RC-0) 


Dual Capture Mode 


T2EDGE1 

INT 

ENA 

(RW-0) 


T2EDGE2 

INT 

ENA 

(RW-0) 


T2C1 

INT 

ENA 

(RW-0) 


T2 
MODE 

=0 
(RW-0) 


T2C1 

OUT 

ENA 

(RW-0) 


T2C2 

OUT 

ENA 

(RW-0) 


Dual Compare Mode 

T2C1 T2EDGE1 

RST OUT 

ENA ENA 

(RW-0) (RW-0) 


T2EDGE1 

POLARITY 

(RW-0) 


T2EDGE1 

RST 

ENA 

(RW-0) 


T2EDGE1 

DET 

ENA 

(RW-0) 


T2 
MODE 

=1 
(RW-0) 


... 


... 


Dual Capi 

T2C1 

RST 

ENA 

(RW-0) 


ure Mode 

T2EDGE2 

POLARITY 

(RW-0) 


T2EDGE1 

POLARITY 

(RW-0) 


T2EDGE2 

DET 

ENA 

(RW-0) 


T2EDGE1 

DET 

ENA 

(RW-0) 


... 


... 


... 


... 


T2EVT 
DATA 

IN 
(R-0) 


T2EVT 

DATA 

OUT 

(RW-0) 


T2EVT 

FUNCTION 

(RW-0) 


T2EVT 
DATA 

DIR 
(RW-0) 


T2IC2/ 

PWM 

DATA IN 

(R-0) 


T2IC2/ 

PWM 

DATA OUT 

(RW-0) 


T2IC2/ 

PWM 

FUNCTION 

(RW-0) 


T2IC2/ 

PWM 

DATA DIR 

(RW-0) 


T2IC1/ 

CR 

DATA IN 

(R-0) 


T2IC1/ 

CR 

DATA OUT 

(RW-0) 


T2IC1/ 

CR 

FUNCTION 

(RW-0) 


T2IC1/ 

CR 

DATA DIR 

(RW-0) 


T2 
STEST 
(RP-0) 


T2 

PRIORITY 

(RP-0) 


... 


... 


... 


... 


... 


... 


CONVERT 
START 
(RW-0) 


SAMPLE 
START 
(RW-0) 


REF 

VOLT 

SELECT2 

(RW-0) 


REF 

VOLT 

SELECT1 

(RW-0) 


REF 

VOLT 

SELECTO 

(RW-0) 


AD 

INPUT 

SELECT2 

(RW-0) 


AD 

INPUT 

SELECT1 

(RW-0) 


AD 

INPUT 

SELECTO 

(RW-0) 


... 


— 


... 


... 


... 


AD 
READY 
(R-1) 


AD 

INT 

FLAG 

(RC-0) 


AD 

INT 

ENA 

(RW-0) 


DATA7 
(R-0) 


DATA6 
(R-0) 


DATA5 
(R-0) 


DATA4 
(R-0) 


DATA3 
(R-0) 


DATA2 
(R-0) 


DATA1 
(R-0) 


DATAO 
(R-0) 


PORT E 
DATA 
AN 7 
(R-0) 


PORT E 
DATA 
AN 6 
(R-0) 


PORT E 
DATA 
AN 5 
(R-0) 


PORT E 
DATA 
AN 4 
(R-0) 


PORT E 
DATA 
AN 3 
(R-0) 


PORT E 
DATA 
AN 2 
(R-0) 


PORTE 
DATA 
AN 1 
(R-0) 


PORT E 
DATA 
AN 
(R-0) 


PORT E 
INPUT 
ENA7 

(RW-0) 


PORT E 
INPUT 
ENA 6 

(RW-0) 


PORT E 
INPUT 
ENA 5 

(RW-0) 


PORT E 
INPUT 
ENA 4 

(RW-0) 


PORTE 
INPUT 
ENA 3 

(RW-0) 


PORT E 
INPUT 
ENA 2 

(RW-0) 


PORTE 
INPUT 
ENA1 

(RW-0) 


PORT E 
INPUT 
ENAO 

(RW-0) 


AD 
STEST 
(RP-0) 


AD 

PRIORITY 

(RP-0) 


AD 
ESPEN 
(RP-0) 


... 


— 


... 


... 


... 



A-5 



Appendix A 



P017.6 



NMI 




P017.7 

OTHER LEVEL 2 INTERRUPTS • 
OTHER LEVEL 1 INTERRUPTS- 



> STATUS REGISTER 
GLOBAL INTERRUPT 
ENABLE BITS 



Figure A-1. interrupt 1 Bloci< Diagram 



P018.6 
P019.6 



P018.3 
P019.3 



INPUT 

PIN 

DATA 



DATA 
OUT 



INT 

PIN 



il, 

190 



OTHER LEVEL 2 INTERRUPTS 
OTHER LEVEL 1INTERRUPTS-n 

P018.0 
P019.0 



DATA 
DIR 



P018.4 
P019.4 



1- 
1 = RISING 



I = FALLING 



CLR 



ENABLE 



POLARITY 



P018.2 
P019.2 



-crio- 



IE2 



ST 






WAKE-UP 
CIRCUITRY 



LEVEL 2 INT REG 



LEVEL 1 INT REG 



WRITE READ 
INT FLAG 



PRIORITY 
SELECT 



IE1 



ST 



P018.1 
P019.1 



STATUS REGISTER GLOBAL 
INTERRUPT ENABLE BITS 



P018.7 
P019.7 



Figure A-2. Interrupts 2 and 3 Blocic Diagram 



A- 6 



Appendix A 




T1 

IC/CR [I> 
PIN 



LEVEL 1 INT 



LEVEL 2 INT 



T1 EDGE 
"POLARITY 4C.2 



Figure A-3. Timer 1: Dual Compare IVIode 



A-7 



Appendix A 



EVENT 



FREQUENCY 



T1 EVT 

PIN 




Figure A-4. Timer 1 System Clock Prescaier 



A-8 



Appendix A 



CLOCK 
PRESCALER 



LSB 16-BIT 
MSB COUNTER 



RESET 



(^ 



S/W 

RESET- 

4A.0 



CMP 1 
RESET ENA 

o\o 

4C.4 



T1 ,_^ 
IC/CR L> 
PIN 



EDGE 
SELECT 



16-BIT LSB 

CAPT/COMP 

REG ^°° 



45 
44 



<-> 



COMPARE 



16-BIT LSB 

COMPARE 

REG I^SB 



EDGE DETECT 
ENA 

o'o 



4C.0 
- EDGE POLARlPi' 4C.2 



COMPARE 



[FLAG 



4B.5 



OVERFLOW 



FLAG 



4A.3 



E XT EDG E 
—I FLAG h— 



4B.7 



4B.0 

— era — 
INT ENA 



4A.4 

— c/o — 

INT ENA 



4B.2 

— o^'o — 
INT ENA 



OUTPUT 
ENABLE 



4C.6 



T1 PWM 
PIN 



4F6 



</" 



LEVEL 1 INT 



LEVEL 2 INT 



Figure A-5. Timer 1: Capture/Compare Mode 





46 
47 




16- 


BIT 




WATCHDOG 

OVERFLOW 

FLAG 




4A.7 


SYSTEM 




rWATCHDOG COUNTER 






WD OVRFL 
RST.ENA 

4A.6 


RESET 






; 


i 


1 ii 




4A.5 






CLOCK 
PRESCALER 




WD OVRFL 
TAP SEL 






D 


coc-r 


















48 


WATCHDOG RESET KEY 






WD OVRFL 
INT ENA 


INTERRUPT 



Figure A-6. Watchdog Timer 



A-9 



Appendix A 



CLOCK 
SOURCE 



16-BIT LSB 

CAPT/COMP 

REG f^SB 



T2 IC1/ 



CR ? cjpi crT 

PIN ^^'-^^' 




-EDGE1 POLARITY 6C.2 

Figure A-7. Timer 2: Dual Compare Mode 



A-10 



Appendix A 



CLOCK 

SOURCE 



LSB - 16_BIT 
]^B COUNTER 



RESET 



C) 



S/W RESET J 
6A.0 



T2 IC1/ _ 
CR IZ> 
PIN 




EDGE1 
SELECT 



16-BIT LSB 

CAPT/COMP. ,-— 

REG 1 MSB 



LSB 



16-BIT 
CAPTURE 
REG 2 MSB 



'm 



sz. 



COMPARE = 



/IS. 



16-BIT LSB 

COMPARE . 

REG MSB 



EDGE 1 
DETECT ENA 1 

6C.0 
o^o 



T2 IC2/ ^_^ 
PWM O 
PIN 



EDGE2 
SELECT 



POLARITY 1 
6C.2 EDGE 1 

DETECT ENA 2 
6C.1 
cy'o 



COMPARE 1 



FLAG! 



6B.5 



6B.0 
INT ENA 



OVERFLOW 6A.4 



FLAG 



6A.3 



INT ENA 



EXT EDGE 1 



FLAG 



6B.7 



6B.2 
INT ENA 



6F.6 



POLARITY 2 
6C.3 



EXT EDGE 2 



FLAG 



6B.6 



6B.1 
INT ENA 



<^ 



LEVEL 1 INT 



LEVEL 2 INT 



Figure A-8. Timer 2: Dual Capture Mode 



A-11 



Appendix A 



50 



FRAME 

FORMAT 

AND MODE 



PARITY 



EVEN/ODD 



ENA 



50.6 



50.5 



SYS 

CLK 



53 



52 



LSB 



SCIRXD 
PIN 



o- 



55.1 



51.3 
TXWAKE 



TXBUF REG 



a: 



WUT 



TXSHF REG 



BAUD 



RATF 
MSB 16 BITS 



RXWAKE h-*- 



RX ERROR 



ERR 



FE 



OE 



PE 



55.7 55.4 55.3 55.2 



51.4 
CLOCK 



RXSHF REG 



/'8 
RXENA A 51.0 



RXBUF REG 



57 



59 



SCI TX INT 



54.0 



TXRDY 



-<f^^ 



INT ENA 



54.7 



54.6 



TX EMPP/ 



51.1 
-o-^o- 



TX ENA 



SCI RX INT 

55.6 55.0 



RXRDY 



55.5 
iBRKDTt 



INT ENA 



TXPRI 

o- 

^ 



5F.6 



LEVEL 1 INT 



LEVEL 2 INT 



-C> SCITXD PIN 



-g2 SCICLK PIN 



RXPR1 



^ 



^ LEVEL 1 INT 



5F.5 



LEVEL 2 INT 



Figure A-9. SCI Block Diagram 



A-12 



Appendix A 



37 



39 



8PIBUF BUFFER 
REGISTER 8 

b; 

I 



SPIDAT 
DATA REGISTER 



STATE CONTROL 



BITS/CHAR 



30. 



1 



SYS 
CLOCK' 



CLOCK RATE 



30. 



OVERRUN 31.7 



SPI INTERRUPT 



A FLAG I o^c 

I 1 IMT C 



31.6 



31.1 
TALK 



-<yo- 



31.0 



INT ENA 



PRIORITY ^ 
o^ 



3F.6 



LEVEL 1 INTREQ 



LEVEL 2 INTREO 



■^ 



MASTER/SLAVE MD 
31.2 



SPISIMO PIN 



o — 4 g2 SPISOMI PIN 



POLARITY 



30.6 



-Ea SPICLK 



Figure A-10. SPI Blocic Diagram 



A-13 



Appendix A 



PIN 



ANO 



AN1 



AN2 



AN3 



AN4 



AN5 



AN6 



AN7 



DIGITAL INPUT REGISTER 

''-im 

! 7D.0 



:.,n^ 



7D.1 



-H E2 



7E.2, 



7D.2 



7E.3 



<r-HlI 



7D.3 



7E.4 



.rtCH 



7D.4 



i-t^L 



7D.5 



7E.6 



r^^^^ 



7D.6 



7E.7r!7D:7 



C^ 



"CCS 
^SS3C=>- 



/7 



70.x 



70.6 



2 10 



INPUT 



SAMPLE 
START 



70.x 



5 4 3 



+VREF 



70.7 



CONVERT 
START 




72 



ADDATA REG 



71.2 



READY 



A/D INTERRUPT 
71.0 



FLAG 



71.1 



INT 
ENA 



o-^ LEVEL 1 INT 

^ LEVEL 2 INT 
7F.6 



Figure A-11. Analog-to-Digital Converter Block Diagram 



A-14 



B. Character Sets 



The TI\/IS370 Assembler recognizes the ASCII character set listed in Table B-1 . 
Table B-2 lists characters that the assembler does not recognize, but may be 
recognized and acted upon by other programs. The device service routine for 
the card reader accepts and stores into the calling program's buffer all the 
characters listed. 



HEX 

(tow 
nibble) 



Table B-1. ASCII Character Set 
1- 2- 3- 4- 5- 6- 7- 



NUL 


DLE 


SP 
32 





48 


<3 


} 


P 




' 




P 











16 


64 


80 




96 




112 


SOH 


DC1 


! 


33 


1 


49 


A 


65 


Q 


81 


= 


q 






1 




17 




97 




113 


ST 


X 


DC2 




34 


2 


50 


B 




R 




b 


r 1 




2 




18 


66 


82 




98 




114 


ETX 


DC3 


- 


35 


3 


51 


C 


67 


S 


83 





s 






3 




19 




99 




115 


EOT 


DC4 


$ 


36 


4 


52 


D 


68 


T 




d 


t 1 




4 




20 


84 




100 




1,6 


ENQ 


N/ 


\K 


% 


37 


5 


53 


E 


69 


U 




a 


u 1 




5 




21 


85 




101 




,17 


ACK 


SYN 


& 


38 


6 


54 


F 




V 




f 


V 1 




6 




22 


70 


86 




102 




118 


BEL 


ETB 




39 


7 


55 


G 




w 


87 


g 


w 






7 




23 


71 




103 




119 


BS 


1 
8 


U 


24 


( 


40 


8 


56 


H 


72 


X 


88 


h 


104 


X 


120 


HI 


r 


EM 


) 


41 


9 


57 


1 




Y 




• 


V 1 




9 




25 


73 


89 




105 




121 


LF 


SUB 




42 




58 


J 


74 


z 


90 


J 


z 






A 




26 




106 




122 


V7 




ESC 


+ 


43 


■ 


59 


K 


75 


[ 




k 


i 1 




B 




27 


91 




107 




123 


FF 


FS 




44 


< 


60 


L 




\ 


92 


1 


1 






C 




28 


76 




108 




124 


CF 


\ 


GS 


~ 


45 


' 


61 


M 




] 




m 


> 1 




D 




29 


77 


93 




109 




125 


SO 


RS 


> 




46 


> 


62 


N 


78 




94 


n 


~ 






E 




30 




110 




126 


SI 




US 


/ 


47 


? 


63 







■" 


95 


o 


DEL 1 




F 




31 


79 




111 




127 



nibble) 



B-1 



Appendix B 



Table B-2. Control Characters 



HEX 


DECIMAL 




VALUE 


VALUE 


CHARACTER 


00 





NUL 


01 


1 


SON 


02 


2 


STX 


03 


3 


ETX 


04 


4 


EOT 


05 


5 


ENQ 


06 


6 


ACK 


07 


7 


BEL 


08 


8 


BS 


09 


9 


HT 


OA 


10 


LF 


OB 


11 


VT 


OC 


12 


FF 


OD 


13 


OR 


OE 


14 


SO 


OF 


15 


SI 


10 


16 


DLE 


11 


17 


DC1 


12 


18 


DC2 


13 


19 


DC3 


14 


20 


DC4 


15 


21 


NAK 


16 


22 


SYN 


17 


23 


ETB 


18 


24 


CAN 


19 


25 


EM 


1A 


26 


SUB 


IB 


27 


ESC 


1C 


28 


FS 


ID 


29 


GS 


IE 


30 


RS 


IF 


31 


US 


7F 


127 


DEL 



B-2 



C. Opcode/Instruction Cross Reference 

Table C-1 (on the following pages) provides an opcode-to-instruction cross 
reference of all 73 mnemonics and 245 opcodes of the TMS370 instruction 
set. To check the instruction of a known opcode, locate the left (high) digit 
across the top or bottom of the table, then find the right (low) digit along the 
side of the table. The intersection contains the instruction mnemonic, oper- 
ands, and byte/cycle particular to that opcode. Some opcodes, such as BO, 
are shared by two instructions, in which case both mnemonics are shown 
along with the byte/cycles count. 



C-1 



Appendix C 



Table C-1. TMS370 Family Opcode/Instruction Map 








1 


2 


3 


4 


5 


6 


7 


8 


9 


A 


B 


C 


D 


E 


F 





JMP 
ra 
2/7 














INCW 
#n.Rd 
3/11 


MOV 
Ps.A 
2/8 






CLRC 

TSTA 

1/9 


MOV 
A.B 
1/9 


MOV 
A.Rd 
2/7 


TRAP 

15 

1/14 


LOST 

n 

2/6 


1 


JN 
ra 
2/5 




MOV 
A,Pd 
2/8 






MOV 
B.Pd 
2/8 




MOV 
Rs.Pd 
3/10 




MOV 
Ps.B 
2/7 








MOV 
B.Rd 
2/7 


TRAP 

14 
1/14 


MOV 

n(SP).A 

2/7 


2 


JZ 
ra 

2/5 


MOV 
Rs,A 
2/7 


MOV 
#n,A 
2/6 


MOV 
Rs.B 
2/7 


MOV 
Rs.Rd 
3/9 


MOV 

#n.B 
2/6 


MOV 
B.A 
1/8 


MOV 

#n.Rd 

3/8 






MOV 
Ps.Rd 
3/10 


DEC 
A 
1/8 


DEC 
B 

1/8 


DEC 

Rn 
2/6 


TRAP 

13 
1/14 


MOV 

A.n(SP) 

2/7 


3 


JC 
ra 
2/5 


AND 
Rs.A 
2/7 


AND 
#n,A 
2/6 


AND 
Rs,B 
2/7 


AND 
Rs.Rd 

3/9 


AND 
#n.B 
2/6 


AND 
B.A 
1/8 


AND 

#n.Rd 

3/8 


AND 
A.Pd 
2/9 


AND 
B.Pd 
2/9 


AND 
#n.Pd 
3/10 


INC 
A 
1/8 


INC 

B 
1/8 


INC 
Rn 
2/6 


TRAP 

12 
1/14 


CMP 

n(SP).A 

2/8 


4 


JP 
ra 
2/5 


OR 
Rs.A 
2/7 


OR 

#n,A 
2/6 


OR 
Rs,B 
2/7 


OR 
Rs.Rd 
3/9 


OR 

#n,B 
2/6 


OR 
B.A 
1/8 


OR 

#n.Rd 

3/8 


OR 
A.Pd 
2/9 


OR 
B.Pd 
2/9 


OR 

#n,Pd 
3/10 


INV 
A 
1/8 


INV 

B 
1/8 


INV 
Rn 
2/6 


TRAP 

11 
1/14 


extend 

lnst.2 

opcodes 


5 


JPZ 
ra 
2/5 


XOR 
Rs.A 
2/7 


XOR 

#n,A 
2/6 


XOR 
Rs.B 
2/7 


XOR 
Rs.Rd 
3/9 


XOR 

#n,B 
2/6 


XOR 

B.A 
1/8 


XOR 

#n,Rd 
3/8 


XOR 
A.Pd 
2/9 


XOR 

/ B.Pd 

2/9 


XOR 

#n,Pd 
3/10 


CLR 
A 
1/8 


CLR 

B 

1/8 


CLR 
Rn 
2/6 


TRAP 

10 
1/14 




6 


JNZ 
ra 
2/5 


BTJO 
Rs.A 
3/9 


BTJO 
#n,A 
3/8 


BTJO 
B.Rd 
3/9 


BTJO 
Rs.Rd 

4/11 


BTJO 

#n.B 
3/8 


BTJO 
B,A 
2/10 


BTJO 
#n.Rd 
4/10 


BTJO 
A.Pd 

3/11 


BTJO 
B.Pd 
3/10 


BTJO 
#n.Pd 
4/11 


XCHB 

A 
1/10 


XCHB 
TESTB 
1/10 


XCHB 
Rn 
2/8 


TRAP 

9 
1/14 


IDLE 
1/6 


7 


JNC 
ra 
2/5 


BTJZ 
Rs.A 
3/9 


BTJZ 

#n,A 
3/8 


BTJZ 
Rs.B 
3/9 


BTJZ 
Rs.Rd 

4/11 


BTJZ 
#n.B 
3/8 


BTJZ 
B.A 
2/10 


BTJZ 
#n.Rd 
4/10 


BTJZ 
A.Pd 
3/10 


BTJZ 
B.Pd 
3/10 


BTJZ 

#n.Pd 
4/11 


SWAP 

A 
1/11 


SWAP 
B 

1/11 


SWAP 
Rn 
2/9 


TRAP 
8 

1/14 


MOV 
#n.Pd 
3/10 


8 


JV 
ra 
2/5 


ADD 
Rs.A 
2/7 


ADD 

#n,A 
2/6 


ADD 
Rs.B 
2/7 


ADD 

Rs.Rd 

3/9 


ADD 

#n.B 
2/6 


ADD 
B.A 
1/8 


ADD 

#n.Rd 
3/8 


MOVW 

#16.Rd 

4/13 


MOVW 
Rs.Rd 
3/12 


MOVW 

#16(B).Rd 

4/15 


PUSH 
A 
1/9 


PUSH 
B 

1/9 


PUSH 
Rs 
2/7 


TRAP 

7 
1/14 


SETC 

1/7 


9 


JL 
ra 
2/5 


ADC 
Rs.A 
2/7 


ADC 

#n,A 
2/6 


ADC 
Rs.B 
2/7 


ADC 

Rs.Rd 

3/9 


ADC 

#n,B 
2/6 


ADC 
B,A 
1/8 


ADC 

#n.Rd 
3/8 


JMPL 
lab 
3/9 


JMPL 
@Rd 


JMPL 
lab(B) 
3/10 


POP 
A 

1/9 


POP 

B 

1/9 


POP 
Rd 
2/7 


TRAP 
6 

1/14 


RTS 

1/9 


A 


JLE 
ra 
2/5 


SUB 
Rs.A 
2/7 


SUB 

#n,A 
2/6 


SUB 
Rs.B 
2/7 


SUB 

Rs.Rd 

3/9 


SUB 

#n,B 
2/6 


SUB 
B,A 
1/8 


SUB 

#n.Rd 
3/8 


MOV 
lab.A 
3/10 


MOV 

@Rs.A 

2/9 


MOV 

lab(B).A 

3/12 


DJNZ 
A.ra 
2/10 


DJNZ 
B.ra 
2/10 


DJNZ 
Rn.ra 
3/8 


TRAP 

5 
1/14 


RTI 

1/12 


B 


JHS 
ra 
2/5 


SBB 
Rs.A 
2/7 


SBB 

#n,A 
2/6 


SBB 
Rs.B 
2/7 


SBB 

Rs.Rd 

3/9 


SBB 

#n,B 
2/6 


SBB 
B,A 
1/8 


SBB 

#n.Rd 
3/8 


MOV 
A.lab 
3/10 


MOV 

A.@Rd 

2/9 


MOV 

A.lab(B) 

3/12 


COM PL 
A 
1/8 


COMPL 

B 

1/8 


COMPL 

Rn 

2/10 


TRAP 

12 
1/14 


PUSH 
ST 

1/8 


C 


JNV 
ra 
2/5 


MPY 
Rs.A 
2/46 


MPY 
#n,A 
2/45 


MPY 
Rs.B 
2/46 


MPY 
Rs.Rd 
3/48 


MPY 

#n,B 
2/45 


MPY 
B.A 
1/47 


MPY 
#n.Rs 
3/47 


BR 
lab 

3/9 


BR 
@Rd 
2/8 


BR 
lab(B) 
3/11 


RR 
A 
1/8 


RR 
B 

1/8 


RR 
Rn 
2/6 


TRAP 
3 

1/14 


POP 
ST 

1/8 


D 


JGE 
ra 
2/5 


CMP 
Rs.A 
2/7 


CMP 
#n,A 
2/6 


CMP 
Rs.B 
2/7 


CMP 
Rs.Rd 
3/9 


CMP 
#n.B 
2/6 


CMP 
B.A 
1/8 


CMP 

#n,Rd 

3/8 


CMP 
lab.A 
3/11 


CMP 
@Rs.A 
2/10 


CMP 

lab(B).A 

3/13 


RRC 
A 
1/8 


RRC 
B 

1/8 


RRC 
Rn 
2/6 


TRAP 
2 

1/14 


LDSP 

1/7 


E 


JG 
ra 
2/5 


DAC 
Rs.A 
2/9 


DAC 

#n,A 
2/8 


DAC 
Rs.B 
2/9 


DAC 
Rs.Rd 
3/11 


DAC 

#n,B 
2/8 


DAC 
B.A 
1/10 


DAC 

#n.Rd 
3/10 


CALL 
lab 
3/13 


CALL 

@Rd 
2/12 


CALL 
lab(B) 
3/15 


RL 
A 
1/8 


RL 
B 

1/8 


RL 
Rn 
2/6 


TRAP 

1 
1/14 


STSP 
1/8 


F 


JLO 
ra 

2/5 


DSB 
Rs.A 
2/9 


DSB 

#n,A 
2/8 


DSB 
Rs.B 
2/9 


DSB 
Rs.Rd 
3/11 


DSB 

#n,B 
2/8 


DSB 

B,A 
1/10 


DSB 

#n.Rd 
3/10 


CALLR 
lab 
3/15 


CALLR 
@Rd 
2/14 


CALLR 
lab(B) 
3/17 


RLC 
A 
1/8 


RLC 
B 

1/8 


RLC 
Rn 
2/6 


TRAP 


1/14 


NOP 
1/7 



B 



NOTE ALL CONDITIONAL JUMPS (OPCODES 01 -OF), BTJO. AND BTJZ 

INSTRUCTIONS USE TWO ADDITIONAL CYCLES IF THE BRANCH IS TAKEN. 
THE BTJO AND BTJZ INSTRUCTIONS HAVE A RELATIVE ADDRESS AS THE 
LAST OPERAND. 



C-2 



Appendix C 



Second byte of two-byte instructions (F4xx): 



MOVW 
n(Rn) 
4/15 


DIV 

Rn,A 

3/14-63 


JMPL 
n(Rn) 
4/16 




MOV 

n(Rn),A 

4/17 




MOV 

A,n(Rn) 

4/16 




BR 
n(Rn) 
4/16 




CMP 
n(Rn) 
4/18 




CALL 
n(Rn) 
4/20 




CALLE F 
n(Rn) 
4/22 





ra - relative address 
Rn - Register 

Rs - Register containing source byte 
Rd - Register containing destination byte 
Ps - Peripheral register containing source byte 
Pd - Peripheral register containing destination byte 
Pn - Peripheral register 
n - Immediate 8-bit number 
#1 6 - Immediate 1 6-bit number 
lab - 16-bit label 



C-3 



Appendix C 



C-4 



D. Instruction/Opcode Cross Reference 

Table D-1 provides an instruction-to-opcode cross reference of all 73 mne- 
monics and 245 opcodes of the TMS370 instrruction set. The columns are 
grouped according to addressing modes (General and Extended). The "Other" 
column contains either the opcode(s) of instructions that do not qualify for 
the General or Extended catagories, or a notation to be referenced at the bot- 
tom of the table for more information on a particular instruction. 



D-1 



Appendix D 



Table D-1 . TMS370 Family Instruction/Opcode Set 





GENERAL 


EXTENDED 


Other 




A 


B 


Rn 


A,B 


B,A 


Rn. 
A 


#n, 
A 


Rn, 
B 


#n, 
B 


Rn, 
Rn 


#n, 
Rn 


A, 
Rn 


B, 
Rn 


A, 
Pn 


Pn, 
A 


B, 
Pn 


Pn, 
B 


#n, 
Pn 


t 


t 


§ 


V 


» 


ADC 










69 


19 


29 


39 


59 


49 


79 


























ADD 










68 


18 


28 


38 


58 


48 


78 


























AND 










63 


13 


23 


33 


53 


43 


73 






83 




93 




A3 












BR 






































8C 


AC 


9C 


EC 




BTJO 










66 


16 


26 


36 


56 


46 


76 






86 




A6 




96 












BTJZ 










67 


17 


27 


37 


57 


47 


77 






87 




A7 




97 












CALL 






































8E 


9E 


AE 


EE 




CALLR 






































8F 


9F 


AF 


EF 




CLR 


85 


C5 


D5 










































CLRC 














































BO 


CMP 










6D 


ID 


2D 


3D 


5D 


4D 


7D 
















8D 


AD 


9D 


ED 


F3 


CMPBIT 














































75,A5 


COM PL 


BB 


CB 


DB 










































DAC 










6E 


IE 


2E 


3E 


5E 


4E 


7E 


























DEC 


B2 


C2 


D2 










































DINT 














































FOOO 


DIV 














































F4 F8 


DJNZ 


BA 


CA 


DA 










































DSB 










6F 


IF 


2F 


3F 


5F 


4F 


7F 


























EINT 














































FOOC 


EINTH 














































F0 04 


EINTL 














































F0 08 


IDLE 














































F6 


INC 


B3 


C3 


D3 










































INV 


B4 


C4 


D4 










































JBITO 














































77,A7 


JBIT1 














































76,A6 


JMP 














































00 


JMPL 






































89 


A9 


99 


E9 




JC 














































03 


JEQ/JZ 














































02 


JG 














































OE 


JGE 














































OD 


JHS 














































OB 


JL 














































09 


JLE 














































OA 


JLO 














































OF 


JN 














































01 


JNC 














































07 


JNE/JNZ 














































06 


JNV 














































OC 


JP 














































04 


JPZ 














































05 


JV 














































08 


LDSP 














































FD 



t Direct {(label) -♦ (A)} 
* Indexed {(label + (B)) -♦ (A)} 
S Indirect {(Rn-1: Rn) -+ (A)} 

^ Offset Indirect (dual opcode Instruction, the first of which is F4) {(n + (Rn - 1: Rn)) -♦ (A)} 
» Single opcode instructions that do not qualify as a General or Extended addressing mode, and dual opcode in- 
structions that do not qualify as an Offset Indirect addressing mode. 



D-2 



Appendix D 



Table D-1. TI\/IS370 Family Instruction/Opcode Set (Concluded) 





GENERAL 


EXTENDED 


Other 




A 


B 


Rn 


A,B 


B,A 


Rn, 
A 


A 


Rn, 
B 


B 


Rn, 
Rn 


Rn 


A, 
Rn 


B, 
Rn 


A, 
Pn 


Pn, 
A 


B, 
Pn 


Pn, 
B 


#n, 
Pn 


t 


* 


§ 


TT 


» 


LOST 














































FO 


MOV 








CO 


62 


12 


22 


32 


52 


42 


72 


DO 


D1 


21 


80 


51 


91 


F7 


8B 


AA 


9A 


EA 


II 


MOVW 






































88 


A8 


98 


E8 




MPY 










6C 


1C 


2C 


3C 


5C 


4C 


7C 


























NOP 














































FF 


OR 










64 


14 


24 


34 


54 


44 


74 






84 




94 




A4 












POP 


B9 


C9 


D9 








































FC 


PUSH 


B8 


C8 


D8 








































FB 


RL 


BE 


CE 


DE 










































RLC 


BF 


CF 


DF 










































RR 


BC 


CO 


DC 










































RRC 


BD 


CD 


DD 










































RTI 














































FA 


RTS 














































F9 


SBB 










SB 


IB 


2B 


3B 


5B 


4B 


7B 


























SBITO 


















































SBIT1 














































]■ 


SETC 














































F8 


STSP 














































FE 


SUB 










6A 


1A 


2A 


3A 


5A 


4A 


7A 


























SWAP 


B7 


C7 


D7 










































TRAP 














































** 


TST 


BO 


C6 












































XCHB 


B6 


C6 


D6 










































XOR 










65 


15 


25 


35 


55 


45 


75 






85 




95 




A5 













t Direct 

t Indexed 

5 Indirect 

^ Offset Indirect (dual opcode instruction, tfie first of whicfi is F4) 

» Unless otherwise indicated, includes single opcode instructions that 
do not qualify as a General or Extended addressing mode, and dual 
opcode instructions that do not qualify as an Offset Indirect 
addressing mode. 

II The MOV instruction also includes the following options 
and their opcodes: Rn.Pn {71}; Pn.Rn {A2}; A,label(B) {AS}; 
A,n(SP) {F2}; A,n(Rn) {F4 EB}; label,A {8A}; n(SP),A {F1} 

j The SBITO instruction consists of the following options 
and their opcodes; Rname {73}; Pname {A3} 

J" The SBIT1 instruction consists of the following options 
and their opcodes; Rname {74}; Pname {A4} 

" The TRAP instruction consists of 1 5 options using operands 
through 15 with opcodes EF through EO respectively. 



D-3 



Appendix D 



D-4 



E. Glossary 



This appendix provides definitions of terms and concepts unique to the 
TMS370 family of devices. Other common terms are included if the use of 
those terms varies from generally accepted usage. 

absolute address: An addressing mode in which code or operands produce 
the actual address. 

A/D pins: The 10 pins that connect the A/D module to the external world; 
includes ANO-7, Vssa- and Vqcs- 

addressing mode: The method by which an instruction calculates the location of 
its required data. 

AN0-AN7 pins: Eight analog input channels to the A/D converter or digital inputs; 
seven of which can be configured as the Voltage reference channel. 

analog-to-digital (A/D) converter: The TMS370 A/D Converter is an 8-bit 
successive-approximation converter with internal sample-and-hold circuitry. 

assembly language: A symbolic language that describes the binary machine code 
in a more readable form. Each of the 73 unique instructions of the TMS370 family converts 
to one machine operation. 

Asynchronous communications mode: An serial communications format that 
needs no synchronizing clock. This format consists of a start bit followed by data bits, 
an optional parity bit and ends with a stop bit. This format is commonly used with 
RS-232-C communications and PC serial ports. 

BCD: Binary coded decimal; each 4 bit nibble expresses a digit from 0-9, and usually 
packed two digits to a byte giving a range of 0-99. 

baud rates: The communication speed for serial ports; equivalent to bits per second. 

Capture register: A Timer 1 or Timer 2 register which is loaded with the 16-bit 
counter value on the occurrence of an external input transition. Either edge of the external 
input can be configured to trigger the capture. 

chip select: For some blocks of the TMS370 memory map, the most-significant bits 
of the address are pre-decoded to activate chip-select signals. These chip-select signals 
allow the TMS370 to access external addresses with a minimum of external logic and to 
perform memory bank selection under software control. 

Compare register: The compare register, in the Timer 1 or Timer 2 module, contains 
a value which is compared to the counter value. The compare function triggers when the 
counter matches the contents of the compare register. 

constant: A value which does not change during execution. 

CPU: The TMS370 CPU is an 8-bit register oriented processor with Status register. 
Program Counter register, and Stack Pointer. The CPU uses the Register File, accessed in 
one bus cycle, as working registers. 

edge detection: Edge detection circuitry senses an active pulse transition on a given 
timer input and provides appropriate output transitions to the rest of the module. The 
active transition can be configured to be low- to- high or high-to-low. 

EEPROM: Electrically Erasable Programmable Read Only Memory; has the capability 
to be programmed and erased under direct program control 

Extended Addressing mode: An addressing mode with an 16-bit range. 

General Addressing mode: An addressing mode with an 8-bit range. 



E-1 



Appendix E 



Halt mode: The Halt mode reduces operating power by stopping the internal clock 
which stops processing in all the modules. This is the lowest-power mode in which all 
Register contents are preserved. 

IDLE Instruction: The IDLE instruction causes the device to enter one of three 
modes; Idle, Halt, or Standby. 

Idle mode: In the Idle mode, the CPU stops processing and waits for the next inter- 
rupt. 

immediate operand: An operand whose actual constant value is specified in the 
instruction and placed after the opcode in the machine code. 

Index: An 8-bit unsigned number added to a base address to give a final address. 

Instruction: The basic unit of programming which causes the execution of one op- 
eration; consisting of an opcode and operands along with optional labels 

interrupts: A signal input to the CPU to stop the flow of a program and force the CPU 
to execute instructions at an address corresponding to the source of the interrupt. When 
the interrupt is finished, the CPU resumes execution at the point where it was interrupted. 

INT1 pin: A pin connected to external devices to allow them to interrupt the CPU; 
INT1 can be software configured as a non-maskable interrupt. 

INT2 and INT3 pins: Pins connected to external devices to allow them to interrupt 
the CPU. 

Isosynchronous Communications mode: An SCI mode in which data trans- 
mission is synchronized by a clock signal (SCICLK) common to both the sender and re- 
ceiver. The format is identical to the asynchronous mode and consists of a start bit, data 
bits, an optional parity bit and a stop bit. 

machine code: The actual bytes read by the CPU during an instruction execution 
usually read by a programmer as hexadecimal bytes. 

MC pin: Mode Control pin, the voltage on this pin during Reset determines the oper- 
ating mode of the TMS370 device; 1 2 volts on the MC pin after reset places the processor 
in the Write Protection Override mode (WPO). 

memory map: A description of the addresses of the various sections and features of 
the TMS370 processor. The map depends on the operating mode. 

Microcomputer mode w/external expansion: An operating mode in which 
the address, control and data buses extend off-chip to access external memory or periph- 
erals. 

Microcomputer single-chip mode: An operating mode in which the device 
uses only on-chip memory. 

Microprocessor mode w/ internal program memory: An operating mode 
in which the on-chip program memory is available to the processor. 

Microprocessor mode w/o internal program memory: An operating 
mode in which the on-chip program memory is not available to the processor; thus, the 
processor must have external memory. 

pP/jjC Mode bit: Microprocessor / Microcomputer Mode bit; determines whether 
the device initializes into one of the microcomputer or a microprocessor operating mode. 

mnemonic: A symbol chosen to aid human memory; commonly used to refer to the 
symbol representing the opcode part of an assembly language instruction. 

multiprocessor communications: A SCI format option which enables one 
processor to efficiently send blocks of data to other processors on the same serial link. 

nested Interrupts: The ability of an interrupt to suspend the service routine of a 
prior interrupt; implemented in TMS370 devices by executing an interrupt service routine 



E-2 



Appendix E 



which uses the HINT, EINTL or El NTH instructions to set the global Interrupt Enable bits 
in the status register. 

non-maskable interrupt (NMI): activation of a NMI always causes the proces- 
sor to execute the NMI routine. On TMS370 devices; INT1 can be configured as an NMI. 

offset: A signed value that is added to the base operand to give the final address 

opcode: Operation code; the first byte of the machine code which describes to the 
CPU the type of operation and combination of operands. Some TMS370 instructions use 
16-bit opcodes. 

operand: The part of an instruction which tells the programmer where the CPU will 
fetch or store data. 

output compare: See Compare register. 

Peripheral File (PF): The 256 bytes of memory, starting at lOOOh, containing the 
registers which control the on-board peripherals and system configuration. 

peripheral file frame: A set of 16 contiguous peripheral file registers, usually re- 
lated by function. 

po\A/erdown mode: One of two power reduction modes; see Halt mode and 
Standby mode. 

PPM: Pulse Position Modulation; a serial signal in which the information is contained 
in the frequency of a signal with a constant pulse width. A TMS370 device can output a 
PPM signal with a constant duty cycle without any program intervention using the Timer 
compare features. 

prescaler: A circuit which slows the rate of a clocking source to the counter. On 
TMS370 devices, the prescaler can slow the clocking source by a factor of 4, 16, 64, or 
256. 

privilege mode: A mode immediately following reset in which the program can alter 
the privileged registers. Once the priviledged mode is disabled, these registers cannot be 
changed until another reset. This mode does not affect the EEPROM or the Watchdog 
registers. 

prototyping device: A device used before masked ROM devices are available 
which have identical functions, pinout, size and timings. Programmable memory such as 
EEPROM or EPROM is used in place of the masked ROM. 

pulse accumulation: A Timer 1 mode which keeps a cumulative count of SYSCLK 
pulses gated by the T1 EVT signal. 

PWM: Pulse Width Modulation; A serial signal in which the information is contained 
in the width of a pulse of a constant frequency signal. A TMS370 device can output a 
PWM signal with a constant duty cycle without any program intervention using the Timer 
compare features. 

ratiometric conversion: An Analog-to- Digital conversion in which the conver- 
sion value is a ratio of the Vref source to the analog input. As Vref 's increased, the 
input voltage needed to give a certain conversion value changes; but all conversion values 
keep the same relationship to Vr^p. 

Register File (RF): The first 256 bytes of memory which can be accessed by the 
majority of the instrucions. 

relative: Operands and code which produce an absolute address at some distance 
from the current location. 

RESET pin: A low level on this pin starts hardware initialization and ensures an or- 
derly software startup. If the MC pin is low when the RESET signal returns high, then the 
processor enters the Microcomputer mode. If the MC pin is high when the RESET signal 
returns high, then it enters the Microprocessor mode. 



E-3 



Appendix E 



Serial Communications Interfacis (SCI): The SCI module is a built-in serial 
interface which can be programmed to be asynchronous or isosynchronous. Many timing, 
data format, and protocol factors are programmable and controlled by the SCI module in 
operation. 

SCICLK pin: Serial Communications Interface Clock pin; used as a synchronizing 
clock input or output in the Isoynchronous mode, or as a general purpose I/O pin. 

Serial Peripheral Interface (SPI): The SPI module is a built-in serial interface 
which facilitates communication between networked master and slave CPUs. As in the 
SCI, the SPI is setup by software and from then on, the CPU takes no part in timing, data 
format, or protocol. 

signed integer: a number system used to express positive and negative integers. 

SPICLK pin: Serial Peripheral Interface Clock. If the SPI is in the Master mode, this 
pin provides the serial clock for the entire serial communications network. If the SPI is in 
the Slave mode, this pin is the serial clock input. 

SPISIMO pin; Serial Peripheral Interface Slave In, Master Out; In the master mode, 
data is output on the SPISIMO pin on the first SPICLK edge and latched from the SPI- 
SOMI pin on the opposite edge of SPICLK. In the slave mode, data is output on the 
SPISOMI pin on the first SPICLK edge and latched from the SPISIMO pin on the opposite 
edge of SPICLK. 

SPISOMI pin: Serial Peripheral Interface Slave Out, Master In; see SPISIMO. 

Stack: That part of the Register File used as last-in, first-out memory for temporary 
variable storage; used during interrupts and calls, to store the current program status. The 
area occupied by the stack is determined by the Stack Pointer and the application pro- 
gram. 

Stack Pointer (SP): An 8-bit CPU register that points to the last entry or top of the 
stack. The SP is automatically incremented before data is pushed onto the stack and de- 
cremented after data is popped from the stack. 

Standby mode: A power reduction mode in which the CPU stops processing, but 
the on-chip oscillator remains active. Timers remain active and can cause the CPU to exit 
the standby mode. 

Status register (ST): A CPU register which monitors the operation of the in- 
structions and contains the global interrupt enable bits. 

TRAP: Trap-to-subroutine. An assembly language instruction which is a one-byte su- 
broutine call. An operand <n> is a trap number that identifies a location in the trap vector 
table, addresses 07FC0h to 07FDFh in memory, containing the address of the subroutine. 

T2IC1/CR pin: Timer 2 Input Capture 1 / Counter Reset pin. A Timer 2 module pin 
which is an input to the counter reset, input capture, or PWM circuit. 

T2IC2/PWM pin: Timer 2 Input Capture 2 / Pulse Width Modulation pin. A Timer 
2 module pin which is the Pulse Width Modulation output or a second input capture. 

unsigned integer: a number system used to express positive integers. 

WAIT pin: Allows an external device to cause the processor to wait an indefinite 
number of clock cycles. When the wait line is released, the processor resynchronizes with 
the rising edge of the clock out signal and continues with the program. 

wait states, automatic: extra clock cycles inserted automatically on every external 
memory access to accomodate peripherals or expansion memory with slower access time 
than the TMS370 processor. These Wait states are governed by two control bits: PF 
AUTO WAIT and AUTOWAIT DISABLE. 

watchdog timer: A Timer 1 module option which can be programmed to generate 
an interrupt when it times out. This function provides a hardware monitor over the soft- 
ware to prevent a "lost" program. If not needed as a watchdog, this timer can be used as 
a general purpose timer. 



E-4 



Appendix E 



Write Protect Override (WPO): The only mode in which a TMS370 device can 
modify the on-board EEPROM. The WPO mode is entered when external circuitry applies 
12 volts to the MC pin after the device has been Reset into one of its normal operating 
modes. 



E-5 



Appendix E 



E-6 



Index 



A/D 1-6 
ADC 

Add with Carry Instruction 1 2-1 9, 1 2-30 
ADD 

Add Instruction 1 2-19, 1 2-31 
addition instructions 1 2-30, 1 2-31 , 1 2-44, 

12-54, 12-55 
Additional Addressing Modes 12-17 
Addressing Modes 

Additional 12-17 

Direct 12-10 

Extended Addressing Modes 12-10 

General Addressing Modes 12-4 

Immediate 12-7 

Indexed 12-12 

Indirect 12-14 

Offset Indirect 12-15 

Peripheral File 12-6 

Program Counter Relative 12-8 

Single Register 12-5 

Stack Pointer Relative 12-9 
Analog-to-Digital (A/D) Converter 

A/D Converter Ready (AD READY) 11-13 

A/D Interrupt Enable bit (AD INT 
ENA) 11-13 

A/D Interrupt Flag (AD INT FLAG) 11-13 

A/D Interrupt Priority Select (AD 
PRIORITY) 11-15 

AD INT ENA bit 11-6 

AD INT FLAG 11-6 

AD PRIORITY bit 11-6 

analog control register (ADCTL) 11-11 

analog conversion data register 
(AD DATA) 11-13 

Analog Input Channel Select Bits (AD IN- 
PUT SELECTO-2) 11-11 

analog interrupt priority register 
(ADPRI) 11-15 

analog port E data input register 
(ADIN) 11-14 

analog port E input enable register 
(ADENA) 11-14 

analog status and interrupt register (ADS- 
TAT) 11-13 

block diagram 11-3 

control registers 1 1 -4 

conversion process 1 1 -5 

CONVERT START bit 11-7 

Convert Start bit (CONVERT 
START) 11-12 



DATA7-DATA0 bits 11-13 

Emulator Suspend Enable (AD 
ESPEN) 11-15 

example program 11-8 

I/O pins 11-5 

interrupts 1 1 -6 

memory map 1 1 -4 

operation 11-5 

overview 1 1 -2 

physical description 11-2 

PORT E DATA AN 7-PORT E DATA AN 
bits 11-14 

PORT E INPUT ENA 7-PORT E INPUT ENA 
11-14 

programming considerations 11-7 

ratiometric conversion 11-5 

Reference Voltage bits (REF VOLT 
SELECTO-2) 11-11 

SAMPLE START bit 11-7 

Sample Start bit (SAMPLE START) 11-12 

sampling time 11 -5 
analog-to-digital converter 1-6 
AND 

Logical AND Instruction 1 2-19, 1 2-32 
applicable documents 1-8 
applications 1 -3 
architecture overview 1 -4 
Array Program (AP) bit 6-4, 6-10, 6-1 1 
assembly language 12-1 
Assembly Language Instructions 

ADC 12-19 

ADD 12-19 

AND 12-19 

BR 12-19 

BTJO 12-19 

BTJZ 12-19 

CALL 12-20 

CALLR 12-20 

CLR 12-20 

CLRC 12-20 

CMP 12-20 

CMPBIT 12-20 

CMPL 12-20 

DAC 12-20 

DEC 12-20 

DINT 12-20,12-46 

DIV 12-21,12-47 

DJNZ 12-21,12-48 

DSB 12-21,12-49 

EINT 12-21,12-50 

EINTH 12-21,12-51 

EINTL 12-21,12-52 

IDLE 4-4,4-5,12-21 



lndex-1 



Index 



INC 12-21,12-54 

INCW 12-21,12-55 

INV 12-21 

J<cnd> 12-61 

JBITO 12-21,12-57 

JBIT1 12-21,12-58 

JMP 12-21,12-59 

JMPL 12-22,12-60 

LDSP 12-22, 12-63 

LOST 3-5,12-22,12-64 

MOV 12-23,12-65 

MOVW 12-23,12-66 

MPY 12-23,12-67 

NOP 12-23 

OR 12-23 

POP 12-24,12-70 

PUSH 12-24,12-71 

RL 12-24,12-72 

RLC 12-24,12-73 

RR 12-24,12-74 

RRC 12-24,12-75 

RTI 5-2,12-24,12-76 

RTS 12-24,12-77 

SBB 12-24,12-78 

SBITO 12-24,12-79 

SBIT1 12-24,12-80 

SETC 12-24,12-81 

STSP 12-25,12-82 

SUB 12-25,12-83 

SWAP 12-25 

TRAP 12-85 

TRAP n 12-25 

TST 12-25,12-86 

XCHB 12-25,12-87 

XOR 12-25 
Assembly Language Tools 14-2 
asynchronous SCI 1-6 

Automatic Wait State Disable (AUTOWAIT DIS- 
ABLE) bit 4-8 
automatic wait states 4-3 
AUTOWAIT DISABLE bit 4-3 



B 



BR 

Branch Instruction 12-19,12-33 
BTJO 

Bit Test and Jump If One 
Instruction 12-19, 12-34 
BTJZ 

Bit Test and Jump If Zero 
Instruction 12-19,12-35 
BUSY bit 6-4,6-7,6-10 



C (carry) bit 12-81 
CALL 

Call Instruction 12-20, 12-36 
CALLR 

Call Relative Instruction 12-37 

CALLR Instruction 12-20 
capture 7-3 
Carry (C) bit 3-4,12-39 
character sets 

See Appendix B 
Chip Select Eighth 1 (CSE) signal 4-13 
Chip Select Eighth 2 (CSE2) signal 4-14 
Chip Select Half 1 (CSH1) signal 4-13 
Chip Select Half 2 (CSH2) signal 4-13 
Chip Select Half 3 (CSH3) signal 4-13 
Chip Select Peripheral File (CSPF) 4-14 
clear 1 -8 

Clock Output (CLKOUT) signal 4-14 
CLR 

Clear Instruction 12-20, 12-38 
CLRC 

Clear the Carry Bit Instruction 1 2-20, 
12-39 
CMOS devices 

See Section 2 and Section 4 
CMP 

Compare Instruction 12-20,12-40 
CMPBIT 

Complement Bit Instruction 12-20, 12-42 
CMPL 

Two's Complement Instruction 12-20 
COLD START bit 4-8 
compare instructions 12-40, 12-42, 12-43 
compare register 7-15 

compare register 7-15 

interrupt flags 7-16 

interrupts 7-16 

T1C2 INT FLAG 7-15 

T1 EDGE INT FLAG 7-15 

T1PWM 7-15 
COMPL 

Two"s Complement Instruction 12-43 
condition flags (C, N, Z, V) 3-5 
conditional jumps 12-61 
counter clock source 7-24 
CPU 1-5 
CPU registers 3-3 



D 



DAC 

Decimal Add with Carry Instruction 1 2-20, 
12-44 
data EEPROM 1-5,3-11,6-2 
data EEPROM programming 6-5 
data memory 1 -4 
DEC 

Decrement Instruction 12-20, 12-45 
DEECTL register 6-2, 6-4 



lndex-2 



Index 



development support 14-1 

ordering information 16-13 
device comparison 2-2 
digital I/O configuration 4-11 
digital port control registers 4-1 1 
digital ports set-up example 4-15 
DINT 

Disable Interrupts Instruction 12-20, 
12-46 
Direct Addressing modes 12-10 
DiV 

Divide Instruction 12-47 

Integer Divide Instruction 12-21 
DIV instruction 12-47 
DJNZ 

Decrement Register and Jump If Not Zero 
Instruction 12-48 

Decrement Relative and Jump If Not Zero 
Instruction 12-21 
DSB 

Decimal Subtract with Borrow 
Instruction 12-21,12-49 



family devices summary 2-1 
frame, peripheral file 3-9 
function A expansion signals 3-17 
function B expansion signals 3-18 



General Addressing Modes 12-4 
global interrupt enable bits (IE1 and IE2) 



5-2 



H 



halt mode 4-4, 4-6 

HALT/ STANDBY bit 4-5, 4- 

hardware interrupts 5-4 



10 



7-13 
7-13, 7-14 



6-6 



edge detection, timer 1 7-13 
compare register 7-14 
counter reset 7-15 
counter reset sources 7-14 
general purpose counter 7-14 
T1 EDGE DETENA 7-14 
T1 OVRFLINT FLAG 7-14 
T1CR0UTENA 7-13 
T1CRRSTENA 7-13 
T1C1 INT FLAG 7-14 
T1 EDGE DETENA 7-13 
T1EDGE INT FLAG 
T1EDGE POLARITY 
T1PWM 7-14 

EEPROM 1-5 

EEPROM modules 6-1 

EEPROM programming 

EEPROM, data 3-11 

EEPROM, program 3-12 

HINT 

Enable Interrupts Instruction 

EINTH 

EINT High Priority Instruction 
Enable High Level Interrupts 
Instruction 12-51 

EINTL 

EINTL Low Priority Instruction 
Enable Low Level Interrupts 
Instruction 12-52 

Execute (EXE) bit 6-4,6-10 

Extended Addressing Modes 12-10 

External Data Strobe (EDS) signal 4-13 

external interrupt control registers 5-5 

external interrupt pins (INT1, INT2, INT3) 

external interrupts 5-5 



12-21, 12-50 
12-21 



12-21 



5-5 



I/O ports 1-5 
IDLE 

Idle Until Interrupt Instruction 12-21, 
12-53 
IDLE instruction 4-4,4-5 
idle modes 4-4 

Immediate Addressing mode 12-7 
Implied 12-4 
INC 

Increment Instruction 12-21, 12-54 
INCW 

Increment Word Instruction 1 2-21 , 1 2-55 
Indexed Addressing modes 12-12 
Indirect Addressing modes 12-14 
INT DATA DIR bit 5-6 
INT DATA OUT bit 5-6 
INT ENABLE bit 5-5 
INT FLAG bit 5-5 
INT PIN DATA bit 5-5 
INT POLARITY bit 5-5 
INT PRIORITY bit 5-5 
interrupt context switch 5-3 
interrupt control registers 5-5 
interrupt enable bits (IE1 and IE2) 5-2 
interrupt priority levels 5-2 
interrupt routines, nested 5-11 
interrupt vector addresses 5-4 
Interrupt 1 Control Register (INT1) 5-8 
Interrupt 1 Enable (INT1 ENABLE) bit 5-8 
Interrupt 1 Flag (INT1 FLAG) bit 5-8 
Interrupt 1 Pin Data (INT1 PIN DATA) bit 5-8 
Interrupt 1 Polarity (INT1 POLARITY) bit 5-8 
Interrupt 1 priority (INT1 PRIORITY) bit 5-8 



lndex-3 



Index 



Interrupt 1, Non-Maskable Interrupt (INTI 

NMI)bit 4-9 
Interrupt 2 Control Register (INT2) 5-9 
Interrupt 2 Data Direction (INT2 DATA DIR) 

bit 5-9 
Interrupt 2 Data Out (INT2 DATA OUT) bit 
Interrupt 2 Enable (INT2 ENABLE) bit 5-9 
Interrupt 2 Flag (Interrupt 2 Flag) 5-9 
Interrupt 2 Pin Data {INT2 PIN DATA) 5-9 
Interrupt 2 Polarity (INT2 POLARITY) bit 5-9 
Interrupt 2 Priority (INT2 PRIORITY) 5-9 
Interrupt 3 Control Register (INT3) 5-10 
Interrupt 3 Data Direction (INT3 DATA DIR) 

bit 5-10 
Interrupt 3 Data Out (INT3 DATA OUT) 

bit 5-10 
Interrupt 3 Enable (INT3 ENABLE) bit 5 
Interrupt 3 Flag (INT3 FLAG) 5-10 
Interrupt 3 Pin Data (INT3 PIN DATA) bit 
Interrupt 3 Polarity (I NTS POLARITY) bit 
Interrupt 3 priorityJINT3 PRIORITY) bit 
interrupts 5-2 



5-9 



-10 

5-10 
5-10 
5-10 



DINT instruction 


12-46 




El NT instruction 


12-50 




EINTH instruction 


1 12-51 




EINTL instruction 


12-52 




RTI instruction 


12-76 




interrupts, external 5-5 




interrupts, hardware 


5-4 




INV 






Invert Instruction 


12-21, 


12-56 


isosynchronous SCI 


1-6,9-4, 


9-5,9-10 



J<cnd> 

Jump on Condition Instruction 12-61 

JBITO 

Conditional Jump Instruction 12-21 
Jump If Bit = Instruction 12-57 

JBIT1 

Condition Jump Instruction 12-21 
Jump If Bit = 1 Instruction 12-58 

JC 12-22 

JG 12-22 

JGE 12-22 

JHS 12-22 

JL 12-22 

JLE 12-22 

JLO 12-22 

JMP 

Jump Unconditional Instruction 12-21, 
12-59 

JMPL 

Jump Long Instruction 12-60 

Jump Unconditional Instruction 12-22 

JN 12-22 

JNC 12-22 

JNV 12-22 



JNZ 12-22 

JP 12-22 

JPZ 12-22 

jump instructions 1 2-34, 1 2-35, 1 2-48, 1 2-57, 

12-58, 12-59, 12-60. 12-61 
JV 12-22 
JZ 12-22 



LDSP 

Load Stack Pointer Instruction 12-22, 
12-63 
LDST 

Load Status Register Instruction 12-22, 
12-64 
LDST instruction 3-5 
Level 1 Interrupt Enable (IE1) bit 3-4 
level 1 interrupts 5-2 
Level 2 Interrupt Enable (IE2) bit 3-4 
level 2 interrupts 5-2 . 
Linker 14-3 



M 



3-14 



MC pin 3-13 
mechanical data 16-5 
MEMORY DISABLE bit 3-20,4-8 
memory expansion 3-16 
memory maps 3-6, 3-22 
memory mode summary 3-22 
memory operating modes 3-13 
microcomputer mode 4-16 
microcomputer mode w/external 

expansion 3-16 
microcomputer single-chip mode 
microprocessor mode 4-16 
microprocessor mode w/internal program 

memory 3-20 
microprocessor mode w/o internal 

memory 3-19 
Microprocessor/Microcomputer Mode (pP/pC 

MODE) bit 4-7 
Mode Control Pin Data (MC PIN DATA) bit 4-7 
Mode Control Pin Write Protect Override (MC 

PIN WPO) status bit 4-7 
MOV 

Move Instruction 12-23,12-65 
move instructions 12-65,12-66 
MOVW 

Move Word Instruction 1 2-23, 1 2-66 
MPY 

Multiply Instruction 1 2-23, 1 2-67 
multiple interrupt servicing 5-1 1 
multiplication instructions 12-67 



lndex-4 



Index 



N 



Negative (N) bit 3-4 

nested interrupt routines 5-11 

non-maskable interrupt 5-5 

NOP 

No Operation Instruction 
No-Operation Instruction 



12-68 
12-23 



o 



offset calculation 12-8 

Offset Indirect Addressing modes 12-15 

Opcode Fetch (OCF) signal 4-14 

opcode map C-1 

operating modes, memory 3-13 

OR 

Logical OR Instruction 12-23,12-69 
OSC FLT DISABLE bit 4-3 
OSC FLT FLAG 4-3 
OSC FLT RST ENA 4-3 
OSC POWER bit 4-6 
oscillator fault 4-3 
Oscillator Fault Disable (OSC FLT DISABLE) 

bit 4-9 
Oscillator Fault Flag (OSC FLT FLAG) 4-7 
Oscillator Fault Reset Enable (OSC FLT RST 

ENA) 4-9 
Oscillator Power (OSC POWER) bit 4-8 
Overflow (V) bit 3-4 
overview, architecture 1 -4 



packaging 16-5 

PCH 3-5 

PCL 3-5 

Peripheral Addressing mode 12-6 

peripheral file (PF) 3-9 

peripheral file address map 3-9 

Peripheral File Automatic Wait (PF AUTO WAIT) 

bit 4-7 
PF AUTO WAIT bit 4-3 
pin descriptions, TMS370Cx10 2-6 
pin descriptions, TMS370Cx50 2-8 
Pins 

A/D pins 11-5 

AN0-AN7 11-5 

INT1 5-5 

INT2 5-5 

INT3 5-5 

MC 3-13 

RESET 3-13,5-12 

SCICLK 9-8, 9-9 

SPISIMO 10-7 

SPISOMI 10-7 

T2iC1/CR 8-7,8-9,8-12 

T2IC2/PWM 8-7,8-9,8-10 



WAIT 4-3 
POP 

POP from Stack Instruction 1 2-24, 1 2-70 
port D 3-16 
powerdown mode 4-4 
Powerdown/ldle (PWRDWN/IDLE) bit 4-10 
prescaler, timer 1 7-1 1 

clock sources 7-11 
PRIVILEGE DISABLE bit 4-2 
privilege mode 4-2 
Privilege Mode Disable (PRIVILEGE DISABLE) 

bit 4-9 
Program Counter (PC) 3-5, 5-2 
Program Counter Relative Addressing 

mode 12-8 
program EEPROM 1-5,3-12 
Program EEPROM Control Register 

(PEECTL) 3-12,6-10 
program EEPROM module 6-9 
Program EEPROM write protection 6-12 
program memory 1-4,3-11 
program ROM 3-12 
programmer 14-17 
programming the data EEPROM 6-5 
programming the program EEPROM 6-11 
prototyping 16-2 

Prototyping/Preproduction Devices 14-19 
PUSH 

Push on Stack Instruction 12-24, 12-71 
PWRDWN/IDLE bit 4-5 



ratiometric conversion 1 1 -5 

Read or Write operation (R/W) signal 

reference documents 1 -8 

Register A,B 12-86 

Register Addressing mode 12-5 

Register B 12-87 

register file 1-4,1-5,3-2 

Register File (RF) 3-7 

Registers 

A/D control registers 11-10 

ADCTL 11-11 

AD DATA 11-13 

ADENA 11-14 

ADIN 11-14 

ADPRI 11-15 

ADSTAT 11-13 

BAUD MSB, BAUD LSB 9-24 

DEECTL 6-2, 6-4 

external interrupt control 5-5 

INT1 5-8 

INT2 5-9 

INT3 5-10 

PC 3-5 

PEECTL 3-12,6-10 
9-28 
9-26 
4-2, 4-7 
4-2, 4-8 



4-14 



RXBUF 
RXCTL 
SCCRO 
SCCRl 
SCCR2 



4-2, 4-9 



lndex-5 



Index 



SCICCR 9-20 

SCICTL 9-22 

SCIPCl 9-29 

SCIPC2 9-30 

SCIPRI 9-31 

SP 3-3 

SPIBUF 10-7,10-14 

SPICCR 10-7,10-11 

SPICTL 10-13 

SPIDAT 10-7,10-14 

SPIPC1 10-15 

SPIPC2 10-16 

SPIPRI 10-17 

ST 3-4 

TXBUF 9-15,9-28 

TXCTL 9-25 

TXSHF 9-15 

T1 CTL1 7-24 

T1 CTL2 7-25 

T1 CTL3 7-27 

T1CTL4 7-29 

T1PC1 7-31 

T1PC2 7-32 

T1PRI 7-33 

T2CTL1 8-16 

T2CTL2 8-17 

T2CTL3 8-19 

T2PC1 8-21 

T2PC2 8-22 

T2PRI 8-23 

WPR 6-2, 6-3 

WUT 9-15 
register-to-register architecture 1 -4 
reset circuit, typical 5-14 
RESET pin 3-13 
reset sequence 5-13 
reset sources 5-12 
reset vectors 3-1 1 

reset, control-bit states following 5-1 3 
Return-From-lnterrupt (RTI) instruction 5-2 
RL 

Rotate Left Instruction 12-24, 12-72 
RLC 

Rotate Left Through Carry 
Instruction 12-24,12-73 
ROM, program 3-12 

rotate instructions 1 2-72, 1 2-73, 1 2-74, 1 2-75 
RR 

Rotate Right Instruction 12-24, 12-74 
RRC 

Rotate Right Through Carry 
Instruction 12-24,12-75 
RTI 

Return From Interrupt Instruction 12-24, 
12-76 
RTS 

Return From Subroutine Instruction 12-24, 
12-77 



SBB 

Subtract with Borrow Instruction 12-24, 

12-78 
SBITO 

Set Bit to Instruction 1 2-24, 1 2-79 
SBIT1 

Set Bit to 1 Instruction 12-24,12-80 
Serial Communications Interface (SCI) 1-6 
address bit format 9-15 
address bit mode 9-13, 9-15 
ADDRESS/IDLE WUP bit 9-13 
ASYNC/ISOSYNC bit 9-9 
asynchronous format 9-9 
asynchronous mode 9-5, 9-9 
baud rates 9-8 
baud select registers (BAUD MSB and 

BAUD LSB) 9-24 
block diagram 9-3 
BRKDTflag 9-7 
CLOCK bit 9-8, 9-9 
clock sources 9-8 
communication control register 

(SCICCR) 9-20 
control register (SCICTL) 9-22 
control registers 9-6,9-19 
data format 9-7 
features 9-4 
idle line format 9-14 
idle line mode 9-13,9-14 
interrupts 9-7 
isosynchronous format 9-10 
isosynchronous mode 9-5,9-10 
memory map 9-6 

multiprocessor communications 9-13 
multiprocessor protocols 9-5 
operation 9-7 
operation modes 9-5 
overview 9-2 
physical description 9-2 
port control register 1 (SCIPCl) 9-29 
port control register 2 (SCIPC2) 9-30 
priority control register (SCIPRI) 9-31 
receiver data buffer register (RXBUF) 9-28 
receiver interrupt control and status register 

(RXCTL) 9-26 
Receiver Wakeup Detect (RXWAKE) 9-26 
RS-232-C example 9-17 
RS-232-C multiprocessor example 9-18 
RXRDYflag 9-7 

SCI Break Detect Flag (BRKDT) 9-27 
SCI Character Length Control Bits (SCI 

CHARO-2) 9-20 
SCI communication modes 9-9 
SCI Communications Mode Control bit 

(ASYNC/ISOSYNC) 9-20 
SCI Framing Error Flag (FE) 9-26 
SCI Internal Clock Enable (CLOCK) 9-22 
SCI Multiprocessor Mode Control bit 

(ADDRESS/IDLE WUP) 9-20 
SCI Number of Stop Bits (STOP 

BITS) 9-21 
SCI Overrun Error Flag (OE) 9-26 



lndex-6 



Index 



SCI Parity Enable bit (PARITY 

ENABLE) 9-21 
SCI Parity Error Flag (PE) 9-26 
SCI Parity Odd/Even (EVEN/ODD 

PARITY) 9-21 
SCI Receive Enable (RXENA) 9-22 
SCI Receiver Error Flag (RX ERROR) 9-27 
SCI Receiver Interrupt Enable (SCI RX INT 

ENA) 9-26 
SCI Receiver Interrupt Priority (SCI RX PRI- 
ORITY) 9-31 
SCI Receiver Ready (RXRDY) 9-27 
SCI RX PRIORITY bit 9-7 
SCI Sleep (SLEEP) 9-22 
SCI Software Reset (SCI SW RESET) 9-23 
SCI Transmit Enable (TXENA) 9-22 
SCI Transmitter Empty (TX EMPTY) 9-25 
SCI Transmitter Interrupt Priority (SCI TX 

PRIORITY) 9-31 
SCI Transmitter Ready (TXRDY) 9-25 
SCI Transmitter Ready Interrupt (SCI TX INT 

ENA) 9-25 
SCI Transmitter Wake-up (TXWAKE) 9-22 
SCI TX PRIORITY bit 9-7 
SCICLK Data Direction (SCICLK DATA 

DIR) 9-29 
SCICLK DATA IN 9-29 
SCICLK DATA IN bit 9-8 
SCICLK DATA OUT 9-29 
SCICLK FUNCTION bit 9-8, 9-9, 9-29 
SCIRXD Data Direction (SCIRXD DATA 

DIR) 9-30 
SCIRXD DATA IN 9-30 
SCIRXD DATA OUT 9-30 
SCIRXD FUNCTION 9-30 
SCITXD Data Direction (SCITXD DATA 

DIR) 9-30 
SCITXD DATA IN 9-30 
SCITXD DATA OUT 9-30 
SCITXD FUNCTION 9-30 
serial clock rates 9-8 
SLEEP bit 9-13,9-14 
transmit data buffer register (TXBUF) 9-28 
transmitter interrupt control and status reg- 
ister (TXCTL) 9-25 
TXRDY flag 9-7 
TXWAKE bit 9-14,9-15 
WUTflag 9-14 
Serial Peripheral Interface (SPI) 1-6 
block diagram 10-3 
character length 10-6 
character length control bits 

(CHARO-2) 10-11 
CLOCK POLARITY bit 10-7 
clock sources 10-7 
Configuration Control register 

(SPICCR) 10-11 
control registers 10-4, 10-10 
data format 10-6 
Emulator Suspend Enable (SPI 

ESPEN) 10-17 
Enable Network Master 

(MASTER/SLAVE) 10-13 
example 10-9 
initialization 10-8 



interrupt priority control register 

(SPIPRI) 10-17 
Interrupt Priority Select (SPI 

PRIORITY) 10-17 
interrupts 10-6 
master mode 10-7 
MASTER/SLAVE bit 10-7 
master/slave connection 10-5 
Master/Slave Transmit Enable 

(TALK) 10-13 
memory map 10-4 
operation 10-5 

operation control register (SPICTL) 10-13 
overview 1 0-2 
physical description 10-2 
port control register 1 (SPIPC1 ) 10-15 
port control register 2 (SPIPC2) 10-16 
RECEIVER OVERRUN bit 1 0-7, 1 0-13 
serial data register (SPI DAT) 10-14 
serial input buffer (SPIBUF) 10-14 
Serial Peripheral Interrupt Flag (SPI INT 

FLAG) 10-13 
Shift Clock Polarity (CLOCK 

POLARITY) 10-12 
slave mode 10-8 
SPI BIT RATE bits 10-7 
SPI Bit Rate Control Bits (SPI BIT 

RATE2-0) 10-12 
SPI INT ENA bit 10-6,10-8 
SPI INT FLAG 10-7,10-8 
SPI Interrupt Enable (SPI INT ENA) 10-13 
SPI operating modes 10-7 
SPI PRIORITY bit 10-6 
SPI SW RESET bit 10-8,10-12 
SPIBUF register 10-7 
SPICCR register 10-7 
SPICLK Data Direction (SPICLK DATA 

DIR) 10-15 
SPICLK Pin Function Select (SPICLK 

FUNCTION) 10-15 
SPICLK Pin Port Data In (SPICLK DATA 

IN) 10-15 
SPICLK Port Data Out (SPICLK DATA 

OUT) 10-15 
SPI DAT register 10-7 
SPISIMO Data Direction (SPISIMO DATA 

DIR) 10-16 
SPISIMO Pin Data In (SPISIMO DATA 

IN) 10-16 
SPISIMO Pin Data Out (SPISIMO DATA 

OUT) 10-16 
SPISIMO Pin Function Select (SPISIMO 

FUNCTION) 10-16 
SPISOMI Data Direction (SPISOMI DATA 

DIR) 10-16 
SPISOMI Pin Data In (SPISOMI DATA 

IN) 10-16 
SPISOMI Pin Data Out (SPISOMI DATA 

OUT) 10-16 
SPISOMI Pin Function Select (SPISOMI 

FUNCTION) 10-16 
TALK bit 10-8 
set 1 -8 
SETC 

Set Carry Instruction 1 2-24, 1 2-81 
Signals 



lndex-7 



Index 



CLKOUT 4-14 

CSE1 3-16,4-13 

CSE2 3-16,4-14 

CSH1 4-13 

CSH2 4-13 

CSH3 4-13 

CSPF 3-16,4-14 

EDS 3-17,3-19,3-20,4-13 

INT1 5-5 

OCF 4-14 

R/W 4-14 

RESET 3-13 

WAIT 4-14 

WPO 3-12 
SPI 1-6 
stack 3-2, 5-2 

stack operations 1 2-70, 1 2-71 , 1 2-82 
Stack Pointer (SP) 3-3, 12-63, 12-82 
Stack Pointer Relative Addressing mode 12-9 
standby mode 4-4, 4-5 
Status and Control Bits 

AD ESPEN 11-15 

AD INPUT SELECTO-2 11-11 

ADINTENA 11-6,11-13 

AD INT FLAG 11-6,11-13 

AD PRIORITY 11-6,11-15 

AD READY 11-13 

ADDRESS/IDLE WUP 9-13,9-20 

AP 6-4,6-10,6-11 

ASYNC/ISOSYNC 9-9, 9-20 

AUTOWAIT DISABLE 4-3, 4-8 

BRKDT 9-7, 9-27 

BUSY 6-4,6-7,6-10 

C 3-4 

CHARO-2 10-11 

CLOCK 9-8, 9-9, 9-22 

CLOCK POLARITY 10-7,10-12 

COLD START 4-8 

CONVERT START 11-7,11-12 

DATA7-DATA0 11-13 

EVEN/ODD PARITY 9-21 

EXE 6-4,6-10 

FE 9-26 

HALT/STANDBY 4-5,4-10 

lEl &IE2 3-4,5-2, 5-11 

IE2 3-4 

INT DATA DIR 5-6 

INT DATA OUT 5-6 

INT ENABLE 5-5 

INT FLAG 5-5 

INT PIN DATA 5-5 

INT POLARITY 5-5 

INT PRIORITY 5-5 

INT1 ENABLE 5-8 

INTl FLAG 5-8 

INTl NMI 4-9 

INTl PIN DATA 5-8 

INTl POLARITY 5-8 

INTl PRIORITY 5-8 

INT2 DATA DIR 5-9 

INT2 DATA OUT 5-9 

INT2 ENABLE 5-9 

INT2 FLAG 5-9 

INT2 PIN DATA 5-9 

INT2 POLARITY 5-9 

INT2 PRIORITY 5-9 



INT3 DATA DIR 5-10 

INT3 DATA OUT 5-10 

INT3 ENABLE 5-10 

INT3FLAG 5-10 

INT3 PIN DATA 5-10 

I NT3 POLARITY 5-10 

INT3 PRIORITY 5-10 

MASTER/SLAVE 10-7,10-13 

IVIC PIN DATA 4-7 

MC PIN WPO bit 4-7 

MEMORY DISABLE 3-20,4-8 

mP/mC MODE 4-7 

N 3-4 

OE 9-26 

OSC FLT DISABLE 4-3, 4-9 

OSC FLT FLAG 4-3, 4-7 

OSC FLT RST ENA 4-3, 4-9 

OSC POWER 4-6, 4-8 

PARITY ENABLE 9-21 

PE 9-26 

PF AUTO WAIT 4-3, 4-7 

PORT E DATA AN 7-PORT E DATA AN 

11-14 
PORT E INPUT ENA 7-PORT E INPUT ENA 

11-14 
POWERDOWN/IDLE 8-13 
PRIVILEGE DISABLE 4-2, 4-9 
PWRDWN/IDLE 4-5,4-10 
RECEIVER OVERRUN 10-13 
REFVOLTSELECTO-2 11-11 
RX ERROR 9-27 
RXENA 9-22 
RXRDY 9-7, 9-27 
RXWAKE 9-26 
SAMPLE START 11-7,11-12 
SCI CHARO-2 9-20 
SCI Emulator Suspend Enable (SCI 

ESPEN) 9-31 
SCI ESPEN 9-31 
SCI RX INT ENA 9-26 
SCI RX PRIORITY 9-7, 9-31 
SCI SW RESET 9-23 
SCI TX INT ENA 9-25 
SCI TX PRIORITY 9-7, 9-31 
SCICLK DATA DIR 9-29 
SCICLK DATA IN 9-8, 9-29 
SCICLK DATA OUT 9-29 
SCICLK FUNCTION 9-8, 9-9, 9-29 
SCI RXD DATA DIR 9-30 
SCIRXDDATAIN 9-30 
SCI RXD DATA OUT 9-30 
SCIRXD FUNCTION 9-30 
SCITXD DATA DIR 9-30 
SCITXDDATAIN 9-30 
SCITXD DATA OUT 9-30 
SCITXD FUNCTION 9-30 
SLEEP 9-13,9-14,9-22 
SPI BIT RATEO-2 10-12 
SPI BIT RATE2-0 10-7 
SPI ESPEN 10-17 
SPI INT ENA 10-6,10-8,10-13 
SPI INT FLAG 10-7,10-8,10-13 
SPI PRIORITY 10-6,10-17 
SPI RECEIVER OVERRUN 10-7 
SPI SW RESET 10-8,10-12 
SPICLK DATA DIR 10-15 



lndex-8 



Index 



SPICLKDATAIN 10-15 

SPICLK DATA OUT 10-15 

SPICLK FUNCTION 10-15 

SPISIMO DATA DIR 10-16 

SPISIMO DATA IN 10-16 

SPISIMO DATA OUT 10-16 

SPISIMO FUNCTION 10-16 

SPISOMI DATA DIR 10-16 

SPISOMI DATA IN 10-16 

SPISOMI DATA OUT 10-16 

SPISOMI FUNCTION 10-16 

STOP BITS 9-21 

TALK 10-8,10-13 

TX EMPTY 9-25 

TXENA 9-22 

TXRDY 9-7, 9-25 

TXWAKE 9-14,9-15,9-22 

Tl INPUT SELECT 0-2 7-24 

T1 MODE. 7-30 

Tl OVRFL INTENA 7-25 

Tl OVRFL INT FLAG 7-25 

Tl PRIORITY 7-33 

Tl SW RESET 7-25 

T1CR0UTENA 7-30 

T1CRRSTENA 7-29 

T1C1 INTENA 7-27 

TlCl INT FLAG 7-27 

TlCl OUT ENA 7-30 

T1C1 RST ENA 7-30 

T1C2INTENA 7-27 

T1C2 INT FLAG 7-28 

T1C2 0UTENA 7-30 

Tl EDGE DET ENA 7-29 

Tl EDGE INT ENA 7-27 

Tl EDGE INT FLAG 7-28 

Tl EDGE POLARITY 7-8, 7-29 

TIEVT DATA DIR 7-31 

T1EVTDATAIN 7-31 

Tl EVT DATA OUT 7-31 

TIEVT FUNCTION 7-31 

T1IC/CR DATA DIR 7-32 

T1IC/CR DATAIN 7-32 

T1IC/CR DATA OUT 7-32 

TliC/CR FUNCTION 7-32 

T1PWM DATA DIR 7-32 

T1PWM DATAIN 7-32 

T1PWM DATA OUT 7-32 

TIPWM FUNCTION 7-32 

T2 INPUT SELECT 0,1 8-16 

T2 INPUT SELECT 0-1 8-8 

T2 MODE 8-20 

T2 OVRFL INT ENA 8-16 

T2 OVRFL INT FLAG 8-9,8-16 

T2 PRIORITY 8-23 

T2 SW RESET 8-10,8-16 

T2C1 INTENA 8-17 

T2C1 INT FLAG 8-10,8-17 

T2C1 OUT ENA 8-20 

T2C1 RST ENA 8-20 

T2C2INTENA 8-17 

T2C2 INT FLAG 8-11,8-18 

T2C2 OUT ENA 8-20 

T2EDGE1 DET ENA 8-9,8-12,8-19 

T2EDGE1 INT ENA 8-17 

T2EDGE1 INT FLAG 8-9,8-12,8-18 

T2EDGE1 INTERRUPT FLAG 8-9 



T2EDGE1 OUT ENA 8-9, 8-20 

T2EDGE1 POLARITY 8-9,8-19 

T2EDGE1 RST ENA 8-9,8-19 

T2EDGE2 DET ENA 8-19 

T2EDGE2 INT ENA 8-17 

T2EDGE2 INT FLAG 8-9,8-11,8-18 

T2EDGE2 POLARITY 8-20 

T2EVT DATA DIR 8-21 

T2EVTDATAIN 8-21 

T2EVT DATA OUT 8-21 

T2EVT FUNCTION 8-21 

T2iC1/CR DATA DIR 8-22 

T2IC1/CR DATAIN 8-22 

T2IC1/CR DATA OUT 8-22 

T2IC1/CR FUNCTION 8-22 

T2IC2/PWM DATA DIR 8-22 

T2IC2/PWM DATA IN 8-22 

T2IC2/PWM DATA OUT 8-22 

T2IC2/PWM FUNCTION 8-22 

T20VRFLINTENA 8-9 

V 3-4 

WD INPUT SELECT 0-2 7-24 

WD OVRFL INT ENA 7-25 

WD OVRFL INT FLAG 7-25 

WD OVRFL RST ENA 7-26 

WD OVRFL TAP SEL 7-24 

WUT 9-14 

W1W0 6-4,6-10 

Z 3-4 
Status Register (ST) 3-4,5-2,12-64 
STSP 

Store Stack Pointer Instruction 12-25, 
12-82 
SUB 

Subtract Instruction 12-25,12-83 
subroutine instructions 12-36, 12-37, 12-77, 

12-85 
subtraction instructions 1 2-45, 1 2-49, 1 2-78, 

12-79, 12-80, 12-83 
SWAP 

Swap Nibbles Instruction 12-25, 12-84 
symbols, used in this manual 1 -8 
system configuration 4-2 
System Control and Configuration Register 

(SCCRO) 4-2, 4-7 
System Control and Configuration Register 1 

(SCCR1) 4-2,4-8 
System Control and Configuration Register 2 

(SCCR2) 4-2,4-9 
system control registers 4-7 
system interface example 4-17 



Tl EEPROM Programmer 14-17 

Timer 1 1-6,7-2 
capture 7-6 
clock prescaler 7-1 1 
compare 7-6 
control registers 7-5 
counter duration 7-12 
counter resolution 7-12 



lndex-9 



Index 



dual compare mode 7-9 
edge detection 7-13 
external clock input 7-1 1 
general purpose timer 7-7 
interrupts 7-3 
operating modes 7-6, 7-7 
pulse accumulation 7-12 
reset sources 7-8 
Tl EVT 7-3 
T1IC/CR 7-3 
T1PWM 7-3 

watchdog counter memory map 7-5 
watchdog counter overflow rates 7-1 2 
Timer 1 Compare 1 Interrupt Enable bit (Tl CI INT 

ENA) 7-27 
Timer 1 Compare 1 Interrupt Flag (T1C1 INT 

FLAG) 7-27 
Timer 1 Compare 1 Reset Enable bit (Tl CI RST 

ENA) 7-30 
Timer 1 Compare 2 Interrupt Enable bit (Tl C2 INT 

ENA) 7-27 
Timer 1 Compare 2 Interrupt Flag bit (T1C2 INT 

FLAG) 7-28 
Timer 1 Counter Control Register 1 

(T1CTL1) 7-24 
Timer 1 Counter Control Register 2 

(T1CTL2) 7-25 
Timer 1 Counter Control Register 3 

(T1CTL3) 7-27 
Timer 1 Counter Control Register 4 

(T1CTL4) 7-29 
Timer 1 Edge Detect Enable bit (Tl EDGE DET 

ENA) 7-29 
Timer 1 Edge Interrupt Enable bit (T1EDGE INT 

ENA) 7-27 
Timer 1 Edge Interrupt Flag bit (Tl EDGE INT 

FLAG) 7-28 
Timer 1 Edge Polarity bit (Tl EDGE 

POLARITY) 7-29 
Timer 1 Event-Pin Data Direction bit (Tl EVT 

DATADIR) 7-31 
Timer 1 External Edge Output Enable bit (T1CR 

OUT ENA) 7-30 
Timer 1 External Reset Enable bit (T1CR RST 

ENA) 7-29 
Timer 1 Input Select bits (Tl INPUT SELECT 

0-2) 7-24 
Timer 1 Interrupt Priority Control Register 

(T1PRI) 7-33 
Timer 1 Interrupt Priority Select bit (Tl PRIOR- 
ITY) 7-33 
Timer 1 Mode Select bit (Tl MODE) 7-30 
Timer 1 Output-Compare Output Enable 1 bit 

(T1C1 OUT ENA) 7-30 
Timer 1 Output-Compare Output Enable 2 bit 

(T1C2 0UTENA) 7-30 
Timer 1 Overflow Interrupt Enable bit (Tl OVRFL 

INT ENA) 7-25 
Timer 1 Overflow Interrupt Flag (Tl OVRFL INT 

FLAG) 7-25 
Timer 1 Port Control Register 1 (T1PC1) 7-31 
Timer 1 Port Control Register 2 (Tl PC2) 7-32 
Timer 1 Software Reset bit (Tl SW 

RESET) 7-25 
Timer 2 1-6 

block diagram 8-2 



capture register 8-10 

capture/compare register 8-11 

clearing interrupt flags 8-13 

clock sources 8-8 

compare register 8-10 

control register 1 (T2CTL1 ) 8-16 

control register 2 (T2CTL2) 8-17 

control register 3 (T2CTL3) 8-19 

control registers 8-4,8-13 

dual capture mode 8-4, 8-7 

dual compare mode 8-3, 8-5 

edge detection in dual capture mode 8-9 

edge detection in dual compare mode 8-9 

event counter mode 8-8 

features 8-3 

I/O pin functions 8-12 

I/O pins 8-2 

interrupt priority register 2 (T2PRI) 8-23 

interrupts 8-12 

maximum counter duration 8-8 

memory map 8-4 

operating modes 8-3, 8-5 

port control register 1 (T2PC1) 8-21 

port control register 2 (T2PC2) 8-22 

power-down modes 8-13 

POWERDOWN/IDLEbit 8-13 

pulse accumulator mode 8-8 

Timer 2 Compare 1 Interrupt Enable (T2C1 

INT ENA) 8-17 
Timer 2 Edge 1 Detect Enable (T2EDGE1 

DET ENA) 8-19 
Timer 2 Edge 1 Detect Output Enable 

(T2EDGE1 OUT ENA) 8-20 
Timer 2 Edge 1 Detect Reset Enable 

(T2EDGE1 RST ENA) 8-19 
Timer 2 Edge 1 Polarity Select (T2EDGE1 

POLARITY) 8-19 
Timer 2 Edge 2 Interrupt Flag (T2EDGE2 INT 

FLAG) 8-18 
Timer 2 Edge 2 Polarity Select (T2EDGE2 

POLARITY) 8-20 
Timer 2 Event Pin Data Direction (T2EVT 

DATADIR) 8-21 
Timer 2 Event Pin Data In (T2EVT DATA 

IN) 8-21 
Timer 2 Event Pin Data Out (T2EVT DATA 

OUT) 8-21 
Timer 2 Event Pin Function Select (T2EVT 

FUNCTION) 8-21 
Timer 2 External Edge 1 Interrupt (T2EDGE1 

INT ENA) 8-17 
Timer 2 External Edge 1 Interrupt (T2EDGE1 

INT FLAG) 8-18 
Timer 2 External Edge 2 Detect Enable 

(T2EDGE2 DET ENA) 8-19 
Timer 2 External Edge 2 Interrupt Enable 

(T2EDGE2 INT ENA) 8-17 
Timer 2 IC1/CR Data Direction (T2IC1/CR 

DATADIR) 8-22 
Timer 2 IC1/CR Data In (T2IC1/CR DATA 

IN) 8-22 
Timer 2 IC1/CR Data Out (T2IC1/CR DATA 

OUT) 8-22 
Timer 2 IC1/CR Function Select (T2IC1/CR 

FUNCTION) 8-22 



lndex-10 



Index 



Timer 2 IC2/PWM Data Direction 

(T2IC2/PWM DATA DIR) 8-22 
Timer 2 IC2/PWiVl Data In (T2IC2/PWIV1 

DATA IN) 8-22 
Timer 2 IC2/PWM Data Out (T2IC2/PWM 

DATA OUT) 8-22 
Timer 2 IC2/PWM Function (T2iC2/PWi\/l 

FUNCTION) 8-22 
Timer 2 Input Select bits (T2 INPUT SELECT 

0,1) 8-16 
Timer 2 Interrupt Priority Select (T2 PRIOR- 
ITY) 8-23 
Timer 2 Mode Select {T2 MODE) 8-20 
Timer 2 Output Compare 1 Enable (T2C1 

OUT ENA) 8-20 
Timer 2 Output Compare 1 Interrupt (T2C1 

INT FLAG) 8-17 
Timer 2 Output Compare 1 Reset (T2C1 RST 

ENA) 8-20 
Timer 2 Output Compare 2 Enable (T2C2 

OUT ENA) 8-20 
Timer 2 Output Compare 2 Interrupt Enable 

(T2C2INTENA) 8-17 
Timer 2 Output Compare 2 Interrupt Flag 

(T2C2 INT FLAG) 8-18 
Timer 2 Overflow Interrupt Enable (T2 

OVRFLINTENA) 8-16 
Timer 2 Overflow Interrupt Flag (T2 OVRFL 

INT FLAG) 8-16 
Timer 2 Software Reset bit (T2 SW 

RESET) 8-16 
T2 OVRFL INT FLAG bit 8-9 
T2SW RESET bit 8-10 
T2C1 INT FLAG bit 8-10 
T2C2 INT FLAG bit 8-11 
T2EDGE1 DETENAbit 8-12 
T2EDGE1 INT FLAG bit 8-12 
T2EDGE2 INT FLAG bit 8-11 
T2EDGE2 POLARITY bit 8-9 
T2IC1/CRpin 8-12 
T2IC2/PWM pin 8-10 
T20VRFL INT ENA bit 8-9 
16-bit resettable up counter 8-9 
timer 2 module 8-1 
timer, watchdog 1 -6 
TMS370 devices 15-2 
TMS370 family devices summary 2-1 
TMS370 family features 1-3 
TMS370Cx10 features 2-3 
TMS370Cx50 features 2-4 
TRAP 

Trap to Subroutine Instruction 12-85 
TRAPn 

Trap to Subroutine Instruction 12-25 
trap vectors 3-11 
TST 

Test Instruction 12-25 
Test, Set Flags from Register 
Instruction 12-86 
T1 EVT Pin Data In bit (T1 EVT DATA IN) 7-31 
T1 EVT Pin Data Out bit (T1 EVT DATA 

OUT) 7-31 
T1 EVT Pin Function Select bit (T1 EVT FUNC- 
TION) 7-31 
T1IC/CR Pin Data Direction bit (T1IC/CR DATA 
DIR) 7-32 



T1IC/CR Pin Data In bit (T1IC/CR DATA 

IN) 7-32 
T1 IC/CR Pin Data Out bit (T1 IC/CR DATA 

OUT) 7-32 
TliC/CR Pin Function Select bit (T1 IC/CR 

FUNCTION) 7-32 
T1 PMW Function Select bit (T1 PWM FUNC- 
TION) 7-32 
T1PWM Data Direction bit (T1 PWM DATA 

DIR) 7-32 
T1 PWM Pin Data In 1 bit (T1 PWM DATA 

IN) 7-32 
T1 PWM Pin Data Out bit (Tl PWM DATA 

OUT) 7-32 



V 



vector addresses, interrupts 5-4 



w 



WAIT input (WAIT) signal 4-14 

WAIT pin 4-3 

wait states 4-3 

watchdog counter memory map 7-5 

Watchdog Input Select bits (WD INPUT SELECT 

0-2) 7-24 
Watchdog Overflow Interrupt Enable bit (WD 

OVRFLINTENA) 7-25 
Watchdog Overflow Interrupt Flag (WD OVRFL 

INT FLAG) 7-25 
Watchdog Overflow Reset Enable bit (WD OVRFL 

RST ENA) 7-26 
Watchdog Overflow Tap Select bit (WD OVRFL 

TAP SEL) 7-24 
Watchdog Timer 1 -6, 7-17 

control registers 7-22 

counter 7-17 

halt 7-21 

initialization example 7-19 

low-power modes 7-21 

non-watchdog mode 7-18 

overflow flag 7-20 

power- up reset 7-19 

reset frequency 7-20 

reset key 7-18 

standby 7-21 

watchdog mode 7-17 

WD OVRFL INT FLAG 7-18 

WD OVRFL RST ENA 7-17,7-18,7-19 

WD OVRFL TAP SEL 7-17,7-20 

WORST 7-18 
WPR (register) 6-2 
Write Protect Override (WPO) 3-12 
write protecting Program EEPROM 6-12 
write protection override (WPO) mode 6-2 
Write Protection Register (WPR) 6-3 
write-protection bits 6-3 
Writel /WriteO (W1 WO) bit 6-4, 6-10 



lndex-11 



Index 

X z 

XCHB Zero (Z) bit 3-4 

Exchange with Register B 
Instruction 12-25,12-87 
XDS 1-2,14-6 

ordering information 16-13 1 

XDS System 14-6 ' 

XOR 

Exclusive Or Instruction 1 2-25, 1 2-88 1 6-bit register access 7-22, 8-14 



lndex-12 



^ 



Texas 
Instruments 



Printed in U.S.A. 
IVIarch 1988 



SPNS01